linux/drivers/scsi/sym53c8xx_2/sym_fw2.h
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   1/*
   2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family 
   3 * of PCI-SCSI IO processors.
   4 *
   5 * Copyright (C) 1999-2001  Gerard Roudier <groudier@free.fr>
   6 *
   7 * This driver is derived from the Linux sym53c8xx driver.
   8 * Copyright (C) 1998-2000  Gerard Roudier
   9 *
  10 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 
  11 * a port of the FreeBSD ncr driver to Linux-1.2.13.
  12 *
  13 * The original ncr driver has been written for 386bsd and FreeBSD by
  14 *         Wolfgang Stanglmeier        <wolf@cologne.de>
  15 *         Stefan Esser                <se@mi.Uni-Koeln.de>
  16 * Copyright (C) 1994  Wolfgang Stanglmeier
  17 *
  18 * Other major contributions:
  19 *
  20 * NVRAM detection and reading.
  21 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
  22 *
  23 *-----------------------------------------------------------------------------
  24 *
  25 * This program is free software; you can redistribute it and/or modify
  26 * it under the terms of the GNU General Public License as published by
  27 * the Free Software Foundation; either version 2 of the License, or
  28 * (at your option) any later version.
  29 *
  30 * This program is distributed in the hope that it will be useful,
  31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  33 * GNU General Public License for more details.
  34 *
  35 * You should have received a copy of the GNU General Public License
  36 * along with this program; if not, write to the Free Software
  37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  38 */
  39
  40/*
  41 *  Scripts for SYMBIOS-Processor
  42 *
  43 *  We have to know the offsets of all labels before we reach 
  44 *  them (for forward jumps). Therefore we declare a struct 
  45 *  here. If you make changes inside the script,
  46 *
  47 *  DONT FORGET TO CHANGE THE LENGTHS HERE!
  48 */
  49
  50/*
  51 *  Script fragments which are loaded into the on-chip RAM 
  52 *  of 825A, 875, 876, 895, 895A, 896 and 1010 chips.
  53 *  Must not exceed 4K bytes.
  54 */
  55struct SYM_FWA_SCR {
  56        u32 start               [ 14];
  57        u32 getjob_begin        [  4];
  58        u32 getjob_end          [  4];
  59#ifdef SYM_CONF_TARGET_ROLE_SUPPORT
  60        u32 select              [  6];
  61#else
  62        u32 select              [  4];
  63#endif
  64#if     SYM_CONF_DMA_ADDRESSING_MODE == 2
  65        u32 is_dmap_dirty       [  4];
  66#endif
  67        u32 wf_sel_done         [  2];
  68        u32 sel_done            [  2];
  69        u32 send_ident          [  2];
  70#ifdef SYM_CONF_IARB_SUPPORT
  71        u32 select2             [  8];
  72#else
  73        u32 select2             [  2];
  74#endif
  75        u32 command             [  2];
  76        u32 dispatch            [ 28];
  77        u32 sel_no_cmd          [ 10];
  78        u32 init                [  6];
  79        u32 clrack              [  4];
  80        u32 datai_done          [ 10];
  81        u32 datai_done_wsr      [ 20];
  82        u32 datao_done          [ 10];
  83        u32 datao_done_wss      [  6];
  84        u32 datai_phase         [  4];
  85        u32 datao_phase         [  6];
  86        u32 msg_in              [  2];
  87        u32 msg_in2             [ 10];
  88#ifdef SYM_CONF_IARB_SUPPORT
  89        u32 status              [ 14];
  90#else
  91        u32 status              [ 10];
  92#endif
  93        u32 complete            [  6];
  94        u32 complete2           [ 12];
  95        u32 done                [ 14];
  96        u32 done_end            [  2];
  97        u32 complete_error      [  4];
  98        u32 save_dp             [ 12];
  99        u32 restore_dp          [  8];
 100        u32 disconnect          [ 12];
 101#ifdef SYM_CONF_IARB_SUPPORT
 102        u32 idle                [  4];
 103#else
 104        u32 idle                [  2];
 105#endif
 106#ifdef SYM_CONF_IARB_SUPPORT
 107        u32 ungetjob            [  6];
 108#else
 109        u32 ungetjob            [  4];
 110#endif
 111#ifdef SYM_CONF_TARGET_ROLE_SUPPORT
 112        u32 reselect            [  4];
 113#else
 114        u32 reselect            [  2];
 115#endif
 116        u32 reselected          [ 22];
 117        u32 resel_scntl4        [ 20];
 118        u32 resel_lun0          [  6];
 119#if   SYM_CONF_MAX_TASK*4 > 512
 120        u32 resel_tag           [ 26];
 121#elif SYM_CONF_MAX_TASK*4 > 256
 122        u32 resel_tag           [ 20];
 123#else
 124        u32 resel_tag           [ 16];
 125#endif
 126        u32 resel_dsa           [  2];
 127        u32 resel_dsa1          [  4];
 128        u32 resel_no_tag        [  6];
 129        u32 data_in             [SYM_CONF_MAX_SG * 2];
 130        u32 data_in2            [  4];
 131        u32 data_out            [SYM_CONF_MAX_SG * 2];
 132        u32 data_out2           [  4];
 133        u32 pm0_data            [ 12];
 134        u32 pm0_data_out        [  6];
 135        u32 pm0_data_end        [  6];
 136        u32 pm1_data            [ 12];
 137        u32 pm1_data_out        [  6];
 138        u32 pm1_data_end        [  6];
 139};
 140
 141/*
 142 *  Script fragments which stay in main memory for all chips 
 143 *  except for chips that support 8K on-chip RAM.
 144 */
 145struct SYM_FWB_SCR {
 146        u32 start64             [  2];
 147        u32 no_data             [  2];
 148#ifdef SYM_CONF_TARGET_ROLE_SUPPORT
 149        u32 sel_for_abort       [ 18];
 150#else
 151        u32 sel_for_abort       [ 16];
 152#endif
 153        u32 sel_for_abort_1     [  2];
 154        u32 msg_in_etc          [ 12];
 155        u32 msg_received        [  4];
 156        u32 msg_weird_seen      [  4];
 157        u32 msg_extended        [ 20];
 158        u32 msg_bad             [  6];
 159        u32 msg_weird           [  4];
 160        u32 msg_weird1          [  8];
 161
 162        u32 wdtr_resp           [  6];
 163        u32 send_wdtr           [  4];
 164        u32 sdtr_resp           [  6];
 165        u32 send_sdtr           [  4];
 166        u32 ppr_resp            [  6];
 167        u32 send_ppr            [  4];
 168        u32 nego_bad_phase      [  4];
 169        u32 msg_out             [  4];
 170        u32 msg_out_done        [  4];
 171        u32 data_ovrun          [  2];
 172        u32 data_ovrun1         [ 22];
 173        u32 data_ovrun2         [  8];
 174        u32 abort_resel         [ 16];
 175        u32 resend_ident        [  4];
 176        u32 ident_break         [  4];
 177        u32 ident_break_atn     [  4];
 178        u32 sdata_in            [  6];
 179        u32 resel_bad_lun       [  4];
 180        u32 bad_i_t_l           [  4];
 181        u32 bad_i_t_l_q         [  4];
 182        u32 bad_status          [  6];
 183        u32 pm_handle           [ 20];
 184        u32 pm_handle1          [  4];
 185        u32 pm_save             [  4];
 186        u32 pm0_save            [ 12];
 187        u32 pm_save_end         [  4];
 188        u32 pm1_save            [ 14];
 189
 190        /* WSR handling */
 191        u32 pm_wsr_handle       [ 38];
 192        u32 wsr_ma_helper       [  4];
 193
 194        /* Data area */
 195        u32 zero                [  1];
 196        u32 scratch             [  1];
 197        u32 pm0_data_addr       [  1];
 198        u32 pm1_data_addr       [  1];
 199        u32 done_pos            [  1];
 200        u32 startpos            [  1];
 201        u32 targtbl             [  1];
 202};
 203
 204/*
 205 *  Script fragments used at initialisations.
 206 *  Only runs out of main memory.
 207 */
 208struct SYM_FWZ_SCR {
 209        u32 snooptest           [  6];
 210        u32 snoopend            [  2];
 211};
 212
 213static struct SYM_FWA_SCR SYM_FWA_SCR = {
 214/*--------------------------< START >----------------------------*/ {
 215        /*
 216         *  Switch the LED on.
 217         *  Will be patched with a NO_OP if LED
 218         *  not needed or not desired.
 219         */
 220        SCR_REG_REG (gpreg, SCR_AND, 0xfe),
 221                0,
 222        /*
 223         *      Clear SIGP.
 224         */
 225        SCR_FROM_REG (ctest2),
 226                0,
 227        /*
 228         *  Stop here if the C code wants to perform 
 229         *  some error recovery procedure manually.
 230         *  (Indicate this by setting SEM in ISTAT)
 231         */
 232        SCR_FROM_REG (istat),
 233                0,
 234        /*
 235         *  Report to the C code the next position in 
 236         *  the start queue the SCRIPTS will schedule.
 237         *  The C code must not change SCRATCHA.
 238         */
 239        SCR_LOAD_ABS (scratcha, 4),
 240                PADDR_B (startpos),
 241        SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
 242                SIR_SCRIPT_STOPPED,
 243        /*
 244         *  Start the next job.
 245         *
 246         *  @DSA     = start point for this job.
 247         *  SCRATCHA = address of this job in the start queue.
 248         *
 249         *  We will restore startpos with SCRATCHA if we fails the 
 250         *  arbitration or if it is the idle job.
 251         *
 252         *  The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS 
 253         *  is a critical path. If it is partially executed, it then 
 254         *  may happen that the job address is not yet in the DSA 
 255         *  and the next queue position points to the next JOB.
 256         */
 257        SCR_LOAD_ABS (dsa, 4),
 258                PADDR_B (startpos),
 259        SCR_LOAD_REL (temp, 4),
 260                4,
 261}/*-------------------------< GETJOB_BEGIN >---------------------*/,{
 262        SCR_STORE_ABS (temp, 4),
 263                PADDR_B (startpos),
 264        SCR_LOAD_REL (dsa, 4),
 265                0,
 266}/*-------------------------< GETJOB_END >-----------------------*/,{
 267        SCR_LOAD_REL (temp, 4),
 268                0,
 269        SCR_RETURN,
 270                0,
 271}/*-------------------------< SELECT >---------------------------*/,{
 272        /*
 273         *  DSA contains the address of a scheduled
 274         *      data structure.
 275         *
 276         *  SCRATCHA contains the address of the start queue  
 277         *      entry which points to the next job.
 278         *
 279         *  Set Initiator mode.
 280         *
 281         *  (Target mode is left as an exercise for the reader)
 282         */
 283#ifdef SYM_CONF_TARGET_ROLE_SUPPORT
 284        SCR_CLR (SCR_TRG),
 285                0,
 286#endif
 287        /*
 288         *      And try to select this target.
 289         */
 290        SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select),
 291                PADDR_A (ungetjob),
 292        /*
 293         *  Now there are 4 possibilities:
 294         *
 295         *  (1) The chip loses arbitration.
 296         *  This is ok, because it will try again,
 297         *  when the bus becomes idle.
 298         *  (But beware of the timeout function!)
 299         *
 300         *  (2) The chip is reselected.
 301         *  Then the script processor takes the jump
 302         *  to the RESELECT label.
 303         *
 304         *  (3) The chip wins arbitration.
 305         *  Then it will execute SCRIPTS instruction until 
 306         *  the next instruction that checks SCSI phase.
 307         *  Then will stop and wait for selection to be 
 308         *  complete or selection time-out to occur.
 309         *
 310         *  After having won arbitration, the SCRIPTS  
 311         *  processor is able to execute instructions while 
 312         *  the SCSI core is performing SCSI selection.
 313         */
 314        /*
 315         *      Initialize the status registers
 316         */
 317        SCR_LOAD_REL (scr0, 4),
 318                offsetof (struct sym_ccb, phys.head.status),
 319        /*
 320         *  We may need help from CPU if the DMA segment 
 321         *  registers aren't up-to-date for this IO.
 322         *  Patched with NOOP for chips that donnot 
 323         *  support DAC addressing.
 324         */
 325#if     SYM_CONF_DMA_ADDRESSING_MODE == 2
 326}/*-------------------------< IS_DMAP_DIRTY >--------------------*/,{
 327        SCR_FROM_REG (HX_REG),
 328                0,
 329        SCR_INT ^ IFTRUE (MASK (HX_DMAP_DIRTY, HX_DMAP_DIRTY)),
 330                SIR_DMAP_DIRTY,
 331#endif
 332}/*-------------------------< WF_SEL_DONE >----------------------*/,{
 333        SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)),
 334                SIR_SEL_ATN_NO_MSG_OUT,
 335}/*-------------------------< SEL_DONE >-------------------------*/,{
 336        /*
 337         *  C1010-33 errata work-around.
 338         *  Due to a race, the SCSI core may not have 
 339         *  loaded SCNTL3 on SEL_TBL instruction.
 340         *  We reload it once phase is stable.
 341         *  Patched with a NOOP for other chips.
 342         */
 343        SCR_LOAD_REL (scntl3, 1),
 344                offsetof(struct sym_dsb, select.sel_scntl3),
 345}/*-------------------------< SEND_IDENT >-----------------------*/,{
 346        /*
 347         *  Selection complete.
 348         *  Send the IDENTIFY and possibly the TAG message 
 349         *  and negotiation message if present.
 350         */
 351        SCR_MOVE_TBL ^ SCR_MSG_OUT,
 352                offsetof (struct sym_dsb, smsg),
 353}/*-------------------------< SELECT2 >--------------------------*/,{
 354#ifdef SYM_CONF_IARB_SUPPORT
 355        /*
 356         *  Set IMMEDIATE ARBITRATION if we have been given 
 357         *  a hint to do so. (Some job to do after this one).
 358         */
 359        SCR_FROM_REG (HF_REG),
 360                0,
 361        SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
 362                8,
 363        SCR_REG_REG (scntl1, SCR_OR, IARB),
 364                0,
 365#endif
 366        /*
 367         *  Anticipate the COMMAND phase.
 368         *  This is the PHASE we expect at this point.
 369         */
 370        SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)),
 371                PADDR_A (sel_no_cmd),
 372}/*-------------------------< COMMAND >--------------------------*/,{
 373        /*
 374         *  ... and send the command
 375         */
 376        SCR_MOVE_TBL ^ SCR_COMMAND,
 377                offsetof (struct sym_dsb, cmd),
 378}/*-------------------------< DISPATCH >-------------------------*/,{
 379        /*
 380         *  MSG_IN is the only phase that shall be 
 381         *  entered at least once for each (re)selection.
 382         *  So we test it first.
 383         */
 384        SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
 385                PADDR_A (msg_in),
 386        SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)),
 387                PADDR_A (datao_phase),
 388        SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)),
 389                PADDR_A (datai_phase),
 390        SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)),
 391                PADDR_A (status),
 392        SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)),
 393                PADDR_A (command),
 394        SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)),
 395                PADDR_B (msg_out),
 396        /*
 397         *  Discard as many illegal phases as 
 398         *  required and tell the C code about.
 399         */
 400        SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)),
 401                16,
 402        SCR_MOVE_ABS (1) ^ SCR_ILG_OUT,
 403                HADDR_1 (scratch),
 404        SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)),
 405                -16,
 406        SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)),
 407                16,
 408        SCR_MOVE_ABS (1) ^ SCR_ILG_IN,
 409                HADDR_1 (scratch),
 410        SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)),
 411                -16,
 412        SCR_INT,
 413                SIR_BAD_PHASE,
 414        SCR_JUMP,
 415                PADDR_A (dispatch),
 416}/*-------------------------< SEL_NO_CMD >-----------------------*/,{
 417        /*
 418         *  The target does not switch to command 
 419         *  phase after IDENTIFY has been sent.
 420         *
 421         *  If it stays in MSG OUT phase send it 
 422         *  the IDENTIFY again.
 423         */
 424        SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
 425                PADDR_B (resend_ident),
 426        /*
 427         *  If target does not switch to MSG IN phase 
 428         *  and we sent a negotiation, assert the 
 429         *  failure immediately.
 430         */
 431        SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
 432                PADDR_A (dispatch),
 433        SCR_FROM_REG (HS_REG),
 434                0,
 435        SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
 436                SIR_NEGO_FAILED,
 437        /*
 438         *  Jump to dispatcher.
 439         */
 440        SCR_JUMP,
 441                PADDR_A (dispatch),
 442}/*-------------------------< INIT >-----------------------------*/,{
 443        /*
 444         *  Wait for the SCSI RESET signal to be 
 445         *  inactive before restarting operations, 
 446         *  since the chip may hang on SEL_ATN 
 447         *  if SCSI RESET is active.
 448         */
 449        SCR_FROM_REG (sstat0),
 450                0,
 451        SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
 452                -16,
 453        SCR_JUMP,
 454                PADDR_A (start),
 455}/*-------------------------< CLRACK >---------------------------*/,{
 456        /*
 457         *  Terminate possible pending message phase.
 458         */
 459        SCR_CLR (SCR_ACK),
 460                0,
 461        SCR_JUMP,
 462                PADDR_A (dispatch),
 463}/*-------------------------< DATAI_DONE >-----------------------*/,{
 464        /*
 465         *  Save current pointer to LASTP.
 466         */
 467        SCR_STORE_REL (temp, 4),
 468                offsetof (struct sym_ccb, phys.head.lastp),
 469        /*
 470         *  If the SWIDE is not full, jump to dispatcher.
 471         *  We anticipate a STATUS phase.
 472         */
 473        SCR_FROM_REG (scntl2),
 474                0,
 475        SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
 476                PADDR_A (datai_done_wsr),
 477        SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)),
 478                PADDR_A (status),
 479        SCR_JUMP,
 480                PADDR_A (dispatch),
 481}/*-------------------------< DATAI_DONE_WSR >-------------------*/,{
 482        /*
 483         *  The SWIDE is full.
 484         *  Clear this condition.
 485         */
 486        SCR_REG_REG (scntl2, SCR_OR, WSR),
 487                0,
 488        /*
 489         *  We are expecting an IGNORE RESIDUE message 
 490         *  from the device, otherwise we are in data 
 491         *  overrun condition. Check against MSG_IN phase.
 492         */
 493        SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
 494                SIR_SWIDE_OVERRUN,
 495        SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
 496                PADDR_A (dispatch),
 497        /*
 498         *  We are in MSG_IN phase,
 499         *  Read the first byte of the message.
 500         *  If it is not an IGNORE RESIDUE message,
 501         *  signal overrun and jump to message 
 502         *  processing.
 503         */
 504        SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
 505                HADDR_1 (msgin[0]),
 506        SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)),
 507                SIR_SWIDE_OVERRUN,
 508        SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)),
 509                PADDR_A (msg_in2),
 510        /*
 511         *  We got the message we expected.
 512         *  Read the 2nd byte, and jump to dispatcher.
 513         */
 514        SCR_CLR (SCR_ACK),
 515                0,
 516        SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
 517                HADDR_1 (msgin[1]),
 518        SCR_CLR (SCR_ACK),
 519                0,
 520        SCR_JUMP,
 521                PADDR_A (dispatch),
 522}/*-------------------------< DATAO_DONE >-----------------------*/,{
 523        /*
 524         *  Save current pointer to LASTP.
 525         */
 526        SCR_STORE_REL (temp, 4),
 527                offsetof (struct sym_ccb, phys.head.lastp),
 528        /*
 529         *  If the SODL is not full jump to dispatcher.
 530         *  We anticipate a STATUS phase.
 531         */
 532        SCR_FROM_REG (scntl2),
 533                0,
 534        SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
 535                PADDR_A (datao_done_wss),
 536        SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)),
 537                PADDR_A (status),
 538        SCR_JUMP,
 539                PADDR_A (dispatch),
 540}/*-------------------------< DATAO_DONE_WSS >-------------------*/,{
 541        /*
 542         *  The SODL is full, clear this condition.
 543         */
 544        SCR_REG_REG (scntl2, SCR_OR, WSS),
 545                0,
 546        /*
 547         *  And signal a DATA UNDERRUN condition 
 548         *  to the C code.
 549         */
 550        SCR_INT,
 551                SIR_SODL_UNDERRUN,
 552        SCR_JUMP,
 553                PADDR_A (dispatch),
 554}/*-------------------------< DATAI_PHASE >----------------------*/,{
 555        /*
 556         *  Jump to current pointer.
 557         */
 558        SCR_LOAD_REL (temp, 4),
 559                offsetof (struct sym_ccb, phys.head.lastp),
 560        SCR_RETURN,
 561                0,
 562}/*-------------------------< DATAO_PHASE >----------------------*/,{
 563        /*
 564         *  C1010-66 errata work-around.
 565         *  Extra clocks of data hold must be inserted 
 566         *  in DATA OUT phase on 33 MHz PCI BUS.
 567         *  Patched with a NOOP for other chips.
 568         */
 569        SCR_REG_REG (scntl4, SCR_OR, (XCLKH_DT|XCLKH_ST)),
 570                0,
 571        /*
 572         *  Jump to current pointer.
 573         */
 574        SCR_LOAD_REL (temp, 4),
 575                offsetof (struct sym_ccb, phys.head.lastp),
 576        SCR_RETURN,
 577                0,
 578}/*-------------------------< MSG_IN >---------------------------*/,{
 579        /*
 580         *  Get the first byte of the message.
 581         *
 582         *  The script processor doesn't negate the
 583         *  ACK signal after this transfer.
 584         */
 585        SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
 586                HADDR_1 (msgin[0]),
 587}/*-------------------------< MSG_IN2 >--------------------------*/,{
 588        /*
 589         *  Check first against 1 byte messages 
 590         *  that we handle from SCRIPTS.
 591         */
 592        SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)),
 593                PADDR_A (complete),
 594        SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)),
 595                PADDR_A (disconnect),
 596        SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)),
 597                PADDR_A (save_dp),
 598        SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)),
 599                PADDR_A (restore_dp),
 600        /*
 601         *  We handle all other messages from the 
 602         *  C code, so no need to waste on-chip RAM 
 603         *  for those ones.
 604         */
 605        SCR_JUMP,
 606                PADDR_B (msg_in_etc),
 607}/*-------------------------< STATUS >---------------------------*/,{
 608        /*
 609         *  get the status
 610         */
 611        SCR_MOVE_ABS (1) ^ SCR_STATUS,
 612                HADDR_1 (scratch),
 613#ifdef SYM_CONF_IARB_SUPPORT
 614        /*
 615         *  If STATUS is not GOOD, clear IMMEDIATE ARBITRATION, 
 616         *  since we may have to tamper the start queue from 
 617         *  the C code.
 618         */
 619        SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)),
 620                8,
 621        SCR_REG_REG (scntl1, SCR_AND, ~IARB),
 622                0,
 623#endif
 624        /*
 625         *  save status to scsi_status.
 626         *  mark as complete.
 627         */
 628        SCR_TO_REG (SS_REG),
 629                0,
 630        SCR_LOAD_REG (HS_REG, HS_COMPLETE),
 631                0,
 632        /*
 633         *  Anticipate the MESSAGE PHASE for 
 634         *  the TASK COMPLETE message.
 635         */
 636        SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
 637                PADDR_A (msg_in),
 638        SCR_JUMP,
 639                PADDR_A (dispatch),
 640}/*-------------------------< COMPLETE >-------------------------*/,{
 641        /*
 642         *  Complete message.
 643         *
 644         *  When we terminate the cycle by clearing ACK,
 645         *  the target may disconnect immediately.
 646         *
 647         *  We don't want to be told of an "unexpected disconnect",
 648         *  so we disable this feature.
 649         */
 650        SCR_REG_REG (scntl2, SCR_AND, 0x7f),
 651                0,
 652        /*
 653         *  Terminate cycle ...
 654         */
 655        SCR_CLR (SCR_ACK|SCR_ATN),
 656                0,
 657        /*
 658         *  ... and wait for the disconnect.
 659         */
 660        SCR_WAIT_DISC,
 661                0,
 662}/*-------------------------< COMPLETE2 >------------------------*/,{
 663        /*
 664         *  Save host status.
 665         */
 666        SCR_STORE_REL (scr0, 4),
 667                offsetof (struct sym_ccb, phys.head.status),
 668        /*
 669         *  Some bridges may reorder DMA writes to memory.
 670         *  We donnot want the CPU to deal with completions  
 671         *  without all the posted write having been flushed 
 672         *  to memory. This DUMMY READ should flush posted 
 673         *  buffers prior to the CPU having to deal with 
 674         *  completions.
 675         */
 676        SCR_LOAD_REL (scr0, 4), /* DUMMY READ */
 677                offsetof (struct sym_ccb, phys.head.status),
 678
 679        /*
 680         *  If command resulted in not GOOD status,
 681         *  call the C code if needed.
 682         */
 683        SCR_FROM_REG (SS_REG),
 684                0,
 685        SCR_CALL ^ IFFALSE (DATA (S_GOOD)),
 686                PADDR_B (bad_status),
 687        /*
 688         *  If we performed an auto-sense, call 
 689         *  the C code to synchronyze task aborts 
 690         *  with UNIT ATTENTION conditions.
 691         */
 692        SCR_FROM_REG (HF_REG),
 693                0,
 694        SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
 695                PADDR_A (complete_error),
 696}/*-------------------------< DONE >-----------------------------*/,{
 697        /*
 698         *  Copy the DSA to the DONE QUEUE and 
 699         *  signal completion to the host.
 700         *  If we are interrupted between DONE 
 701         *  and DONE_END, we must reset, otherwise 
 702         *  the completed CCB may be lost.
 703         */
 704        SCR_STORE_ABS (dsa, 4),
 705                PADDR_B (scratch),
 706        SCR_LOAD_ABS (dsa, 4),
 707                PADDR_B (done_pos),
 708        SCR_LOAD_ABS (scratcha, 4),
 709                PADDR_B (scratch),
 710        SCR_STORE_REL (scratcha, 4),
 711                0,
 712        /*
 713         *  The instruction below reads the DONE QUEUE next 
 714         *  free position from memory.
 715         *  In addition it ensures that all PCI posted writes  
 716         *  are flushed and so the DSA value of the done 
 717         *  CCB is visible by the CPU before INTFLY is raised.
 718         */
 719        SCR_LOAD_REL (scratcha, 4),
 720                4,
 721        SCR_INT_FLY,
 722                0,
 723        SCR_STORE_ABS (scratcha, 4),
 724                PADDR_B (done_pos),
 725}/*-------------------------< DONE_END >-------------------------*/,{
 726        SCR_JUMP,
 727                PADDR_A (start),
 728}/*-------------------------< COMPLETE_ERROR >-------------------*/,{
 729        SCR_LOAD_ABS (scratcha, 4),
 730                PADDR_B (startpos),
 731        SCR_INT,
 732                SIR_COMPLETE_ERROR,
 733}/*-------------------------< SAVE_DP >--------------------------*/,{
 734        /*
 735         *  Clear ACK immediately.
 736         *  No need to delay it.
 737         */
 738        SCR_CLR (SCR_ACK),
 739                0,
 740        /*
 741         *  Keep track we received a SAVE DP, so 
 742         *  we will switch to the other PM context 
 743         *  on the next PM since the DP may point 
 744         *  to the current PM context.
 745         */
 746        SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED),
 747                0,
 748        /*
 749         *  SAVE_DP message:
 750         *  Copy LASTP to SAVEP.
 751         */
 752        SCR_LOAD_REL (scratcha, 4),
 753                offsetof (struct sym_ccb, phys.head.lastp),
 754        SCR_STORE_REL (scratcha, 4),
 755                offsetof (struct sym_ccb, phys.head.savep),
 756        /*
 757         *  Anticipate the MESSAGE PHASE for 
 758         *  the DISCONNECT message.
 759         */
 760        SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
 761                PADDR_A (msg_in),
 762        SCR_JUMP,
 763                PADDR_A (dispatch),
 764}/*-------------------------< RESTORE_DP >-----------------------*/,{
 765        /*
 766         *  Clear ACK immediately.
 767         *  No need to delay it.
 768         */
 769        SCR_CLR (SCR_ACK),
 770                0,
 771        /*
 772         *  Copy SAVEP to LASTP.
 773         */
 774        SCR_LOAD_REL  (scratcha, 4),
 775                offsetof (struct sym_ccb, phys.head.savep),
 776        SCR_STORE_REL (scratcha, 4),
 777                offsetof (struct sym_ccb, phys.head.lastp),
 778        SCR_JUMP,
 779                PADDR_A (dispatch),
 780}/*-------------------------< DISCONNECT >-----------------------*/,{
 781        /*
 782         *  DISCONNECTing  ...
 783         *
 784         *  disable the "unexpected disconnect" feature,
 785         *  and remove the ACK signal.
 786         */
 787        SCR_REG_REG (scntl2, SCR_AND, 0x7f),
 788                0,
 789        SCR_CLR (SCR_ACK|SCR_ATN),
 790                0,
 791        /*
 792         *  Wait for the disconnect.
 793         */
 794        SCR_WAIT_DISC,
 795                0,
 796        /*
 797         *  Status is: DISCONNECTED.
 798         */
 799        SCR_LOAD_REG (HS_REG, HS_DISCONNECT),
 800                0,
 801        /*
 802         *  Save host status.
 803         */
 804        SCR_STORE_REL (scr0, 4),
 805                offsetof (struct sym_ccb, phys.head.status),
 806        SCR_JUMP,
 807                PADDR_A (start),
 808}/*-------------------------< IDLE >-----------------------------*/,{
 809        /*
 810         *  Nothing to do?
 811         *  Switch the LED off and wait for reselect.
 812         *  Will be patched with a NO_OP if LED
 813         *  not needed or not desired.
 814         */
 815        SCR_REG_REG (gpreg, SCR_OR, 0x01),
 816                0,
 817#ifdef SYM_CONF_IARB_SUPPORT
 818        SCR_JUMPR,
 819                8,
 820#endif
 821}/*-------------------------< UNGETJOB >-------------------------*/,{
 822#ifdef SYM_CONF_IARB_SUPPORT
 823        /*
 824         *  Set IMMEDIATE ARBITRATION, for the next time.
 825         *  This will give us better chance to win arbitration 
 826         *  for the job we just wanted to do.
 827         */
 828        SCR_REG_REG (scntl1, SCR_OR, IARB),
 829                0,
 830#endif
 831        /*
 832         *  We are not able to restart the SCRIPTS if we are 
 833         *  interrupted and these instruction haven't been 
 834         *  all executed. BTW, this is very unlikely to 
 835         *  happen, but we check that from the C code.
 836         */
 837        SCR_LOAD_REG (dsa, 0xff),
 838                0,
 839        SCR_STORE_ABS (scratcha, 4),
 840                PADDR_B (startpos),
 841}/*-------------------------< RESELECT >-------------------------*/,{
 842#ifdef SYM_CONF_TARGET_ROLE_SUPPORT
 843        /*
 844         *  Make sure we are in initiator mode.
 845         */
 846        SCR_CLR (SCR_TRG),
 847                0,
 848#endif
 849        /*
 850         *  Sleep waiting for a reselection.
 851         */
 852        SCR_WAIT_RESEL,
 853                PADDR_A(start),
 854}/*-------------------------< RESELECTED >-----------------------*/,{
 855        /*
 856         *  Switch the LED on.
 857         *  Will be patched with a NO_OP if LED
 858         *  not needed or not desired.
 859         */
 860        SCR_REG_REG (gpreg, SCR_AND, 0xfe),
 861                0,
 862        /*
 863         *  load the target id into the sdid
 864         */
 865        SCR_REG_SFBR (ssid, SCR_AND, 0x8F),
 866                0,
 867        SCR_TO_REG (sdid),
 868                0,
 869        /*
 870         *  Load the target control block address
 871         */
 872        SCR_LOAD_ABS (dsa, 4),
 873                PADDR_B (targtbl),
 874        SCR_SFBR_REG (dsa, SCR_SHL, 0),
 875                0,
 876        SCR_REG_REG (dsa, SCR_SHL, 0),
 877                0,
 878        SCR_REG_REG (dsa, SCR_AND, 0x3c),
 879                0,
 880        SCR_LOAD_REL (dsa, 4),
 881                0,
 882        /*
 883         *  We expect MESSAGE IN phase.
 884         *  If not, get help from the C code.
 885         */
 886        SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
 887                SIR_RESEL_NO_MSG_IN,
 888        /*
 889         *  Load the legacy synchronous transfer registers.
 890         */
 891        SCR_LOAD_REL (scntl3, 1),
 892                offsetof(struct sym_tcb, head.wval),
 893        SCR_LOAD_REL (sxfer, 1),
 894                offsetof(struct sym_tcb, head.sval),
 895}/*-------------------------< RESEL_SCNTL4 >---------------------*/,{
 896        /*
 897         *  The C1010 uses a new synchronous timing scheme.
 898         *  Will be patched with a NO_OP if not a C1010.
 899         */
 900        SCR_LOAD_REL (scntl4, 1),
 901                offsetof(struct sym_tcb, head.uval),
 902        /*
 903         *  Get the IDENTIFY message.
 904         */
 905        SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
 906                HADDR_1 (msgin),
 907        /*
 908         *  If IDENTIFY LUN #0, use a faster path 
 909         *  to find the LCB structure.
 910         */
 911        SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
 912                PADDR_A (resel_lun0),
 913        /*
 914         *  If message isn't an IDENTIFY, 
 915         *  tell the C code about.
 916         */
 917        SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
 918                SIR_RESEL_NO_IDENTIFY,
 919        /*
 920         *  It is an IDENTIFY message,
 921         *  Load the LUN control block address.
 922         */
 923        SCR_LOAD_REL (dsa, 4),
 924                offsetof(struct sym_tcb, head.luntbl_sa),
 925        SCR_SFBR_REG (dsa, SCR_SHL, 0),
 926                0,
 927        SCR_REG_REG (dsa, SCR_SHL, 0),
 928                0,
 929        SCR_REG_REG (dsa, SCR_AND, 0xfc),
 930                0,
 931        SCR_LOAD_REL (dsa, 4),
 932                0,
 933        SCR_JUMPR,
 934                8,
 935}/*-------------------------< RESEL_LUN0 >-----------------------*/,{
 936        /*
 937         *  LUN 0 special case (but usual one :))
 938         */
 939        SCR_LOAD_REL (dsa, 4),
 940                offsetof(struct sym_tcb, head.lun0_sa),
 941        /*
 942         *  Jump indirectly to the reselect action for this LUN.
 943         */
 944        SCR_LOAD_REL (temp, 4),
 945                offsetof(struct sym_lcb, head.resel_sa),
 946        SCR_RETURN,
 947                0,
 948        /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */
 949}/*-------------------------< RESEL_TAG >------------------------*/,{
 950        /*
 951         *  ACK the IDENTIFY previously received.
 952         */
 953        SCR_CLR (SCR_ACK),
 954                0,
 955        /*
 956         *  It shall be a tagged command.
 957         *  Read SIMPLE+TAG.
 958         *  The C code will deal with errors.
 959         *  Aggressive optimization, isn't it? :)
 960         */
 961        SCR_MOVE_ABS (2) ^ SCR_MSG_IN,
 962                HADDR_1 (msgin),
 963        /*
 964         *  Load the pointer to the tagged task 
 965         *  table for this LUN.
 966         */
 967        SCR_LOAD_REL (dsa, 4),
 968                offsetof(struct sym_lcb, head.itlq_tbl_sa),
 969        /*
 970         *  The SIDL still contains the TAG value.
 971         *  Aggressive optimization, isn't it? :):)
 972         */
 973        SCR_REG_SFBR (sidl, SCR_SHL, 0),
 974                0,
 975#if SYM_CONF_MAX_TASK*4 > 512
 976        SCR_JUMPR ^ IFFALSE (CARRYSET),
 977                8,
 978        SCR_REG_REG (dsa1, SCR_OR, 2),
 979                0,
 980        SCR_REG_REG (sfbr, SCR_SHL, 0),
 981                0,
 982        SCR_JUMPR ^ IFFALSE (CARRYSET),
 983                8,
 984        SCR_REG_REG (dsa1, SCR_OR, 1),
 985                0,
 986#elif SYM_CONF_MAX_TASK*4 > 256
 987        SCR_JUMPR ^ IFFALSE (CARRYSET),
 988                8,
 989        SCR_REG_REG (dsa1, SCR_OR, 1),
 990                0,
 991#endif
 992        /*
 993         *  Retrieve the DSA of this task.
 994         *  JUMP indirectly to the restart point of the CCB.
 995         */
 996        SCR_SFBR_REG (dsa, SCR_AND, 0xfc),
 997                0,
 998        SCR_LOAD_REL (dsa, 4),
 999                0,
1000        SCR_LOAD_REL (temp, 4),
1001                offsetof(struct sym_ccb, phys.head.go.restart),
1002        SCR_RETURN,
1003                0,
1004        /* In normal situations we branch to RESEL_DSA */
1005}/*-------------------------< RESEL_DSA >------------------------*/,{
1006        /*
1007         *  ACK the IDENTIFY or TAG previously received.
1008         */
1009        SCR_CLR (SCR_ACK),
1010                0,
1011}/*-------------------------< RESEL_DSA1 >-----------------------*/,{
1012        /*
1013         *      Initialize the status registers
1014         */
1015        SCR_LOAD_REL (scr0, 4),
1016                offsetof (struct sym_ccb, phys.head.status),
1017        /*
1018         *  Jump to dispatcher.
1019         */
1020        SCR_JUMP,
1021                PADDR_A (dispatch),
1022}/*-------------------------< RESEL_NO_TAG >---------------------*/,{
1023        /*
1024         *  Load the DSA with the unique ITL task.
1025         */
1026        SCR_LOAD_REL (dsa, 4),
1027                offsetof(struct sym_lcb, head.itl_task_sa),
1028        /*
1029         *  JUMP indirectly to the restart point of the CCB.
1030         */
1031        SCR_LOAD_REL (temp, 4),
1032                offsetof(struct sym_ccb, phys.head.go.restart),
1033        SCR_RETURN,
1034                0,
1035        /* In normal situations we branch to RESEL_DSA */
1036}/*-------------------------< DATA_IN >--------------------------*/,{
1037/*
1038 *  Because the size depends on the
1039 *  #define SYM_CONF_MAX_SG parameter,
1040 *  it is filled in at runtime.
1041 *
1042 *  ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1043 *  ||  SCR_CHMOV_TBL ^ SCR_DATA_IN,
1044 *  ||          offsetof (struct sym_dsb, data[ i]),
1045 *  ##==========================================
1046 */
10470
1048}/*-------------------------< DATA_IN2 >-------------------------*/,{
1049        SCR_CALL,
1050                PADDR_A (datai_done),
1051        SCR_JUMP,
1052                PADDR_B (data_ovrun),
1053}/*-------------------------< DATA_OUT >-------------------------*/,{
1054/*
1055 *  Because the size depends on the
1056 *  #define SYM_CONF_MAX_SG parameter,
1057 *  it is filled in at runtime.
1058 *
1059 *  ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1060 *  ||  SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1061 *  ||          offsetof (struct sym_dsb, data[ i]),
1062 *  ##==========================================
1063 */
10640
1065}/*-------------------------< DATA_OUT2 >------------------------*/,{
1066        SCR_CALL,
1067                PADDR_A (datao_done),
1068        SCR_JUMP,
1069                PADDR_B (data_ovrun),
1070}/*-------------------------< PM0_DATA >-------------------------*/,{
1071        /*
1072         *  Read our host flags to SFBR, so we will be able 
1073         *  to check against the data direction we expect.
1074         */
1075        SCR_FROM_REG (HF_REG),
1076                0,
1077        /*
1078         *  Check against actual DATA PHASE.
1079         */
1080        SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
1081                PADDR_A (pm0_data_out),
1082        /*
1083         *  Actual phase is DATA IN.
1084         *  Check against expected direction.
1085         */
1086        SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1087                PADDR_B (data_ovrun),
1088        /*
1089         *  Keep track we are moving data from the 
1090         *  PM0 DATA mini-script.
1091         */
1092        SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
1093                0,
1094        /*
1095         *  Move the data to memory.
1096         */
1097        SCR_CHMOV_TBL ^ SCR_DATA_IN,
1098                offsetof (struct sym_ccb, phys.pm0.sg),
1099        SCR_JUMP,
1100                PADDR_A (pm0_data_end),
1101}/*-------------------------< PM0_DATA_OUT >---------------------*/,{
1102        /*
1103         *  Actual phase is DATA OUT.
1104         *  Check against expected direction.
1105         */
1106        SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
1107                PADDR_B (data_ovrun),
1108        /*
1109         *  Keep track we are moving data from the 
1110         *  PM0 DATA mini-script.
1111         */
1112        SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
1113                0,
1114        /*
1115         *  Move the data from memory.
1116         */
1117        SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1118                offsetof (struct sym_ccb, phys.pm0.sg),
1119}/*-------------------------< PM0_DATA_END >---------------------*/,{
1120        /*
1121         *  Clear the flag that told we were moving  
1122         *  data from the PM0 DATA mini-script.
1123         */
1124        SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)),
1125                0,
1126        /*
1127         *  Return to the previous DATA script which 
1128         *  is guaranteed by design (if no bug) to be 
1129         *  the main DATA script for this transfer.
1130         */
1131        SCR_LOAD_REL (temp, 4),
1132                offsetof (struct sym_ccb, phys.pm0.ret),
1133        SCR_RETURN,
1134                0,
1135}/*-------------------------< PM1_DATA >-------------------------*/,{
1136        /*
1137         *  Read our host flags to SFBR, so we will be able 
1138         *  to check against the data direction we expect.
1139         */
1140        SCR_FROM_REG (HF_REG),
1141                0,
1142        /*
1143         *  Check against actual DATA PHASE.
1144         */
1145        SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
1146                PADDR_A (pm1_data_out),
1147        /*
1148         *  Actual phase is DATA IN.
1149         *  Check against expected direction.
1150         */
1151        SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1152                PADDR_B (data_ovrun),
1153        /*
1154         *  Keep track we are moving data from the 
1155         *  PM1 DATA mini-script.
1156         */
1157        SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
1158                0,
1159        /*
1160         *  Move the data to memory.
1161         */
1162        SCR_CHMOV_TBL ^ SCR_DATA_IN,
1163                offsetof (struct sym_ccb, phys.pm1.sg),
1164        SCR_JUMP,
1165                PADDR_A (pm1_data_end),
1166}/*-------------------------< PM1_DATA_OUT >---------------------*/,{
1167        /*
1168         *  Actual phase is DATA OUT.
1169         *  Check against expected direction.
1170         */
1171        SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
1172                PADDR_B (data_ovrun),
1173        /*
1174         *  Keep track we are moving data from the 
1175         *  PM1 DATA mini-script.
1176         */
1177        SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
1178                0,
1179        /*
1180         *  Move the data from memory.
1181         */
1182        SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1183                offsetof (struct sym_ccb, phys.pm1.sg),
1184}/*-------------------------< PM1_DATA_END >---------------------*/,{
1185        /*
1186         *  Clear the flag that told we were moving  
1187         *  data from the PM1 DATA mini-script.
1188         */
1189        SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)),
1190                0,
1191        /*
1192         *  Return to the previous DATA script which 
1193         *  is guaranteed by design (if no bug) to be 
1194         *  the main DATA script for this transfer.
1195         */
1196        SCR_LOAD_REL (temp, 4),
1197                offsetof (struct sym_ccb, phys.pm1.ret),
1198        SCR_RETURN,
1199                0,
1200}/*-------------------------<>-----------------------------------*/
1201};
1202
1203static struct SYM_FWB_SCR SYM_FWB_SCR = {
1204/*--------------------------< START64 >--------------------------*/ {
1205        /*
1206         *  SCRIPT entry point for the 895A, 896 and 1010.
1207         *  For now, there is no specific stuff for those 
1208         *  chips at this point, but this may come.
1209         */
1210        SCR_JUMP,
1211                PADDR_A (init),
1212}/*-------------------------< NO_DATA >--------------------------*/,{
1213        SCR_JUMP,
1214                PADDR_B (data_ovrun),
1215}/*-------------------------< SEL_FOR_ABORT >--------------------*/,{
1216        /*
1217         *  We are jumped here by the C code, if we have 
1218         *  some target to reset or some disconnected 
1219         *  job to abort. Since error recovery is a serious 
1220         *  busyness, we will really reset the SCSI BUS, if 
1221         *  case of a SCSI interrupt occurring in this path.
1222         */
1223#ifdef SYM_CONF_TARGET_ROLE_SUPPORT
1224        /*
1225         *  Set initiator mode.
1226         */
1227        SCR_CLR (SCR_TRG),
1228                0,
1229#endif
1230        /*
1231         *      And try to select this target.
1232         */
1233        SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel),
1234                PADDR_A (reselect),
1235        /*
1236         *  Wait for the selection to complete or 
1237         *  the selection to time out.
1238         */
1239        SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1240                -8,
1241        /*
1242         *  Call the C code.
1243         */
1244        SCR_INT,
1245                SIR_TARGET_SELECTED,
1246        /*
1247         *  The C code should let us continue here. 
1248         *  Send the 'kiss of death' message.
1249         *  We expect an immediate disconnect once 
1250         *  the target has eaten the message.
1251         */
1252        SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1253                0,
1254        SCR_MOVE_TBL ^ SCR_MSG_OUT,
1255                offsetof (struct sym_hcb, abrt_tbl),
1256        SCR_CLR (SCR_ACK|SCR_ATN),
1257                0,
1258        SCR_WAIT_DISC,
1259                0,
1260        /*
1261         *  Tell the C code that we are done.
1262         */
1263        SCR_INT,
1264                SIR_ABORT_SENT,
1265}/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{
1266        /*
1267         *  Jump at scheduler.
1268         */
1269        SCR_JUMP,
1270                PADDR_A (start),
1271}/*-------------------------< MSG_IN_ETC >-----------------------*/,{
1272        /*
1273         *  If it is an EXTENDED (variable size message)
1274         *  Handle it.
1275         */
1276        SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)),
1277                PADDR_B (msg_extended),
1278        /*
1279         *  Let the C code handle any other 
1280         *  1 byte message.
1281         */
1282        SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)),
1283                PADDR_B (msg_received),
1284        SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)),
1285                PADDR_B (msg_received),
1286        /*
1287         *  We donnot handle 2 bytes messages from SCRIPTS.
1288         *  So, let the C code deal with these ones too.
1289         */
1290        SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)),
1291                PADDR_B (msg_weird_seen),
1292        SCR_CLR (SCR_ACK),
1293                0,
1294        SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1295                HADDR_1 (msgin[1]),
1296}/*-------------------------< MSG_RECEIVED >---------------------*/,{
1297        SCR_LOAD_REL (scratcha, 4),     /* DUMMY READ */
1298                0,
1299        SCR_INT,
1300                SIR_MSG_RECEIVED,
1301}/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{
1302        SCR_LOAD_REL (scratcha, 4),     /* DUMMY READ */
1303                0,
1304        SCR_INT,
1305                SIR_MSG_WEIRD,
1306}/*-------------------------< MSG_EXTENDED >---------------------*/,{
1307        /*
1308         *  Clear ACK and get the next byte 
1309         *  assumed to be the message length.
1310         */
1311        SCR_CLR (SCR_ACK),
1312                0,
1313        SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1314                HADDR_1 (msgin[1]),
1315        /*
1316         *  Try to catch some unlikely situations as 0 length 
1317         *  or too large the length.
1318         */
1319        SCR_JUMP ^ IFTRUE (DATA (0)),
1320                PADDR_B (msg_weird_seen),
1321        SCR_TO_REG (scratcha),
1322                0,
1323        SCR_REG_REG (sfbr, SCR_ADD, (256-8)),
1324                0,
1325        SCR_JUMP ^ IFTRUE (CARRYSET),
1326                PADDR_B (msg_weird_seen),
1327        /*
1328         *  We donnot handle extended messages from SCRIPTS.
1329         *  Read the amount of data corresponding to the 
1330         *  message length and call the C code.
1331         */
1332        SCR_STORE_REL (scratcha, 1),
1333                offsetof (struct sym_dsb, smsg_ext.size),
1334        SCR_CLR (SCR_ACK),
1335                0,
1336        SCR_MOVE_TBL ^ SCR_MSG_IN,
1337                offsetof (struct sym_dsb, smsg_ext),
1338        SCR_JUMP,
1339                PADDR_B (msg_received),
1340}/*-------------------------< MSG_BAD >--------------------------*/,{
1341        /*
1342         *  unimplemented message - reject it.
1343         */
1344        SCR_INT,
1345                SIR_REJECT_TO_SEND,
1346        SCR_SET (SCR_ATN),
1347                0,
1348        SCR_JUMP,
1349                PADDR_A (clrack),
1350}/*-------------------------< MSG_WEIRD >------------------------*/,{
1351        /*
1352         *  weird message received
1353         *  ignore all MSG IN phases and reject it.
1354         */
1355        SCR_INT,
1356                SIR_REJECT_TO_SEND,
1357        SCR_SET (SCR_ATN),
1358                0,
1359}/*-------------------------< MSG_WEIRD1 >-----------------------*/,{
1360        SCR_CLR (SCR_ACK),
1361                0,
1362        SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
1363                PADDR_A (dispatch),
1364        SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1365                HADDR_1 (scratch),
1366        SCR_JUMP,
1367                PADDR_B (msg_weird1),
1368}/*-------------------------< WDTR_RESP >------------------------*/,{
1369        /*
1370         *  let the target fetch our answer.
1371         */
1372        SCR_SET (SCR_ATN),
1373                0,
1374        SCR_CLR (SCR_ACK),
1375                0,
1376        SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1377                PADDR_B (nego_bad_phase),
1378}/*-------------------------< SEND_WDTR >------------------------*/,{
1379        /*
1380         *  Send the M_X_WIDE_REQ
1381         */
1382        SCR_MOVE_ABS (4) ^ SCR_MSG_OUT,
1383                HADDR_1 (msgout),
1384        SCR_JUMP,
1385                PADDR_B (msg_out_done),
1386}/*-------------------------< SDTR_RESP >------------------------*/,{
1387        /*
1388         *  let the target fetch our answer.
1389         */
1390        SCR_SET (SCR_ATN),
1391                0,
1392        SCR_CLR (SCR_ACK),
1393                0,
1394        SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1395                PADDR_B (nego_bad_phase),
1396}/*-------------------------< SEND_SDTR >------------------------*/,{
1397        /*
1398         *  Send the M_X_SYNC_REQ
1399         */
1400        SCR_MOVE_ABS (5) ^ SCR_MSG_OUT,
1401                HADDR_1 (msgout),
1402        SCR_JUMP,
1403                PADDR_B (msg_out_done),
1404}/*-------------------------< PPR_RESP >-------------------------*/,{
1405        /*
1406         *  let the target fetch our answer.
1407         */
1408        SCR_SET (SCR_ATN),
1409                0,
1410        SCR_CLR (SCR_ACK),
1411                0,
1412        SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1413                PADDR_B (nego_bad_phase),
1414}/*-------------------------< SEND_PPR >-------------------------*/,{
1415        /*
1416         *  Send the M_X_PPR_REQ
1417         */
1418        SCR_MOVE_ABS (8) ^ SCR_MSG_OUT,
1419                HADDR_1 (msgout),
1420        SCR_JUMP,
1421                PADDR_B (msg_out_done),
1422}/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{
1423        SCR_INT,
1424                SIR_NEGO_PROTO,
1425        SCR_JUMP,
1426                PADDR_A (dispatch),
1427}/*-------------------------< MSG_OUT >--------------------------*/,{
1428        /*
1429         *  The target requests a message.
1430         *  We donnot send messages that may 
1431         *  require the device to go to bus free.
1432         */
1433        SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
1434                HADDR_1 (msgout),
1435        /*
1436         *  ... wait for the next phase
1437         *  if it's a message out, send it again, ...
1438         */
1439        SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
1440                PADDR_B (msg_out),
1441}/*-------------------------< MSG_OUT_DONE >---------------------*/,{
1442        /*
1443         *  Let the C code be aware of the 
1444         *  sent message and clear the message.
1445         */
1446        SCR_INT,
1447                SIR_MSG_OUT_DONE,
1448        /*
1449         *  ... and process the next phase
1450         */
1451        SCR_JUMP,
1452                PADDR_A (dispatch),
1453}/*-------------------------< DATA_OVRUN >-----------------------*/,{
1454        /*
1455         *  Use scratcha to count the extra bytes.
1456         */
1457        SCR_LOAD_ABS (scratcha, 4),
1458                PADDR_B (zero),
1459}/*-------------------------< DATA_OVRUN1 >----------------------*/,{
1460        /*
1461         *  The target may want to transfer too much data.
1462         *
1463         *  If phase is DATA OUT write 1 byte and count it.
1464         */
1465        SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)),
1466                16,
1467        SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT,
1468                HADDR_1 (scratch),
1469        SCR_JUMP,
1470                PADDR_B (data_ovrun2),
1471        /*
1472         *  If WSR is set, clear this condition, and 
1473         *  count this byte.
1474         */
1475        SCR_FROM_REG (scntl2),
1476                0,
1477        SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
1478                16,
1479        SCR_REG_REG (scntl2, SCR_OR, WSR),
1480                0,
1481        SCR_JUMP,
1482                PADDR_B (data_ovrun2),
1483        /*
1484         *  Finally check against DATA IN phase.
1485         *  Signal data overrun to the C code 
1486         *  and jump to dispatcher if not so.
1487         *  Read 1 byte otherwise and count it.
1488         */
1489        SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)),
1490                16,
1491        SCR_INT,
1492                SIR_DATA_OVERRUN,
1493        SCR_JUMP,
1494                PADDR_A (dispatch),
1495        SCR_CHMOV_ABS (1) ^ SCR_DATA_IN,
1496                HADDR_1 (scratch),
1497}/*-------------------------< DATA_OVRUN2 >----------------------*/,{
1498        /*
1499         *  Count this byte.
1500         *  This will allow to return a negative 
1501         *  residual to user.
1502         */
1503        SCR_REG_REG (scratcha,  SCR_ADD,  0x01),
1504                0,
1505        SCR_REG_REG (scratcha1, SCR_ADDC, 0),
1506                0,
1507        SCR_REG_REG (scratcha2, SCR_ADDC, 0),
1508                0,
1509        /*
1510         *  .. and repeat as required.
1511         */
1512        SCR_JUMP,
1513                PADDR_B (data_ovrun1),
1514}/*-------------------------< ABORT_RESEL >----------------------*/,{
1515        SCR_SET (SCR_ATN),
1516                0,
1517        SCR_CLR (SCR_ACK),
1518                0,
1519        /*
1520         *  send the abort/abortag/reset message
1521         *  we expect an immediate disconnect
1522         */
1523        SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1524                0,
1525        SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
1526                HADDR_1 (msgout),
1527        SCR_CLR (SCR_ACK|SCR_ATN),
1528                0,
1529        SCR_WAIT_DISC,
1530                0,
1531        SCR_INT,
1532                SIR_RESEL_ABORTED,
1533        SCR_JUMP,
1534                PADDR_A (start),
1535}/*-------------------------< RESEND_IDENT >---------------------*/,{
1536        /*
1537         *  The target stays in MSG OUT phase after having acked 
1538         *  Identify [+ Tag [+ Extended message ]]. Targets shall
1539         *  behave this way on parity error.
1540         *  We must send it again all the messages.
1541         */
1542        SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the  */
1543                0,         /* 1rst ACK = 90 ns. Hope the chip isn't too fast */
1544        SCR_JUMP,
1545                PADDR_A (send_ident),
1546}/*-------------------------< IDENT_BREAK >----------------------*/,{
1547        SCR_CLR (SCR_ATN),
1548                0,
1549        SCR_JUMP,
1550                PADDR_A (select2),
1551}/*-------------------------< IDENT_BREAK_ATN >------------------*/,{
1552        SCR_SET (SCR_ATN),
1553                0,
1554        SCR_JUMP,
1555                PADDR_A (select2),
1556}/*-------------------------< SDATA_IN >-------------------------*/,{
1557        SCR_CHMOV_TBL ^ SCR_DATA_IN,
1558                offsetof (struct sym_dsb, sense),
1559        SCR_CALL,
1560                PADDR_A (datai_done),
1561        SCR_JUMP,
1562                PADDR_B (data_ovrun),
1563}/*-------------------------< RESEL_BAD_LUN >--------------------*/,{
1564        /*
1565         *  Message is an IDENTIFY, but lun is unknown.
1566         *  Signal problem to C code for logging the event.
1567         *  Send a M_ABORT to clear all pending tasks.
1568         */
1569        SCR_INT,
1570                SIR_RESEL_BAD_LUN,
1571        SCR_JUMP,
1572                PADDR_B (abort_resel),
1573}/*-------------------------< BAD_I_T_L >------------------------*/,{
1574        /*
1575         *  We donnot have a task for that I_T_L.
1576         *  Signal problem to C code for logging the event.
1577         *  Send a M_ABORT message.
1578         */
1579        SCR_INT,
1580                SIR_RESEL_BAD_I_T_L,
1581        SCR_JUMP,
1582                PADDR_B (abort_resel),
1583}/*-------------------------< BAD_I_T_L_Q >----------------------*/,{
1584        /*
1585         *  We donnot have a task that matches the tag.
1586         *  Signal problem to C code for logging the event.
1587         *  Send a M_ABORTTAG message.
1588         */
1589        SCR_INT,
1590                SIR_RESEL_BAD_I_T_L_Q,
1591        SCR_JUMP,
1592                PADDR_B (abort_resel),
1593}/*-------------------------< BAD_STATUS >-----------------------*/,{
1594        /*
1595         *  Anything different from INTERMEDIATE 
1596         *  CONDITION MET should be a bad SCSI status, 
1597         *  given that GOOD status has already been tested.
1598         *  Call the C code.
1599         */
1600        SCR_LOAD_ABS (scratcha, 4),
1601                PADDR_B (startpos),
1602        SCR_INT ^ IFFALSE (DATA (S_COND_MET)),
1603                SIR_BAD_SCSI_STATUS,
1604        SCR_RETURN,
1605                0,
1606}/*-------------------------< PM_HANDLE >------------------------*/,{
1607        /*
1608         *  Phase mismatch handling.
1609         *
1610         *  Since we have to deal with 2 SCSI data pointers  
1611         *  (current and saved), we need at least 2 contexts.
1612         *  Each context (pm0 and pm1) has a saved area, a 
1613         *  SAVE mini-script and a DATA phase mini-script.
1614         */
1615        /*
1616         *  Get the PM handling flags.
1617         */
1618        SCR_FROM_REG (HF_REG),
1619                0,
1620        /*
1621         *  If no flags (1rst PM for example), avoid 
1622         *  all the below heavy flags testing.
1623         *  This makes the normal case a bit faster.
1624         */
1625        SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED))),
1626                PADDR_B (pm_handle1),
1627        /*
1628         *  If we received a SAVE DP, switch to the 
1629         *  other PM context since the savep may point 
1630         *  to the current PM context.
1631         */
1632        SCR_JUMPR ^ IFFALSE (MASK (HF_DP_SAVED, HF_DP_SAVED)),
1633                8,
1634        SCR_REG_REG (sfbr, SCR_XOR, HF_ACT_PM),
1635                0,
1636        /*
1637         *  If we have been interrupt in a PM DATA mini-script,
1638         *  we take the return address from the corresponding 
1639         *  saved area.
1640         *  This ensure the return address always points to the 
1641         *  main DATA script for this transfer.
1642         */
1643        SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1))),
1644                PADDR_B (pm_handle1),
1645        SCR_JUMPR ^ IFFALSE (MASK (HF_IN_PM0, HF_IN_PM0)),
1646                16,
1647        SCR_LOAD_REL (ia, 4),
1648                offsetof(struct sym_ccb, phys.pm0.ret),
1649        SCR_JUMP,
1650                PADDR_B (pm_save),
1651        SCR_LOAD_REL (ia, 4),
1652                offsetof(struct sym_ccb, phys.pm1.ret),
1653        SCR_JUMP,
1654                PADDR_B (pm_save),
1655}/*-------------------------< PM_HANDLE1 >-----------------------*/,{
1656        /*
1657         *  Normal case.
1658         *  Update the return address so that it 
1659         *  will point after the interrupted MOVE.
1660         */
1661        SCR_REG_REG (ia, SCR_ADD, 8),
1662                0,
1663        SCR_REG_REG (ia1, SCR_ADDC, 0),
1664                0,
1665}/*-------------------------< PM_SAVE >--------------------------*/,{
1666        /*
1667         *  Clear all the flags that told us if we were 
1668         *  interrupted in a PM DATA mini-script and/or 
1669         *  we received a SAVE DP.
1670         */
1671        SCR_SFBR_REG (HF_REG, SCR_AND, (~(HF_IN_PM0|HF_IN_PM1|HF_DP_SAVED))),
1672                0,
1673        /*
1674         *  Choose the current PM context.
1675         */
1676        SCR_JUMP ^ IFTRUE (MASK (HF_ACT_PM, HF_ACT_PM)),
1677                PADDR_B (pm1_save),
1678}/*-------------------------< PM0_SAVE >-------------------------*/,{
1679        SCR_STORE_REL (ia, 4),
1680                offsetof(struct sym_ccb, phys.pm0.ret),
1681        /*
1682         *  If WSR bit is set, either UA and RBC may 
1683         *  have to be changed whether the device wants 
1684         *  to ignore this residue or not.
1685         */
1686        SCR_FROM_REG (scntl2),
1687                0,
1688        SCR_CALL ^ IFTRUE (MASK (WSR, WSR)),
1689                PADDR_B (pm_wsr_handle),
1690        /*
1691         *  Save the remaining byte count, the updated 
1692         *  address and the return address.
1693         */
1694        SCR_STORE_REL (rbc, 4),
1695                offsetof(struct sym_ccb, phys.pm0.sg.size),
1696        SCR_STORE_REL (ua, 4),
1697                offsetof(struct sym_ccb, phys.pm0.sg.addr),
1698        /*
1699         *  Set the current pointer at the PM0 DATA mini-script.
1700         */
1701        SCR_LOAD_ABS (ia, 4),
1702                PADDR_B (pm0_data_addr),
1703}/*-------------------------< PM_SAVE_END >----------------------*/,{
1704        SCR_STORE_REL (ia, 4),
1705                offsetof(struct sym_ccb, phys.head.lastp),
1706        SCR_JUMP,
1707                PADDR_A (dispatch),
1708}/*-------------------------< PM1_SAVE >-------------------------*/,{
1709        SCR_STORE_REL (ia, 4),
1710                offsetof(struct sym_ccb, phys.pm1.ret),
1711        /*
1712         *  If WSR bit is set, either UA and RBC may 
1713         *  have to be changed whether the device wants 
1714         *  to ignore this residue or not.
1715         */
1716        SCR_FROM_REG (scntl2),
1717                0,
1718        SCR_CALL ^ IFTRUE (MASK (WSR, WSR)),
1719                PADDR_B (pm_wsr_handle),
1720        /*
1721         *  Save the remaining byte count, the updated 
1722         *  address and the return address.
1723         */
1724        SCR_STORE_REL (rbc, 4),
1725                offsetof(struct sym_ccb, phys.pm1.sg.size),
1726        SCR_STORE_REL (ua, 4),
1727                offsetof(struct sym_ccb, phys.pm1.sg.addr),
1728        /*
1729         *  Set the current pointer at the PM1 DATA mini-script.
1730         */
1731        SCR_LOAD_ABS (ia, 4),
1732                PADDR_B (pm1_data_addr),
1733        SCR_JUMP,
1734                PADDR_B (pm_save_end),
1735}/*-------------------------< PM_WSR_HANDLE >--------------------*/,{
1736        /*
1737         *  Phase mismatch handling from SCRIPT with WSR set.
1738         *  Such a condition can occur if the chip wants to 
1739         *  execute a CHMOV(size > 1) when the WSR bit is 
1740         *  set and the target changes PHASE.
1741         *
1742         *  We must move the residual byte to memory.
1743         *
1744         *  UA contains bit 0..31 of the address to 
1745         *  move the residual byte.
1746         *  Move it to the table indirect.
1747         */
1748        SCR_STORE_REL (ua, 4),
1749                offsetof (struct sym_ccb, phys.wresid.addr),
1750        /*
1751         *  Increment UA (move address to next position).
1752         */
1753        SCR_REG_REG (ua, SCR_ADD, 1),
1754                0,
1755        SCR_REG_REG (ua1, SCR_ADDC, 0),
1756                0,
1757        SCR_REG_REG (ua2, SCR_ADDC, 0),
1758                0,
1759        SCR_REG_REG (ua3, SCR_ADDC, 0),
1760                0,
1761        /*
1762         *  Compute SCRATCHA as:
1763         *  - size to transfer = 1 byte.
1764         *  - bit 24..31 = high address bit [32...39].
1765         */
1766        SCR_LOAD_ABS (scratcha, 4),
1767                PADDR_B (zero),
1768        SCR_REG_REG (scratcha, SCR_OR, 1),
1769                0,
1770        SCR_FROM_REG (rbc3),
1771                0,
1772        SCR_TO_REG (scratcha3),
1773                0,
1774        /*
1775         *  Move this value to the table indirect.
1776         */
1777        SCR_STORE_REL (scratcha, 4),
1778                offsetof (struct sym_ccb, phys.wresid.size),
1779        /*
1780         *  Wait for a valid phase.
1781         *  While testing with bogus QUANTUM drives, the C1010 
1782         *  sometimes raised a spurious phase mismatch with 
1783         *  WSR and the CHMOV(1) triggered another PM.
1784         *  Waiting explicitly for the PHASE seemed to avoid
1785         *  the nested phase mismatch. Btw, this didn't happen 
1786         *  using my IBM drives.
1787         */
1788        SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_IN)),
1789                0,
1790        /*
1791         *  Perform the move of the residual byte.
1792         */
1793        SCR_CHMOV_TBL ^ SCR_DATA_IN,
1794                offsetof (struct sym_ccb, phys.wresid),
1795        /*
1796         *  We can now handle the phase mismatch with UA fixed.
1797         *  RBC[0..23]=0 is a special case that does not require 
1798         *  a PM context. The C code also checks against this.
1799         */
1800        SCR_FROM_REG (rbc),
1801                0,
1802        SCR_RETURN ^ IFFALSE (DATA (0)),
1803                0,
1804        SCR_FROM_REG (rbc1),
1805                0,
1806        SCR_RETURN ^ IFFALSE (DATA (0)),
1807                0,
1808        SCR_FROM_REG (rbc2),
1809                0,
1810        SCR_RETURN ^ IFFALSE (DATA (0)),
1811                0,
1812        /*
1813         *  RBC[0..23]=0.
1814         *  Not only we donnot need a PM context, but this would 
1815         *  lead to a bogus CHMOV(0). This condition means that 
1816         *  the residual was the last byte to move from this CHMOV.
1817         *  So, we just have to move the current data script pointer 
1818         *  (i.e. TEMP) to the SCRIPTS address following the 
1819         *  interrupted CHMOV and jump to dispatcher.
1820         *  IA contains the data pointer to save.
1821         */
1822        SCR_JUMP,
1823                PADDR_B (pm_save_end),
1824}/*-------------------------< WSR_MA_HELPER >--------------------*/,{
1825        /*
1826         *  Helper for the C code when WSR bit is set.
1827         *  Perform the move of the residual byte.
1828         */
1829        SCR_CHMOV_TBL ^ SCR_DATA_IN,
1830                offsetof (struct sym_ccb, phys.wresid),
1831        SCR_JUMP,
1832                PADDR_A (dispatch),
1833
1834}/*-------------------------< ZERO >-----------------------------*/,{
1835        SCR_DATA_ZERO,
1836}/*-------------------------< SCRATCH >--------------------------*/,{
1837        SCR_DATA_ZERO,
1838}/*-------------------------< PM0_DATA_ADDR >--------------------*/,{
1839        SCR_DATA_ZERO,
1840}/*-------------------------< PM1_DATA_ADDR >--------------------*/,{
1841        SCR_DATA_ZERO,
1842}/*-------------------------< DONE_POS >-------------------------*/,{
1843        SCR_DATA_ZERO,
1844}/*-------------------------< STARTPOS >-------------------------*/,{
1845        SCR_DATA_ZERO,
1846}/*-------------------------< TARGTBL >--------------------------*/,{
1847        SCR_DATA_ZERO,
1848}/*-------------------------<>-----------------------------------*/
1849};
1850
1851static struct SYM_FWZ_SCR SYM_FWZ_SCR = {
1852 /*-------------------------< SNOOPTEST >------------------------*/{
1853        /*
1854         *  Read the variable from memory.
1855         */
1856        SCR_LOAD_REL (scratcha, 4),
1857                offsetof(struct sym_hcb, scratch),
1858        /*
1859         *  Write the variable to memory.
1860         */
1861        SCR_STORE_REL (temp, 4),
1862                offsetof(struct sym_hcb, scratch),
1863        /*
1864         *  Read back the variable from memory.
1865         */
1866        SCR_LOAD_REL (temp, 4),
1867                offsetof(struct sym_hcb, scratch),
1868}/*-------------------------< SNOOPEND >-------------------------*/,{
1869        /*
1870         *  And stop.
1871         */
1872        SCR_INT,
1873                99,
1874}/*-------------------------<>-----------------------------------*/
1875};
1876