1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15/***************************************************************************** 16 * 17 * Module: __RTW_MP_PHY_REGDEF_H_ 18 * 19 * 20 * Note: 1. Define PMAC/BB register map 21 * 2. Define RF register map 22 * 3. PMAC/BB register bit mask. 23 * 4. RF reg bit mask. 24 * 5. Other BB/RF relative definition. 25 * 26 * 27 * Export: Constants, macro, functions(API), global variables(None). 28 * 29 * Abbrev: 30 * 31 * History: 32 * Data Who Remark 33 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. 34 * 2. Reorganize code architecture. 35 * 09/25/2008 MH 1. Add RL6052 register definition 36 * 37 *****************************************************************************/ 38#ifndef __RTW_MP_PHY_REGDEF_H_ 39#define __RTW_MP_PHY_REGDEF_H_ 40 41 42/*--------------------------Define Parameters-------------------------------*/ 43 44/* */ 45/* 8192S Regsiter offset definition */ 46/* */ 47 48/* */ 49/* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */ 50/* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 51/* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */ 52/* 3. RF register 0x00-2E */ 53/* 4. Bit Mask for BB/RF register */ 54/* 5. Other definition for BB/RF R/W */ 55/* */ 56 57 58/* */ 59/* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 60/* 1. Page1(0x100) */ 61/* */ 62#define rPMAC_Reset 0x100 63#define rPMAC_TxStart 0x104 64#define rPMAC_TxLegacySIG 0x108 65#define rPMAC_TxHTSIG1 0x10c 66#define rPMAC_TxHTSIG2 0x110 67#define rPMAC_PHYDebug 0x114 68#define rPMAC_TxPacketNum 0x118 69#define rPMAC_TxIdle 0x11c 70#define rPMAC_TxMACHeader0 0x120 71#define rPMAC_TxMACHeader1 0x124 72#define rPMAC_TxMACHeader2 0x128 73#define rPMAC_TxMACHeader3 0x12c 74#define rPMAC_TxMACHeader4 0x130 75#define rPMAC_TxMACHeader5 0x134 76#define rPMAC_TxDataType 0x138 77#define rPMAC_TxRandomSeed 0x13c 78#define rPMAC_CCKPLCPPreamble 0x140 79#define rPMAC_CCKPLCPHeader 0x144 80#define rPMAC_CCKCRC16 0x148 81#define rPMAC_OFDMRxCRC32OK 0x170 82#define rPMAC_OFDMRxCRC32Er 0x174 83#define rPMAC_OFDMRxParityEr 0x178 84#define rPMAC_OFDMRxCRC8Er 0x17c 85#define rPMAC_CCKCRxRC16Er 0x180 86#define rPMAC_CCKCRxRC32Er 0x184 87#define rPMAC_CCKCRxRC32OK 0x188 88#define rPMAC_TxStatus 0x18c 89 90/* */ 91/* 2. Page2(0x200) */ 92/* */ 93/* The following two definition are only used for USB interface. */ 94/* define RF_BB_CMD_ADDR 0x02c0 RF/BB read/write command address. */ 95/* define RF_BB_CMD_DATA 0x02c4 RF/BB read/write command data. */ 96 97/* */ 98/* 3. Page8(0x800) */ 99/* */ 100#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */ 101 102#define rFPGA0_TxInfo 0x804 /* Status report?? */ 103#define rFPGA0_PSDFunction 0x808 104 105#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 106 107#define rFPGA0_RFTiming1 0x810 /* Useless now */ 108#define rFPGA0_RFTiming2 0x814 109/* define rFPGA0_XC_RFTiming 0x818 */ 110/* define rFPGA0_XD_RFTiming 0x81c */ 111 112#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 113#define rFPGA0_XA_HSSIParameter2 0x824 114#define rFPGA0_XB_HSSIParameter1 0x828 115#define rFPGA0_XB_HSSIParameter2 0x82c 116#define rFPGA0_XC_HSSIParameter1 0x830 117#define rFPGA0_XC_HSSIParameter2 0x834 118#define rFPGA0_XD_HSSIParameter1 0x838 119#define rFPGA0_XD_HSSIParameter2 0x83c 120#define rFPGA0_XA_LSSIParameter 0x840 121#define rFPGA0_XB_LSSIParameter 0x844 122#define rFPGA0_XC_LSSIParameter 0x848 123#define rFPGA0_XD_LSSIParameter 0x84c 124 125#define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 126#define rFPGA0_RFSleepUpParameter 0x854 127 128#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 129#define rFPGA0_XCD_SwitchControl 0x85c 130 131#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 132#define rFPGA0_XB_RFInterfaceOE 0x864 133#define rFPGA0_XC_RFInterfaceOE 0x868 134#define rFPGA0_XD_RFInterfaceOE 0x86c 135 136#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 137#define rFPGA0_XCD_RFInterfaceSW 0x874 138 139#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 140#define rFPGA0_XCD_RFParameter 0x87c 141 142#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 143#define rFPGA0_AnalogParameter2 0x884 144#define rFPGA0_AnalogParameter3 0x888 /* Useless now */ 145#define rFPGA0_AnalogParameter4 0x88c 146 147#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 148#define rFPGA0_XB_LSSIReadBack 0x8a4 149#define rFPGA0_XC_LSSIReadBack 0x8a8 150#define rFPGA0_XD_LSSIReadBack 0x8ac 151 152#define rFPGA0_PSDReport 0x8b4 /* Useless now */ 153#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now RF Interface Readback Value */ 154#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 155 156/* */ 157/* 4. Page9(0x900) */ 158/* */ 159#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC RF BW Setting?? */ 160 161#define rFPGA1_TxBlock 0x904 /* Useless now */ 162#define rFPGA1_DebugSelect 0x908 /* Useless now */ 163#define rFPGA1_TxInfo 0x90c /* Useless now Status report?? */ 164 165/* */ 166/* 5. PageA(0xA00) */ 167/* */ 168/* Set Control channel to upper or lower. These settings are required only for 40MHz */ 169#define rCCK0_System 0xa00 170 171#define rCCK0_AFESetting 0xa04 /* Disable init gain now Select RX path by RSSI */ 172#define rCCK0_CCA 0xa08 /* Disable init gain now Init gain */ 173 174#define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 175#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 176 177#define rCCK0_RxHP 0xa14 178 179#define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 180#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 181 182#define rCCK0_TxFilter1 0xa20 183#define rCCK0_TxFilter2 0xa24 184#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 185#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 186#define rCCK0_TRSSIReport 0xa50 187#define rCCK0_RxReport 0xa54 /* 0xa57 */ 188#define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 189#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 190 191/* */ 192/* 6. PageC(0xC00) */ 193/* */ 194#define rOFDM0_LSTF 0xc00 195 196#define rOFDM0_TRxPathEnable 0xc04 197#define rOFDM0_TRMuxPar 0xc08 198#define rOFDM0_TRSWIsolation 0xc0c 199 200#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 201#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 202#define rOFDM0_XBRxAFE 0xc18 203#define rOFDM0_XBRxIQImbalance 0xc1c 204#define rOFDM0_XCRxAFE 0xc20 205#define rOFDM0_XCRxIQImbalance 0xc24 206#define rOFDM0_XDRxAFE 0xc28 207#define rOFDM0_XDRxIQImbalance 0xc2c 208 209#define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD DM tune init gain */ 210#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 211#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 212#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 213 214#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 215#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 216#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 217#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 218 219#define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 220#define rOFDM0_XAAGCCore2 0xc54 221#define rOFDM0_XBAGCCore1 0xc58 222#define rOFDM0_XBAGCCore2 0xc5c 223#define rOFDM0_XCAGCCore1 0xc60 224#define rOFDM0_XCAGCCore2 0xc64 225#define rOFDM0_XDAGCCore1 0xc68 226#define rOFDM0_XDAGCCore2 0xc6c 227 228#define rOFDM0_AGCParameter1 0xc70 229#define rOFDM0_AGCParameter2 0xc74 230#define rOFDM0_AGCRSSITable 0xc78 231#define rOFDM0_HTSTFAGC 0xc7c 232 233#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 234#define rOFDM0_XATxAFE 0xc84 235#define rOFDM0_XBTxIQImbalance 0xc88 236#define rOFDM0_XBTxAFE 0xc8c 237#define rOFDM0_XCTxIQImbalance 0xc90 238#define rOFDM0_XCTxAFE 0xc94 239#define rOFDM0_XDTxIQImbalance 0xc98 240#define rOFDM0_XDTxAFE 0xc9c 241#define rOFDM0_RxIQExtAnta 0xca0 242 243#define rOFDM0_RxHPParameter 0xce0 244#define rOFDM0_TxPseudoNoiseWgt 0xce4 245#define rOFDM0_FrameSync 0xcf0 246#define rOFDM0_DFSReport 0xcf4 247#define rOFDM0_TxCoeff1 0xca4 248#define rOFDM0_TxCoeff2 0xca8 249#define rOFDM0_TxCoeff3 0xcac 250#define rOFDM0_TxCoeff4 0xcb0 251#define rOFDM0_TxCoeff5 0xcb4 252#define rOFDM0_TxCoeff6 0xcb8 253 254/* 7. PageD(0xD00) */ 255#define rOFDM1_LSTF 0xd00 256#define rOFDM1_TRxPathEnable 0xd04 257 258#define rOFDM1_CFO 0xd08 /* No setting now */ 259#define rOFDM1_CSI1 0xd10 260#define rOFDM1_SBD 0xd14 261#define rOFDM1_CSI2 0xd18 262#define rOFDM1_CFOTracking 0xd2c 263#define rOFDM1_TRxMesaure1 0xd34 264#define rOFDM1_IntfDet 0xd3c 265#define rOFDM1_PseudoNoiseStateAB 0xd50 266#define rOFDM1_PseudoNoiseStateCD 0xd54 267#define rOFDM1_RxPseudoNoiseWgt 0xd58 268 269#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 270#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 271#define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 272 273#define rOFDM_ShortCFOAB 0xdac /* No setting now */ 274#define rOFDM_ShortCFOCD 0xdb0 275#define rOFDM_LongCFOAB 0xdb4 276#define rOFDM_LongCFOCD 0xdb8 277#define rOFDM_TailCFOAB 0xdbc 278#define rOFDM_TailCFOCD 0xdc0 279#define rOFDM_PWMeasure1 0xdc4 280#define rOFDM_PWMeasure2 0xdc8 281#define rOFDM_BWReport 0xdcc 282#define rOFDM_AGCReport 0xdd0 283#define rOFDM_RxSNR 0xdd4 284#define rOFDM_RxEVMCSI 0xdd8 285#define rOFDM_SIGReport 0xddc 286 287 288/* */ 289/* 8. PageE(0xE00) */ 290/* */ 291#define rTxAGC_Rate18_06 0xe00 292#define rTxAGC_Rate54_24 0xe04 293#define rTxAGC_CCK_Mcs32 0xe08 294#define rTxAGC_Mcs03_Mcs00 0xe10 295#define rTxAGC_Mcs07_Mcs04 0xe14 296#define rTxAGC_Mcs11_Mcs08 0xe18 297#define rTxAGC_Mcs15_Mcs12 0xe1c 298 299/* Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register] */ 300#define rRx_Wait_CCCA 0xe70 301#define rAnapar_Ctrl_BB 0xee0 302 303/* */ 304/* 7. RF Register 0x00-0x2E (RF 8256) */ 305/* RF-0222D 0x00-3F */ 306/* */ 307/* Zebra1 */ 308#define RTL92SE_FPGA_VERIFY 0 309#define rZebra1_HSSIEnable 0x0 /* Useless now */ 310#define rZebra1_TRxEnable1 0x1 311#define rZebra1_TRxEnable2 0x2 312#define rZebra1_AGC 0x4 313#define rZebra1_ChargePump 0x5 314/* if (RTL92SE_FPGA_VERIFY == 1) */ 315#define rZebra1_Channel 0x7 /* RF channel switch */ 316/* else */ 317 318/* endif */ 319#define rZebra1_TxGain 0x8 /* Useless now */ 320#define rZebra1_TxLPF 0x9 321#define rZebra1_RxLPF 0xb 322#define rZebra1_RxHPFCorner 0xc 323 324/* Zebra4 */ 325#define rGlobalCtrl 0 /* Useless now */ 326#define rRTL8256_TxLPF 19 327#define rRTL8256_RxLPF 11 328 329/* RTL8258 */ 330#define rRTL8258_TxLPF 0x11 /* Useless now */ 331#define rRTL8258_RxLPF 0x13 332#define rRTL8258_RSSILPF 0xa 333 334/* */ 335/* RL6052 Register definition */ 336#define RF_AC 0x00 /* */ 337 338#define RF_IQADJ_G1 0x01 /* */ 339#define RF_IQADJ_G2 0x02 /* */ 340#define RF_POW_TRSW 0x05 /* */ 341 342#define RF_GAIN_RX 0x06 /* */ 343#define RF_GAIN_TX 0x07 /* */ 344 345#define RF_TXM_IDAC 0x08 /* */ 346#define RF_BS_IQGEN 0x0F /* */ 347 348#define RF_MODE1 0x10 /* */ 349#define RF_MODE2 0x11 /* */ 350 351#define RF_RX_AGC_HP 0x12 /* */ 352#define RF_TX_AGC 0x13 /* */ 353#define RF_BIAS 0x14 /* */ 354#define RF_IPA 0x15 /* */ 355#define RF_TXBIAS 0x16 /* */ 356#define RF_POW_ABILITY 0x17 /* */ 357#define RF_MODE_AG 0x18 /* */ 358#define rRfChannel 0x18 /* RF channel and BW switch */ 359#define RF_CHNLBW 0x18 /* RF channel and BW switch */ 360#define RF_TOP 0x19 /* */ 361 362#define RF_RX_G1 0x1A /* */ 363#define RF_RX_G2 0x1B /* */ 364 365#define RF_RX_BB2 0x1C /* */ 366#define RF_RX_BB1 0x1D /* */ 367 368#define RF_RCK1 0x1E /* */ 369#define RF_RCK2 0x1F /* */ 370 371#define RF_TX_G1 0x20 /* */ 372#define RF_TX_G2 0x21 /* */ 373#define RF_TX_G3 0x22 /* */ 374 375#define RF_TX_BB1 0x23 /* */ 376 377#define RF_T_METER 0x24 /* */ 378 379#define RF_SYN_G1 0x25 /* RF TX Power control */ 380#define RF_SYN_G2 0x26 /* RF TX Power control */ 381#define RF_SYN_G3 0x27 /* RF TX Power control */ 382#define RF_SYN_G4 0x28 /* RF TX Power control */ 383#define RF_SYN_G5 0x29 /* RF TX Power control */ 384#define RF_SYN_G6 0x2A /* RF TX Power control */ 385#define RF_SYN_G7 0x2B /* RF TX Power control */ 386#define RF_SYN_G8 0x2C /* RF TX Power control */ 387 388#define RF_RCK_OS 0x30 /* RF TX PA control */ 389#define RF_TXPA_G1 0x31 /* RF TX PA control */ 390#define RF_TXPA_G2 0x32 /* RF TX PA control */ 391#define RF_TXPA_G3 0x33 /* RF TX PA control */ 392 393/* */ 394/* Bit Mask */ 395/* */ 396/* 1. Page1(0x100) */ 397#define bBBResetB 0x100 /* Useless now? */ 398#define bGlobalResetB 0x200 399#define bOFDMTxStart 0x4 400#define bCCKTxStart 0x8 401#define bCRC32Debug 0x100 402#define bPMACLoopback 0x10 403#define bTxLSIG 0xffffff 404#define bOFDMTxRate 0xf 405#define bOFDMTxReserved 0x10 406#define bOFDMTxLength 0x1ffe0 407#define bOFDMTxParity 0x20000 408#define bTxHTSIG1 0xffffff 409#define bTxHTMCSRate 0x7f 410#define bTxHTBW 0x80 411#define bTxHTLength 0xffff00 412#define bTxHTSIG2 0xffffff 413#define bTxHTSmoothing 0x1 414#define bTxHTSounding 0x2 415#define bTxHTReserved 0x4 416#define bTxHTAggreation 0x8 417#define bTxHTSTBC 0x30 418#define bTxHTAdvanceCoding 0x40 419#define bTxHTShortGI 0x80 420#define bTxHTNumberHT_LTF 0x300 421#define bTxHTCRC8 0x3fc00 422#define bCounterReset 0x10000 423#define bNumOfOFDMTx 0xffff 424#define bNumOfCCKTx 0xffff0000 425#define bTxIdleInterval 0xffff 426#define bOFDMService 0xffff0000 427#define bTxMACHeader 0xffffffff 428#define bTxDataInit 0xff 429#define bTxHTMode 0x100 430#define bTxDataType 0x30000 431#define bTxRandomSeed 0xffffffff 432#define bCCKTxPreamble 0x1 433#define bCCKTxSFD 0xffff0000 434#define bCCKTxSIG 0xff 435#define bCCKTxService 0xff00 436#define bCCKLengthExt 0x8000 437#define bCCKTxLength 0xffff0000 438#define bCCKTxCRC16 0xffff 439#define bCCKTxStatus 0x1 440#define bOFDMTxStatus 0x2 441 442#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 443 444/* 2. Page8(0x800) */ 445#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 446#define bJapanMode 0x2 447#define bCCKTxSC 0x30 448#define bCCKEn 0x1000000 449#define bOFDMEn 0x2000000 450 451#define bOFDMRxADCPhase 0x10000 /* Useless now */ 452#define bOFDMTxDACPhase 0x40000 453#define bXATxAGC 0x3f 454 455#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 456#define bXCTxAGC 0xf000 457#define bXDTxAGC 0xf0000 458 459#define bPAStart 0xf0000000 /* Useless now */ 460#define bTRStart 0x00f00000 461#define bRFStart 0x0000f000 462#define bBBStart 0x000000f0 463#define bBBCCKStart 0x0000000f 464#define bPAEnd 0xf /* Reg0x814 */ 465#define bTREnd 0x0f000000 466#define bRFEnd 0x000f0000 467#define bCCAMask 0x000000f0 /* T2R */ 468#define bR2RCCAMask 0x00000f00 469#define bHSSI_R2TDelay 0xf8000000 470#define bHSSI_T2RDelay 0xf80000 471#define bContTxHSSI 0x400 /* chane gain at continue Tx */ 472#define bIGFromCCK 0x200 473#define bAGCAddress 0x3f 474#define bRxHPTx 0x7000 475#define bRxHPT2R 0x38000 476#define bRxHPCCKIni 0xc0000 477#define bAGCTxCode 0xc00000 478#define bAGCRxCode 0x300000 479 480#define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 481#define b3WireAddressLength 0x400 482 483#define b3WireRFPowerDown 0x1 /* Useless now */ 484/* define bHWSISelect 0x8 */ 485#define b5GPAPEPolarity 0x40000000 486#define b2GPAPEPolarity 0x80000000 487#define bRFSW_TxDefaultAnt 0x3 488#define bRFSW_TxOptionAnt 0x30 489#define bRFSW_RxDefaultAnt 0x300 490#define bRFSW_RxOptionAnt 0x3000 491#define bRFSI_3WireData 0x1 492#define bRFSI_3WireClock 0x2 493#define bRFSI_3WireLoad 0x4 494#define bRFSI_3WireRW 0x8 495#define bRFSI_3Wire 0xf 496 497#define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 498 499#define bRFSI_TRSW 0x20 /* Useless now */ 500#define bRFSI_TRSWB 0x40 501#define bRFSI_ANTSW 0x100 502#define bRFSI_ANTSWB 0x200 503#define bRFSI_PAPE 0x400 504#define bRFSI_PAPE5G 0x800 505#define bBandSelect 0x1 506#define bHTSIG2_GI 0x80 507#define bHTSIG2_Smoothing 0x01 508#define bHTSIG2_Sounding 0x02 509#define bHTSIG2_Aggreaton 0x08 510#define bHTSIG2_STBC 0x30 511#define bHTSIG2_AdvCoding 0x40 512#define bHTSIG2_NumOfHTLTF 0x300 513#define bHTSIG2_CRC8 0x3fc 514#define bHTSIG1_MCS 0x7f 515#define bHTSIG1_BandWidth 0x80 516#define bHTSIG1_HTLength 0xffff 517#define bLSIG_Rate 0xf 518#define bLSIG_Reserved 0x10 519#define bLSIG_Length 0x1fffe 520#define bLSIG_Parity 0x20 521#define bCCKRxPhase 0x4 522#if (RTL92SE_FPGA_VERIFY == 1) 523#define bLSSIReadAddress 0x3f000000 /* LSSI "Read" Address 524 Reg 0x824 rFPGA0_XA_HSSIParameter2 */ 525#else 526#define bLSSIReadAddress 0x7f800000 /* T65 RF */ 527#endif 528#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 529#if (RTL92SE_FPGA_VERIFY == 1) 530#define bLSSIReadBackData 0xfff /* Reg 0x8a0 531 rFPGA0_XA_LSSIReadBack */ 532#else 533#define bLSSIReadBackData 0xfffff /* T65 RF */ 534#endif 535#define bLSSIReadOKFlag 0x1000 /* Useless now */ 536#define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 537#define bRegulator0Standby 0x1 538#define bRegulatorPLLStandby 0x2 539#define bRegulator1Standby 0x4 540#define bPLLPowerUp 0x8 541#define bDPLLPowerUp 0x10 542#define bDA10PowerUp 0x20 543#define bAD7PowerUp 0x200 544#define bDA6PowerUp 0x2000 545#define bXtalPowerUp 0x4000 546#define b40MDClkPowerUP 0x8000 547#define bDA6DebugMode 0x20000 548#define bDA6Swing 0x380000 549 550#define bADClkPhase 0x4000000 /* Reg 0x880 551 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 552 553#define b80MClkDelay 0x18000000 /* Useless */ 554#define bAFEWatchDogEnable 0x20000000 555 556#define bXtalCap01 0xc0000000 /* Reg 0x884 557 rFPGA0_AnalogParameter2 Crystal cap */ 558#define bXtalCap23 0x3 559#define bXtalCap92x 0x0f000000 560#define bXtalCap 0x0f000000 561 562#define bIntDifClkEnable 0x400 /* Useless */ 563#define bExtSigClkEnable 0x800 564#define bBandgapMbiasPowerUp 0x10000 565#define bAD11SHGain 0xc0000 566#define bAD11InputRange 0x700000 567#define bAD11OPCurrent 0x3800000 568#define bIPathLoopback 0x4000000 569#define bQPathLoopback 0x8000000 570#define bAFELoopback 0x10000000 571#define bDA10Swing 0x7e0 572#define bDA10Reverse 0x800 573#define bDAClkSource 0x1000 574#define bAD7InputRange 0x6000 575#define bAD7Gain 0x38000 576#define bAD7OutputCMMode 0x40000 577#define bAD7InputCMMode 0x380000 578#define bAD7Current 0xc00000 579#define bRegulatorAdjust 0x7000000 580#define bAD11PowerUpAtTx 0x1 581#define bDA10PSAtTx 0x10 582#define bAD11PowerUpAtRx 0x100 583#define bDA10PSAtRx 0x1000 584#define bCCKRxAGCFormat 0x200 585#define bPSDFFTSamplepPoint 0xc000 586#define bPSDAverageNum 0x3000 587#define bIQPathControl 0xc00 588#define bPSDFreq 0x3ff 589#define bPSDAntennaPath 0x30 590#define bPSDIQSwitch 0x40 591#define bPSDRxTrigger 0x400000 592#define bPSDTxTrigger 0x80000000 593#define bPSDSineToneScale 0x7f000000 594#define bPSDReport 0xffff 595 596/* 3. Page9(0x900) */ 597#define bOFDMTxSC 0x30000000 /* Useless */ 598#define bCCKTxOn 0x1 599#define bOFDMTxOn 0x2 600#define bDebugPage 0xfff /* reset debug page and HWord, 601 * LWord */ 602#define bDebugItem 0xff /* reset debug page and LWord */ 603#define bAntL 0x10 604#define bAntNonHT 0x100 605#define bAntHT1 0x1000 606#define bAntHT2 0x10000 607#define bAntHT1S1 0x100000 608#define bAntNonHTS1 0x1000000 609 610/* 4. PageA(0xA00) */ 611#define bCCKBBMode 0x3 /* Useless */ 612#define bCCKTxPowerSaving 0x80 613#define bCCKRxPowerSaving 0x40 614 615#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0 20/40 sw */ 616 617#define bCCKScramble 0x8 /* Useless */ 618#define bCCKAntDiversity 0x8000 619#define bCCKCarrierRecovery 0x4000 620#define bCCKTxRate 0x3000 621#define bCCKDCCancel 0x0800 622#define bCCKISICancel 0x0400 623#define bCCKMatchFilter 0x0200 624#define bCCKEqualizer 0x0100 625#define bCCKPreambleDetect 0x800000 626#define bCCKFastFalseCCA 0x400000 627#define bCCKChEstStart 0x300000 628#define bCCKCCACount 0x080000 629#define bCCKcs_lim 0x070000 630#define bCCKBistMode 0x80000000 631#define bCCKCCAMask 0x40000000 632#define bCCKTxDACPhase 0x4 633#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 634#define bCCKr_cp_mode0 0x0100 635#define bCCKTxDCOffset 0xf0 636#define bCCKRxDCOffset 0xf 637#define bCCKCCAMode 0xc000 638#define bCCKFalseCS_lim 0x3f00 639#define bCCKCS_ratio 0xc00000 640#define bCCKCorgBit_sel 0x300000 641#define bCCKPD_lim 0x0f0000 642#define bCCKNewCCA 0x80000000 643#define bCCKRxHPofIG 0x8000 644#define bCCKRxIG 0x7f00 645#define bCCKLNAPolarity 0x800000 646#define bCCKRx1stGain 0x7f0000 647#define bCCKRFExtend 0x20000000 /* CCK Rx init gain polar */ 648#define bCCKRxAGCSatLevel 0x1f000000 649#define bCCKRxAGCSatCount 0xe0 650#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 651#define bCCKFixedRxAGC 0x8000 652#define bCCKAntennaPolarity 0x2000 653#define bCCKTxFilterType 0x0c00 654#define bCCKRxAGCReportType 0x0300 655#define bCCKRxDAGCEn 0x80000000 656#define bCCKRxDAGCPeriod 0x20000000 657#define bCCKRxDAGCSatLevel 0x1f000000 658#define bCCKTimingRecovery 0x800000 659#define bCCKTxC0 0x3f0000 660#define bCCKTxC1 0x3f000000 661#define bCCKTxC2 0x3f 662#define bCCKTxC3 0x3f00 663#define bCCKTxC4 0x3f0000 664#define bCCKTxC5 0x3f000000 665#define bCCKTxC6 0x3f 666#define bCCKTxC7 0x3f00 667#define bCCKDebugPort 0xff0000 668#define bCCKDACDebug 0x0f000000 669#define bCCKFalseAlarmEnable 0x8000 670#define bCCKFalseAlarmRead 0x4000 671#define bCCKTRSSI 0x7f 672#define bCCKRxAGCReport 0xfe 673#define bCCKRxReport_AntSel 0x80000000 674#define bCCKRxReport_MFOff 0x40000000 675#define bCCKRxRxReport_SQLoss 0x20000000 676#define bCCKRxReport_Pktloss 0x10000000 677#define bCCKRxReport_Lockedbit 0x08000000 678#define bCCKRxReport_RateError 0x04000000 679#define bCCKRxReport_RxRate 0x03000000 680#define bCCKRxFACounterLower 0xff 681#define bCCKRxFACounterUpper 0xff000000 682#define bCCKRxHPAGCStart 0xe000 683#define bCCKRxHPAGCFinal 0x1c00 684#define bCCKRxFalseAlarmEnable 0x8000 685#define bCCKFACounterFreeze 0x4000 686#define bCCKTxPathSel 0x10000000 687#define bCCKDefaultRxPath 0xc000000 688#define bCCKOptionRxPath 0x3000000 689 690/* 5. PageC(0xC00) */ 691#define bNumOfSTF 0x3 /* Useless */ 692#define bShift_L 0xc0 693#define bGI_TH 0xc 694#define bRxPathA 0x1 695#define bRxPathB 0x2 696#define bRxPathC 0x4 697#define bRxPathD 0x8 698#define bTxPathA 0x1 699#define bTxPathB 0x2 700#define bTxPathC 0x4 701#define bTxPathD 0x8 702#define bTRSSIFreq 0x200 703#define bADCBackoff 0x3000 704#define bDFIRBackoff 0xc000 705#define bTRSSILatchPhase 0x10000 706#define bRxIDCOffset 0xff 707#define bRxQDCOffset 0xff00 708#define bRxDFIRMode 0x1800000 709#define bRxDCNFType 0xe000000 710#define bRXIQImb_A 0x3ff 711#define bRXIQImb_B 0xfc00 712#define bRXIQImb_C 0x3f0000 713#define bRXIQImb_D 0xffc00000 714#define bDC_dc_Notch 0x60000 715#define bRxNBINotch 0x1f000000 716#define bPD_TH 0xf 717#define bPD_TH_Opt2 0xc000 718#define bPWED_TH 0x700 719#define bIfMF_Win_L 0x800 720#define bPD_Option 0x1000 721#define bMF_Win_L 0xe000 722#define bBW_Search_L 0x30000 723#define bwin_enh_L 0xc0000 724#define bBW_TH 0x700000 725#define bED_TH2 0x3800000 726#define bBW_option 0x4000000 727#define bRatio_TH 0x18000000 728#define bWindow_L 0xe0000000 729#define bSBD_Option 0x1 730#define bFrame_TH 0x1c 731#define bFS_Option 0x60 732#define bDC_Slope_check 0x80 733#define bFGuard_Counter_DC_L 0xe00 734#define bFrame_Weight_Short 0x7000 735#define bSub_Tune 0xe00000 736#define bFrame_DC_Length 0xe000000 737#define bSBD_start_offset 0x30000000 738#define bFrame_TH_2 0x7 739#define bFrame_GI2_TH 0x38 740#define bGI2_Sync_en 0x40 741#define bSarch_Short_Early 0x300 742#define bSarch_Short_Late 0xc00 743#define bSarch_GI2_Late 0x70000 744#define bCFOAntSum 0x1 745#define bCFOAcc 0x2 746#define bCFOStartOffset 0xc 747#define bCFOLookBack 0x70 748#define bCFOSumWeight 0x80 749#define bDAGCEnable 0x10000 750#define bTXIQImb_A 0x3ff 751#define bTXIQImb_B 0xfc00 752#define bTXIQImb_C 0x3f0000 753#define bTXIQImb_D 0xffc00000 754#define bTxIDCOffset 0xff 755#define bTxQDCOffset 0xff00 756#define bTxDFIRMode 0x10000 757#define bTxPesudoNoiseOn 0x4000000 758#define bTxPesudoNoise_A 0xff 759#define bTxPesudoNoise_B 0xff00 760#define bTxPesudoNoise_C 0xff0000 761#define bTxPesudoNoise_D 0xff000000 762#define bCCADropOption 0x20000 763#define bCCADropThres 0xfff00000 764#define bEDCCA_H 0xf 765#define bEDCCA_L 0xf0 766#define bLambda_ED 0x300 767#define bRxInitialGain 0x7f 768#define bRxAntDivEn 0x80 769#define bRxAGCAddressForLNA 0x7f00 770#define bRxHighPowerFlow 0x8000 771#define bRxAGCFreezeThres 0xc0000 772#define bRxFreezeStep_AGC1 0x300000 773#define bRxFreezeStep_AGC2 0xc00000 774#define bRxFreezeStep_AGC3 0x3000000 775#define bRxFreezeStep_AGC0 0xc000000 776#define bRxRssi_Cmp_En 0x10000000 777#define bRxQuickAGCEn 0x20000000 778#define bRxAGCFreezeThresMode 0x40000000 779#define bRxOverFlowCheckType 0x80000000 780#define bRxAGCShift 0x7f 781#define bTRSW_Tri_Only 0x80 782#define bPowerThres 0x300 783#define bRxAGCEn 0x1 784#define bRxAGCTogetherEn 0x2 785#define bRxAGCMin 0x4 786#define bRxHP_Ini 0x7 787#define bRxHP_TRLNA 0x70 788#define bRxHP_RSSI 0x700 789#define bRxHP_BBP1 0x7000 790#define bRxHP_BBP2 0x70000 791#define bRxHP_BBP3 0x700000 792#define bRSSI_H 0x7f0000 /* thresh for hi power */ 793#define bRSSI_Gen 0x7f000000 /* thresh for ant div */ 794#define bRxSettle_TRSW 0x7 795#define bRxSettle_LNA 0x38 796#define bRxSettle_RSSI 0x1c0 797#define bRxSettle_BBP 0xe00 798#define bRxSettle_RxHP 0x7000 799#define bRxSettle_AntSW_RSSI 0x38000 800#define bRxSettle_AntSW 0xc0000 801#define bRxProcessTime_DAGC 0x300000 802#define bRxSettle_HSSI 0x400000 803#define bRxProcessTime_BBPPW 0x800000 804#define bRxAntennaPowerShift 0x3000000 805#define bRSSITableSelect 0xc000000 806#define bRxHP_Final 0x7000000 807#define bRxHTSettle_BBP 0x7 808#define bRxHTSettle_HSSI 0x8 809#define bRxHTSettle_RxHP 0x70 810#define bRxHTSettle_BBPPW 0x80 811#define bRxHTSettle_Idle 0x300 812#define bRxHTSettle_Reserved 0x1c00 813#define bRxHTRxHPEn 0x8000 814#define bRxHTAGCFreezeThres 0x30000 815#define bRxHTAGCTogetherEn 0x40000 816#define bRxHTAGCMin 0x80000 817#define bRxHTAGCEn 0x100000 818#define bRxHTDAGCEn 0x200000 819#define bRxHTRxHP_BBP 0x1c00000 820#define bRxHTRxHP_Final 0xe0000000 821#define bRxPWRatioTH 0x3 822#define bRxPWRatioEn 0x4 823#define bRxMFHold 0x3800 824#define bRxPD_Delay_TH1 0x38 825#define bRxPD_Delay_TH2 0x1c0 826#define bRxPD_DC_COUNT_MAX 0x600 827/* define bRxMF_Hold 0x3800 */ 828#define bRxPD_Delay_TH 0x8000 829#define bRxProcess_Delay 0xf0000 830#define bRxSearchrange_GI2_Early 0x700000 831#define bRxFrame_Guard_Counter_L 0x3800000 832#define bRxSGI_Guard_L 0xc000000 833#define bRxSGI_Search_L 0x30000000 834#define bRxSGI_TH 0xc0000000 835#define bDFSCnt0 0xff 836#define bDFSCnt1 0xff00 837#define bDFSFlag 0xf0000 838#define bMFWeightSum 0x300000 839#define bMinIdxTH 0x7f000000 840#define bDAFormat 0x40000 841#define bTxChEmuEnable 0x01000000 842#define bTRSWIsolation_A 0x7f 843#define bTRSWIsolation_B 0x7f00 844#define bTRSWIsolation_C 0x7f0000 845#define bTRSWIsolation_D 0x7f000000 846#define bExtLNAGain 0x7c00 847 848/* 6. PageE(0xE00) */ 849#define bSTBCEn 0x4 /* Useless */ 850#define bAntennaMapping 0x10 851#define bNss 0x20 852#define bCFOAntSumD 0x200 853#define bPHYCounterReset 0x8000000 854#define bCFOReportGet 0x4000000 855#define bOFDMContinueTx 0x10000000 856#define bOFDMSingleCarrier 0x20000000 857#define bOFDMSingleTone 0x40000000 858/* define bRxPath1 0x01 */ 859/* define bRxPath2 0x02 */ 860/* define bRxPath3 0x04 */ 861/* define bRxPath4 0x08 */ 862/* define bTxPath1 0x10 */ 863/* define bTxPath2 0x20 */ 864#define bHTDetect 0x100 865#define bCFOEn 0x10000 866#define bCFOValue 0xfff00000 867#define bSigTone_Re 0x3f 868#define bSigTone_Im 0x7f00 869#define bCounter_CCA 0xffff 870#define bCounter_ParityFail 0xffff0000 871#define bCounter_RateIllegal 0xffff 872#define bCounter_CRC8Fail 0xffff0000 873#define bCounter_MCSNoSupport 0xffff 874#define bCounter_FastSync 0xffff 875#define bShortCFO 0xfff 876#define bShortCFOTLength 12 /* total */ 877#define bShortCFOFLength 11 /* fraction */ 878#define bLongCFO 0x7ff 879#define bLongCFOTLength 11 880#define bLongCFOFLength 11 881#define bTailCFO 0x1fff 882#define bTailCFOTLength 13 883#define bTailCFOFLength 12 884#define bmax_en_pwdB 0xffff 885#define bCC_power_dB 0xffff0000 886#define bnoise_pwdB 0xffff 887#define bPowerMeasTLength 10 888#define bPowerMeasFLength 3 889#define bRx_HT_BW 0x1 890#define bRxSC 0x6 891#define bRx_HT 0x8 892#define bNB_intf_det_on 0x1 893#define bIntf_win_len_cfg 0x30 894#define bNB_Intf_TH_cfg 0x1c0 895#define bRFGain 0x3f 896#define bTableSel 0x40 897#define bTRSW 0x80 898#define bRxSNR_A 0xff 899#define bRxSNR_B 0xff00 900#define bRxSNR_C 0xff0000 901#define bRxSNR_D 0xff000000 902#define bSNREVMTLength 8 903#define bSNREVMFLength 1 904#define bCSI1st 0xff 905#define bCSI2nd 0xff00 906#define bRxEVM1st 0xff0000 907#define bRxEVM2nd 0xff000000 908#define bSIGEVM 0xff 909#define bPWDB 0xff00 910#define bSGIEN 0x10000 911 912#define bSFactorQAM1 0xf /* Useless */ 913#define bSFactorQAM2 0xf0 914#define bSFactorQAM3 0xf00 915#define bSFactorQAM4 0xf000 916#define bSFactorQAM5 0xf0000 917#define bSFactorQAM6 0xf0000 918#define bSFactorQAM7 0xf00000 919#define bSFactorQAM8 0xf000000 920#define bSFactorQAM9 0xf0000000 921#define bCSIScheme 0x100000 922 923#define bNoiseLvlTopSet 0x3 /* Useless */ 924#define bChSmooth 0x4 925#define bChSmoothCfg1 0x38 926#define bChSmoothCfg2 0x1c0 927#define bChSmoothCfg3 0xe00 928#define bChSmoothCfg4 0x7000 929#define bMRCMode 0x800000 930#define bTHEVMCfg 0x7000000 931 932#define bLoopFitType 0x1 /* Useless */ 933#define bUpdCFO 0x40 934#define bUpdCFOOffData 0x80 935#define bAdvUpdCFO 0x100 936#define bAdvTimeCtrl 0x800 937#define bUpdClko 0x1000 938#define bFC 0x6000 939#define bTrackingMode 0x8000 940#define bPhCmpEnable 0x10000 941#define bUpdClkoLTF 0x20000 942#define bComChCFO 0x40000 943#define bCSIEstiMode 0x80000 944#define bAdvUpdEqz 0x100000 945#define bUChCfg 0x7000000 946#define bUpdEqz 0x8000000 947 948#define bTxAGCRate18_06 0x7f7f7f7f /* Useless */ 949#define bTxAGCRate54_24 0x7f7f7f7f 950#define bTxAGCRateMCS32 0x7f 951#define bTxAGCRateCCK 0x7f00 952#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f 953#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f 954#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f 955#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f 956 957/* Rx Pseduo noise */ 958#define bRxPesudoNoiseOn 0x20000000 /* Useless */ 959#define bRxPesudoNoise_A 0xff 960#define bRxPesudoNoise_B 0xff00 961#define bRxPesudoNoise_C 0xff0000 962#define bRxPesudoNoise_D 0xff000000 963#define bPesudoNoiseState_A 0xffff 964#define bPesudoNoiseState_B 0xffff0000 965#define bPesudoNoiseState_C 0xffff 966#define bPesudoNoiseState_D 0xffff0000 967 968/* 7. RF Register */ 969/* Zebra1 */ 970#define bZebra1_HSSIEnable 0x8 /* Useless */ 971#define bZebra1_TRxControl 0xc00 972#define bZebra1_TRxGainSetting 0x07f 973#define bZebra1_RxCorner 0xc00 974#define bZebra1_TxChargePump 0x38 975#define bZebra1_RxChargePump 0x7 976#define bZebra1_ChannelNum 0xf80 977#define bZebra1_TxLPFBW 0x400 978#define bZebra1_RxLPFBW 0x600 979 980/* Zebra4 */ 981#define bRTL8256RegModeCtrl1 0x100 /* Useless */ 982#define bRTL8256RegModeCtrl0 0x40 983#define bRTL8256_TxLPFBW 0x18 984#define bRTL8256_RxLPFBW 0x600 985 986/* RTL8258 */ 987#define bRTL8258_TxLPFBW 0xc /* Useless */ 988#define bRTL8258_RxLPFBW 0xc00 989#define bRTL8258_RSSILPFBW 0xc0 990 991 992/* */ 993/* Other Definition */ 994/* */ 995 996/* byte endable for sb_write */ 997#define bByte0 0x1 /* Useless */ 998#define bByte1 0x2 999#define bByte2 0x4 1000#define bByte3 0x8
1001#define bWord0 0x3 1002#define bWord1 0xc 1003#define bDWord 0xf 1004 1005/* for PutRegsetting & GetRegSetting BitMask */ 1006#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1007#define bMaskByte1 0xff00 1008#define bMaskByte2 0xff0000 1009#define bMaskByte3 0xff000000 1010#define bMaskHWord 0xffff0000 1011#define bMaskLWord 0x0000ffff 1012#define bMaskDWord 0xffffffff 1013#define bMaskH4Bits 0xf0000000 1014#define bMaskOFDM_D 0xffc00000 1015#define bMaskCCK 0x3f3f3f3f 1016#define bMask12Bits 0xfff 1017 1018/* for PutRFRegsetting & GetRFRegSetting BitMask */ 1019#if (RTL92SE_FPGA_VERIFY == 1) 1020#define bRFRegOffsetMask 0xfff 1021#else 1022#define bRFRegOffsetMask 0xfffff 1023#endif 1024#define bEnable 0x1 /* Useless */ 1025#define bDisabl 0x0 1026 1027#define LeftAntenna 0x0 /* Useless */ 1028#define RightAntenna 0x1 1029 1030#define tCheckTxStatus 500 /* 500ms Useless */ 1031#define tUpdateRxCounter 100 /* 100ms */ 1032 1033#define rateCCK 0 /* Useless */ 1034#define rateOFDM 1 1035#define rateHT 2 1036 1037/* define Register-End */ 1038#define bPMAC_End 0x1ff /* Useless */ 1039#define bFPGAPHY0_End 0x8ff 1040#define bFPGAPHY1_End 0x9ff 1041#define bCCKPHY0_End 0xaff 1042#define bOFDMPHY0_End 0xcff 1043#define bOFDMPHY1_End 0xdff 1044 1045/* define max debug item in each debug page */ 1046/* define bMaxItem_FPGA_PHY0 0x9 */ 1047/* define bMaxItem_FPGA_PHY1 0x3 */ 1048/* define bMaxItem_PHY_11B 0x16 */ 1049/* define bMaxItem_OFDM_PHY0 0x29 */ 1050/* define bMaxItem_OFDM_PHY1 0x0 */ 1051 1052#define bPMACControl 0x0 /* Useless */ 1053#define bWMACControl 0x1 1054#define bWNICControl 0x2 1055 1056#define RCR_AAP BIT(0) /* accept all physical address */ 1057#define RCR_APM BIT(1) /* accept physical match */ 1058#define RCR_AM BIT(2) /* accept multicast */ 1059#define RCR_AB BIT(3) /* accept broadcast */ 1060#define RCR_ACRC32 BIT(5) /* accept error packet */ 1061#define RCR_9356SEL BIT(6) 1062#define RCR_AICV BIT(12) /* Accept ICV error packet */ 1063#define RCR_RXFTH0 (BIT(13)|BIT(14)|BIT(15)) /* Rx FIFO threshold */ 1064#define RCR_ADF BIT(18) /* Accept Data(frame type) frame */ 1065#define RCR_ACF BIT(19) /* Accept control frame */ 1066#define RCR_AMF BIT(20) /* Accept management frame */ 1067#define RCR_ADD3 BIT(21) 1068#define RCR_APWRMGT BIT(22) /* Accept power management packet */ 1069#define RCR_CBSSID BIT(23) /* Accept BSSID match packet */ 1070#define RCR_ENMARP BIT(28) /* enable mac auto reset phy */ 1071#define RCR_EnCS1 BIT(29) /* enable carrier sense method 1 */ 1072#define RCR_EnCS2 BIT(30) /* enable carrier sense method 2 */ 1073#define RCR_OnlyErlPkt BIT(31) /* Rx Early mode is performed for 1074 * packet size greater than 1536 */ 1075 1076/*--------------------------Define Parameters-------------------------------*/ 1077 1078 1079#endif /* __INC_HAL8192SPHYREG_H */ 1080