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7#ifndef __SOUND_HDA_REGISTER_H
8#define __SOUND_HDA_REGISTER_H
9
10#include <linux/io.h>
11#include <sound/hdaudio.h>
12
13#define AZX_REG_GCAP 0x00
14#define AZX_GCAP_64OK (1 << 0)
15#define AZX_GCAP_NSDO (3 << 1)
16#define AZX_GCAP_BSS (31 << 3)
17#define AZX_GCAP_ISS (15 << 8)
18#define AZX_GCAP_OSS (15 << 12)
19#define AZX_REG_VMIN 0x02
20#define AZX_REG_VMAJ 0x03
21#define AZX_REG_OUTPAY 0x04
22#define AZX_REG_INPAY 0x06
23#define AZX_REG_GCTL 0x08
24#define AZX_GCTL_RESET (1 << 0)
25#define AZX_GCTL_FCNTRL (1 << 1)
26#define AZX_GCTL_UNSOL (1 << 8)
27#define AZX_REG_WAKEEN 0x0c
28#define AZX_REG_STATESTS 0x0e
29#define AZX_REG_GSTS 0x10
30#define AZX_GSTS_FSTS (1 << 1)
31#define AZX_REG_GCAP2 0x12
32#define AZX_REG_LLCH 0x14
33#define AZX_REG_OUTSTRMPAY 0x18
34#define AZX_REG_INSTRMPAY 0x1A
35#define AZX_REG_INTCTL 0x20
36#define AZX_REG_INTSTS 0x24
37#define AZX_REG_WALLCLK 0x30
38#define AZX_REG_OLD_SSYNC 0x34
39#define AZX_REG_SSYNC 0x38
40#define AZX_REG_CORBLBASE 0x40
41#define AZX_REG_CORBUBASE 0x44
42#define AZX_REG_CORBWP 0x48
43#define AZX_REG_CORBRP 0x4a
44#define AZX_CORBRP_RST (1 << 15)
45#define AZX_REG_CORBCTL 0x4c
46#define AZX_CORBCTL_RUN (1 << 1)
47#define AZX_CORBCTL_CMEIE (1 << 0)
48#define AZX_REG_CORBSTS 0x4d
49#define AZX_CORBSTS_CMEI (1 << 0)
50#define AZX_REG_CORBSIZE 0x4e
51
52#define AZX_REG_RIRBLBASE 0x50
53#define AZX_REG_RIRBUBASE 0x54
54#define AZX_REG_RIRBWP 0x58
55#define AZX_RIRBWP_RST (1 << 15)
56#define AZX_REG_RINTCNT 0x5a
57#define AZX_REG_RIRBCTL 0x5c
58#define AZX_RBCTL_IRQ_EN (1 << 0)
59#define AZX_RBCTL_DMA_EN (1 << 1)
60#define AZX_RBCTL_OVERRUN_EN (1 << 2)
61#define AZX_REG_RIRBSTS 0x5d
62#define AZX_RBSTS_IRQ (1 << 0)
63#define AZX_RBSTS_OVERRUN (1 << 2)
64#define AZX_REG_RIRBSIZE 0x5e
65
66#define AZX_REG_IC 0x60
67#define AZX_REG_IR 0x64
68#define AZX_REG_IRS 0x68
69#define AZX_IRS_VALID (1<<1)
70#define AZX_IRS_BUSY (1<<0)
71
72#define AZX_REG_DPLBASE 0x70
73#define AZX_REG_DPUBASE 0x74
74#define AZX_DPLBASE_ENABLE 0x1
75
76
77enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
78
79
80#define AZX_REG_SD_CTL 0x00
81#define AZX_REG_SD_STS 0x03
82#define AZX_REG_SD_LPIB 0x04
83#define AZX_REG_SD_CBL 0x08
84#define AZX_REG_SD_LVI 0x0c
85#define AZX_REG_SD_FIFOW 0x0e
86#define AZX_REG_SD_FIFOSIZE 0x10
87#define AZX_REG_SD_FORMAT 0x12
88#define AZX_REG_SD_FIFOL 0x14
89#define AZX_REG_SD_BDLPL 0x18
90#define AZX_REG_SD_BDLPU 0x1c
91
92
93#define AZX_REG_LLCH 0x14
94
95#define AZX_REG_GTS_BASE 0x520
96
97#define AZX_REG_GTSCC (AZX_REG_GTS_BASE + 0x00)
98#define AZX_REG_WALFCC (AZX_REG_GTS_BASE + 0x04)
99#define AZX_REG_TSCCL (AZX_REG_GTS_BASE + 0x08)
100#define AZX_REG_TSCCU (AZX_REG_GTS_BASE + 0x0C)
101#define AZX_REG_LLPFOC (AZX_REG_GTS_BASE + 0x14)
102#define AZX_REG_LLPCL (AZX_REG_GTS_BASE + 0x18)
103#define AZX_REG_LLPCU (AZX_REG_GTS_BASE + 0x1C)
104
105
106#define AZX_REG_HSW_EM4 0x100c
107#define AZX_REG_HSW_EM5 0x1010
108
109
110#define AZX_REG_SKL_EM4L 0x1040
111
112
113#define AZX_PCIREG_TCSEL 0x44
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118
119
120#define BDL_SIZE 4096
121#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
122#define AZX_MAX_FRAG 32
123
124#define AZX_MAX_BUF_SIZE (1024*1024*1024)
125
126
127#define RIRB_INT_RESPONSE 0x01
128#define RIRB_INT_OVERRUN 0x04
129#define RIRB_INT_MASK 0x05
130
131
132#define STATESTS_INT_MASK ((1 << HDA_MAX_CODECS) - 1)
133
134
135#define SD_CTL_STREAM_RESET 0x01
136#define SD_CTL_DMA_START 0x02
137#define SD_CTL_STRIPE (3 << 16)
138#define SD_CTL_TRAFFIC_PRIO (1 << 18)
139#define SD_CTL_DIR (1 << 19)
140#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
141#define SD_CTL_STREAM_TAG_SHIFT 20
142
143
144#define SD_INT_DESC_ERR 0x10
145#define SD_INT_FIFO_ERR 0x08
146#define SD_INT_COMPLETE 0x04
147#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
148 SD_INT_COMPLETE)
149
150
151#define SD_STS_FIFO_READY 0x20
152
153
154#define AZX_INT_ALL_STREAM 0xff
155#define AZX_INT_CTRL_EN 0x40000000
156#define AZX_INT_GLOBAL_EN 0x80000000
157
158
159#define AZX_MAX_CORB_ENTRIES 256
160#define AZX_MAX_RIRB_ENTRIES 256
161
162
163#define AZX_REG_CAP_HDR 0x0
164#define AZX_CAP_HDR_VER_OFF 28
165#define AZX_CAP_HDR_VER_MASK (0xF << AZX_CAP_HDR_VER_OFF)
166#define AZX_CAP_HDR_ID_OFF 16
167#define AZX_CAP_HDR_ID_MASK (0xFFF << AZX_CAP_HDR_ID_OFF)
168#define AZX_CAP_HDR_NXT_PTR_MASK 0xFFFF
169
170
171#define AZX_SPB_CAP_ID 0x4
172#define AZX_REG_SPB_BASE_ADDR 0x700
173#define AZX_REG_SPB_SPBFCH 0x00
174#define AZX_REG_SPB_SPBFCCTL 0x04
175
176#define AZX_SPB_BASE 0x08
177
178#define AZX_SPB_INTERVAL 0x08
179
180#define AZX_SPB_SPIB 0x00
181
182#define AZX_SPB_MAXFIFO 0x04
183
184
185#define AZX_GTS_CAP_ID 0x1
186#define AZX_REG_GTS_GTSCH 0x00
187#define AZX_REG_GTS_GTSCD 0x04
188#define AZX_REG_GTS_GTSCTLAC 0x0C
189#define AZX_GTS_BASE 0x20
190#define AZX_GTS_INTERVAL 0x20
191
192
193#define AZX_PP_CAP_ID 0x3
194#define AZX_REG_PP_PPCH 0x10
195#define AZX_REG_PP_PPCTL 0x04
196#define AZX_PPCTL_PIE (1<<31)
197#define AZX_PPCTL_GPROCEN (1<<30)
198
199#define AZX_PPCTL_PROCEN(_X_) (1<<(_X_))
200
201#define AZX_REG_PP_PPSTS 0x08
202
203#define AZX_PPHC_BASE 0x10
204#define AZX_PPHC_INTERVAL 0x10
205
206#define AZX_REG_PPHCLLPL 0x0
207#define AZX_REG_PPHCLLPU 0x4
208#define AZX_REG_PPHCLDPL 0x8
209#define AZX_REG_PPHCLDPU 0xC
210
211#define AZX_PPLC_BASE 0x10
212#define AZX_PPLC_MULTI 0x10
213#define AZX_PPLC_INTERVAL 0x10
214
215#define AZX_REG_PPLCCTL 0x0
216#define AZX_PPLCCTL_STRM_BITS 4
217#define AZX_PPLCCTL_STRM_SHIFT 20
218#define AZX_REG_MASK(bit_num, offset) \
219 (((1 << (bit_num)) - 1) << (offset))
220#define AZX_PPLCCTL_STRM_MASK \
221 AZX_REG_MASK(AZX_PPLCCTL_STRM_BITS, AZX_PPLCCTL_STRM_SHIFT)
222#define AZX_PPLCCTL_RUN (1<<1)
223#define AZX_PPLCCTL_STRST (1<<0)
224
225#define AZX_REG_PPLCFMT 0x4
226#define AZX_REG_PPLCLLPL 0x8
227#define AZX_REG_PPLCLLPU 0xC
228
229
230#define AZX_ML_CAP_ID 0x2
231#define AZX_REG_ML_MLCH 0x00
232#define AZX_REG_ML_MLCD 0x04
233#define AZX_ML_BASE 0x40
234#define AZX_ML_INTERVAL 0x40
235
236#define AZX_REG_ML_LCAP 0x00
237#define AZX_REG_ML_LCTL 0x04
238#define AZX_REG_ML_LOSIDV 0x08
239#define AZX_REG_ML_LSDIID 0x0C
240#define AZX_REG_ML_LPSOO 0x10
241#define AZX_REG_ML_LPSIO 0x12
242#define AZX_REG_ML_LWALFC 0x18
243#define AZX_REG_ML_LOUTPAY 0x20
244#define AZX_REG_ML_LINPAY 0x30
245
246#define AZX_MLCTL_SPA (1<<16)
247#define AZX_MLCTL_CPA 23
248
249
250
251#define AZX_DRSM_CAP_ID 0x5
252#define AZX_REG_DRSM_CTL 0x4
253
254#define AZX_DRSM_BASE 0x08
255
256#define AZX_DRSM_INTERVAL 0x08
257
258
259#define GTSCC_TSCCD_MASK 0x80000000
260#define GTSCC_TSCCD_SHIFT BIT(31)
261#define GTSCC_TSCCI_MASK 0x20
262#define GTSCC_CDMAS_DMA_DIR_SHIFT 4
263
264#define WALFCC_CIF_MASK 0x1FF
265#define WALFCC_FN_SHIFT 9
266#define HDA_CLK_CYCLES_PER_FRAME 512
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273#define HDA_MAX_CYCLE_VALUE 499
274#define HDA_MAX_CYCLE_OFFSET 10
275#define HDA_MAX_CYCLE_READ_RETRY 10
276
277#define TSCCU_CCU_SHIFT 32
278#define LLPC_CCU_SHIFT 32
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283
284static inline unsigned int
285snd_hdac_stream_get_pos_lpib(struct hdac_stream *stream)
286{
287 return snd_hdac_stream_readl(stream, SD_LPIB);
288}
289
290static inline unsigned int
291snd_hdac_stream_get_pos_posbuf(struct hdac_stream *stream)
292{
293 return le32_to_cpu(*stream->posbuf);
294}
295
296#endif
297