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32#ifndef __AMDGPU_DRM_H__
33#define __AMDGPU_DRM_H__
34
35#include "drm.h"
36
37#if defined(__cplusplus)
38extern "C" {
39#endif
40
41#define DRM_AMDGPU_GEM_CREATE 0x00
42#define DRM_AMDGPU_GEM_MMAP 0x01
43#define DRM_AMDGPU_CTX 0x02
44#define DRM_AMDGPU_BO_LIST 0x03
45#define DRM_AMDGPU_CS 0x04
46#define DRM_AMDGPU_INFO 0x05
47#define DRM_AMDGPU_GEM_METADATA 0x06
48#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
49#define DRM_AMDGPU_GEM_VA 0x08
50#define DRM_AMDGPU_WAIT_CS 0x09
51#define DRM_AMDGPU_GEM_OP 0x10
52#define DRM_AMDGPU_GEM_USERPTR 0x11
53
54#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
55#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
56#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
57#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
58#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
59#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
60#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
61#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
62#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
63#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
64#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
65#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
66
67#define AMDGPU_GEM_DOMAIN_CPU 0x1
68#define AMDGPU_GEM_DOMAIN_GTT 0x2
69#define AMDGPU_GEM_DOMAIN_VRAM 0x4
70#define AMDGPU_GEM_DOMAIN_GDS 0x8
71#define AMDGPU_GEM_DOMAIN_GWS 0x10
72#define AMDGPU_GEM_DOMAIN_OA 0x20
73
74
75#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
76
77#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
78
79#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
80
81#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
82
83#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
84
85struct drm_amdgpu_gem_create_in {
86
87 __u64 bo_size;
88
89 __u64 alignment;
90
91 __u64 domains;
92
93 __u64 domain_flags;
94};
95
96struct drm_amdgpu_gem_create_out {
97
98 __u32 handle;
99 __u32 _pad;
100};
101
102union drm_amdgpu_gem_create {
103 struct drm_amdgpu_gem_create_in in;
104 struct drm_amdgpu_gem_create_out out;
105};
106
107
108#define AMDGPU_BO_LIST_OP_CREATE 0
109
110#define AMDGPU_BO_LIST_OP_DESTROY 1
111
112#define AMDGPU_BO_LIST_OP_UPDATE 2
113
114struct drm_amdgpu_bo_list_in {
115
116 __u32 operation;
117
118 __u32 list_handle;
119
120 __u32 bo_number;
121
122 __u32 bo_info_size;
123
124 __u64 bo_info_ptr;
125};
126
127struct drm_amdgpu_bo_list_entry {
128
129 __u32 bo_handle;
130
131 __u32 bo_priority;
132};
133
134struct drm_amdgpu_bo_list_out {
135
136 __u32 list_handle;
137 __u32 _pad;
138};
139
140union drm_amdgpu_bo_list {
141 struct drm_amdgpu_bo_list_in in;
142 struct drm_amdgpu_bo_list_out out;
143};
144
145
146#define AMDGPU_CTX_OP_ALLOC_CTX 1
147#define AMDGPU_CTX_OP_FREE_CTX 2
148#define AMDGPU_CTX_OP_QUERY_STATE 3
149
150
151#define AMDGPU_CTX_NO_RESET 0
152
153#define AMDGPU_CTX_GUILTY_RESET 1
154
155#define AMDGPU_CTX_INNOCENT_RESET 2
156
157#define AMDGPU_CTX_UNKNOWN_RESET 3
158
159struct drm_amdgpu_ctx_in {
160
161 __u32 op;
162
163 __u32 flags;
164 __u32 ctx_id;
165 __u32 _pad;
166};
167
168union drm_amdgpu_ctx_out {
169 struct {
170 __u32 ctx_id;
171 __u32 _pad;
172 } alloc;
173
174 struct {
175
176 __u64 flags;
177
178 __u32 hangs;
179
180 __u32 reset_status;
181 } state;
182};
183
184union drm_amdgpu_ctx {
185 struct drm_amdgpu_ctx_in in;
186 union drm_amdgpu_ctx_out out;
187};
188
189
190
191
192
193
194#define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
195#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
196#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
197#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
198
199struct drm_amdgpu_gem_userptr {
200 __u64 addr;
201 __u64 size;
202
203 __u32 flags;
204
205 __u32 handle;
206};
207
208
209#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
210#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
211#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
212#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
213#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
214#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
215#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
216#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
217#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
218#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
219#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
220#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
221#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
222#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
223#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
224#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
225
226#define AMDGPU_TILING_SET(field, value) \
227 (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
228#define AMDGPU_TILING_GET(value, field) \
229 (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
230
231#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
232#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
233
234
235struct drm_amdgpu_gem_metadata {
236
237 __u32 handle;
238
239 __u32 op;
240 struct {
241
242 __u64 flags;
243
244 __u64 tiling_info;
245 __u32 data_size_bytes;
246 __u32 data[64];
247 } data;
248};
249
250struct drm_amdgpu_gem_mmap_in {
251
252 __u32 handle;
253 __u32 _pad;
254};
255
256struct drm_amdgpu_gem_mmap_out {
257
258 __u64 addr_ptr;
259};
260
261union drm_amdgpu_gem_mmap {
262 struct drm_amdgpu_gem_mmap_in in;
263 struct drm_amdgpu_gem_mmap_out out;
264};
265
266struct drm_amdgpu_gem_wait_idle_in {
267
268 __u32 handle;
269
270 __u32 flags;
271
272 __u64 timeout;
273};
274
275struct drm_amdgpu_gem_wait_idle_out {
276
277 __u32 status;
278
279 __u32 domain;
280};
281
282union drm_amdgpu_gem_wait_idle {
283 struct drm_amdgpu_gem_wait_idle_in in;
284 struct drm_amdgpu_gem_wait_idle_out out;
285};
286
287struct drm_amdgpu_wait_cs_in {
288
289 __u64 handle;
290
291 __u64 timeout;
292 __u32 ip_type;
293 __u32 ip_instance;
294 __u32 ring;
295 __u32 ctx_id;
296};
297
298struct drm_amdgpu_wait_cs_out {
299
300 __u64 status;
301};
302
303union drm_amdgpu_wait_cs {
304 struct drm_amdgpu_wait_cs_in in;
305 struct drm_amdgpu_wait_cs_out out;
306};
307
308#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
309#define AMDGPU_GEM_OP_SET_PLACEMENT 1
310
311
312struct drm_amdgpu_gem_op {
313
314 __u32 handle;
315
316 __u32 op;
317
318 __u64 value;
319};
320
321#define AMDGPU_VA_OP_MAP 1
322#define AMDGPU_VA_OP_UNMAP 2
323
324
325#define AMDGPU_VM_DELAY_UPDATE (1 << 0)
326
327
328
329#define AMDGPU_VM_PAGE_READABLE (1 << 1)
330
331#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
332
333#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
334
335struct drm_amdgpu_gem_va {
336
337 __u32 handle;
338 __u32 _pad;
339
340 __u32 operation;
341
342 __u32 flags;
343
344 __u64 va_address;
345
346 __u64 offset_in_bo;
347
348 __u64 map_size;
349};
350
351#define AMDGPU_HW_IP_GFX 0
352#define AMDGPU_HW_IP_COMPUTE 1
353#define AMDGPU_HW_IP_DMA 2
354#define AMDGPU_HW_IP_UVD 3
355#define AMDGPU_HW_IP_VCE 4
356#define AMDGPU_HW_IP_NUM 5
357
358#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
359
360#define AMDGPU_CHUNK_ID_IB 0x01
361#define AMDGPU_CHUNK_ID_FENCE 0x02
362#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
363
364struct drm_amdgpu_cs_chunk {
365 __u32 chunk_id;
366 __u32 length_dw;
367 __u64 chunk_data;
368};
369
370struct drm_amdgpu_cs_in {
371
372 __u32 ctx_id;
373
374 __u32 bo_list_handle;
375 __u32 num_chunks;
376 __u32 _pad;
377
378 __u64 chunks;
379};
380
381struct drm_amdgpu_cs_out {
382 __u64 handle;
383};
384
385union drm_amdgpu_cs {
386 struct drm_amdgpu_cs_in in;
387 struct drm_amdgpu_cs_out out;
388};
389
390
391
392
393#define AMDGPU_IB_FLAG_CE (1<<0)
394
395
396#define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
397
398struct drm_amdgpu_cs_chunk_ib {
399 __u32 _pad;
400
401 __u32 flags;
402
403 __u64 va_start;
404
405 __u32 ib_bytes;
406
407 __u32 ip_type;
408
409 __u32 ip_instance;
410
411 __u32 ring;
412};
413
414struct drm_amdgpu_cs_chunk_dep {
415 __u32 ip_type;
416 __u32 ip_instance;
417 __u32 ring;
418 __u32 ctx_id;
419 __u64 handle;
420};
421
422struct drm_amdgpu_cs_chunk_fence {
423 __u32 handle;
424 __u32 offset;
425};
426
427struct drm_amdgpu_cs_chunk_data {
428 union {
429 struct drm_amdgpu_cs_chunk_ib ib_data;
430 struct drm_amdgpu_cs_chunk_fence fence_data;
431 };
432};
433
434
435
436
437
438#define AMDGPU_IDS_FLAGS_FUSION 0x1
439
440
441#define AMDGPU_INFO_ACCEL_WORKING 0x00
442
443#define AMDGPU_INFO_CRTC_FROM_ID 0x01
444
445#define AMDGPU_INFO_HW_IP_INFO 0x02
446
447#define AMDGPU_INFO_HW_IP_COUNT 0x03
448
449#define AMDGPU_INFO_TIMESTAMP 0x05
450
451#define AMDGPU_INFO_FW_VERSION 0x0e
452
453 #define AMDGPU_INFO_FW_VCE 0x1
454
455 #define AMDGPU_INFO_FW_UVD 0x2
456
457 #define AMDGPU_INFO_FW_GMC 0x03
458
459 #define AMDGPU_INFO_FW_GFX_ME 0x04
460
461 #define AMDGPU_INFO_FW_GFX_PFP 0x05
462
463 #define AMDGPU_INFO_FW_GFX_CE 0x06
464
465 #define AMDGPU_INFO_FW_GFX_RLC 0x07
466
467 #define AMDGPU_INFO_FW_GFX_MEC 0x08
468
469 #define AMDGPU_INFO_FW_SMC 0x0a
470
471 #define AMDGPU_INFO_FW_SDMA 0x0b
472
473#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
474
475#define AMDGPU_INFO_VRAM_USAGE 0x10
476
477#define AMDGPU_INFO_GTT_USAGE 0x11
478
479#define AMDGPU_INFO_GDS_CONFIG 0x13
480
481#define AMDGPU_INFO_VRAM_GTT 0x14
482
483#define AMDGPU_INFO_READ_MMR_REG 0x15
484
485#define AMDGPU_INFO_DEV_INFO 0x16
486
487#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
488
489#define AMDGPU_INFO_NUM_EVICTIONS 0x18
490
491#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
492#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
493#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
494#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
495
496struct drm_amdgpu_query_fw {
497
498 __u32 fw_type;
499
500
501
502
503 __u32 ip_instance;
504
505
506
507
508 __u32 index;
509 __u32 _pad;
510};
511
512
513struct drm_amdgpu_info {
514
515 __u64 return_pointer;
516
517
518 __u32 return_size;
519
520 __u32 query;
521
522 union {
523 struct {
524 __u32 id;
525 __u32 _pad;
526 } mode_crtc;
527
528 struct {
529
530 __u32 type;
531
532
533
534
535 __u32 ip_instance;
536 } query_hw_ip;
537
538 struct {
539 __u32 dword_offset;
540
541 __u32 count;
542 __u32 instance;
543
544 __u32 flags;
545 } read_mmr_reg;
546
547 struct drm_amdgpu_query_fw query_fw;
548 };
549};
550
551struct drm_amdgpu_info_gds {
552
553 __u32 gds_gfx_partition_size;
554
555 __u32 compute_partition_size;
556
557 __u32 gds_total_size;
558
559 __u32 gws_per_gfx_partition;
560
561 __u32 gws_per_compute_partition;
562
563 __u32 oa_per_gfx_partition;
564
565 __u32 oa_per_compute_partition;
566 __u32 _pad;
567};
568
569struct drm_amdgpu_info_vram_gtt {
570 __u64 vram_size;
571 __u64 vram_cpu_accessible_size;
572 __u64 gtt_size;
573};
574
575struct drm_amdgpu_info_firmware {
576 __u32 ver;
577 __u32 feature;
578};
579
580#define AMDGPU_VRAM_TYPE_UNKNOWN 0
581#define AMDGPU_VRAM_TYPE_GDDR1 1
582#define AMDGPU_VRAM_TYPE_DDR2 2
583#define AMDGPU_VRAM_TYPE_GDDR3 3
584#define AMDGPU_VRAM_TYPE_GDDR4 4
585#define AMDGPU_VRAM_TYPE_GDDR5 5
586#define AMDGPU_VRAM_TYPE_HBM 6
587#define AMDGPU_VRAM_TYPE_DDR3 7
588
589struct drm_amdgpu_info_device {
590
591 __u32 device_id;
592
593 __u32 chip_rev;
594 __u32 external_rev;
595
596 __u32 pci_rev;
597 __u32 family;
598 __u32 num_shader_engines;
599 __u32 num_shader_arrays_per_engine;
600
601 __u32 gpu_counter_freq;
602 __u64 max_engine_clock;
603 __u64 max_memory_clock;
604
605 __u32 cu_active_number;
606 __u32 cu_ao_mask;
607 __u32 cu_bitmap[4][4];
608
609 __u32 enabled_rb_pipes_mask;
610 __u32 num_rb_pipes;
611 __u32 num_hw_gfx_contexts;
612 __u32 _pad;
613 __u64 ids_flags;
614
615 __u64 virtual_address_offset;
616
617 __u64 virtual_address_max;
618
619 __u32 virtual_address_alignment;
620
621 __u32 pte_fragment_size;
622 __u32 gart_page_size;
623
624 __u32 ce_ram_size;
625
626 __u32 vram_type;
627
628 __u32 vram_bit_width;
629
630 __u32 vce_harvest_config;
631};
632
633struct drm_amdgpu_info_hw_ip {
634
635 __u32 hw_ip_version_major;
636 __u32 hw_ip_version_minor;
637
638 __u64 capabilities_flags;
639
640 __u32 ib_start_alignment;
641
642 __u32 ib_size_alignment;
643
644 __u32 available_rings;
645 __u32 _pad;
646};
647
648
649
650
651#define AMDGPU_FAMILY_UNKNOWN 0
652#define AMDGPU_FAMILY_SI 110
653#define AMDGPU_FAMILY_CI 120
654#define AMDGPU_FAMILY_KV 125
655#define AMDGPU_FAMILY_VI 130
656#define AMDGPU_FAMILY_CZ 135
657
658#if defined(__cplusplus)
659}
660#endif
661
662#endif
663