LXR linux/sound/arm/pxa2xx-ac97-lib.c

   1/*
   2 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
   3 * which contain:
   4 *
   5 * Author:      Nicolas Pitre
   6 * Created:     Dec 02, 2004
   7 * Copyright:   MontaVista Software Inc.
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License version 2 as
  11 * published by the Free Software Foundation.
  12 */
  13
  14#include <linux/kernel.h>
  15#include <linux/platform_device.h>
  16#include <linux/interrupt.h>
  17#include <linux/clk.h>
  18#include <linux/delay.h>
  19#include <linux/module.h>
  20#include <linux/io.h>
  21#include <linux/gpio.h>
  22
  23#include <sound/ac97_codec.h>
  24#include <sound/pxa2xx-lib.h>
  25
  26#include <mach/irqs.h>
  27#include <mach/regs-ac97.h>
  28#include <mach/audio.h>
  29
  30static DEFINE_MUTEX(car_mutex);
  31static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
  32static volatile long gsr_bits;
  33static struct clk *ac97_clk;
  34static struct clk *ac97conf_clk;
  35static int reset_gpio;
  36
  37extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
  38
  39/*
  40 * Beware PXA27x bugs:
  41 *
  42 *   o Slot 12 read from modem space will hang controller.
  43 *   o CDONE, SDONE interrupt fails after any slot 12 IO.
  44 *
  45 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
  46 * 1 jiffy timeout if interrupt never comes).
  47 */
  48
  49unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  50{
  51        unsigned short val = -1;
  52        volatile u32 *reg_addr;
  53
  54        mutex_lock(&car_mutex);
  55
  56        /* set up primary or secondary codec space */
  57        if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
  58                reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
  59        else
  60                reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
  61        reg_addr += (reg >> 1);
  62
  63        /* start read access across the ac97 link */
  64        GSR = GSR_CDONE | GSR_SDONE;
  65        gsr_bits = 0;
  66        val = *reg_addr;
  67        if (reg == AC97_GPIO_STATUS)
  68                goto out;
  69        if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
  70            !((GSR | gsr_bits) & GSR_SDONE)) {
  71                printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
  72                                __func__, reg, GSR | gsr_bits);
  73                val = -1;
  74                goto out;
  75        }
  76
  77        /* valid data now */
  78        GSR = GSR_CDONE | GSR_SDONE;
  79        gsr_bits = 0;
  80        val = *reg_addr;
  81        /* but we've just started another cycle... */
  82        wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
  83
  84out:    mutex_unlock(&car_mutex);
  85        return val;
  86}
  87EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
  88
  89void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  90                        unsigned short val)
  91{
  92        volatile u32 *reg_addr;
  93
  94        mutex_lock(&car_mutex);
  95
  96        /* set up primary or secondary codec space */
  97        if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
  98                reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
  99        else
 100                reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
 101        reg_addr += (reg >> 1);
 102
 103        GSR = GSR_CDONE | GSR_SDONE;
 104        gsr_bits = 0;
 105        *reg_addr = val;
 106        if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
 107            !((GSR | gsr_bits) & GSR_CDONE))
 108                printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
 109                                __func__, reg, GSR | gsr_bits);
 110
 111        mutex_unlock(&car_mutex);
 112}
 113EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
 114
 115#ifdef CONFIG_PXA25x
 116static inline void pxa_ac97_warm_pxa25x(void)
 117{
 118        gsr_bits = 0;
 119
 120        GCR |= GCR_WARM_RST;
 121}
 122
 123static inline void pxa_ac97_cold_pxa25x(void)
 124{
 125        GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
 126        GCR &= ~GCR_COLD_RST;  /* then assert nCRST */
 127
 128        gsr_bits = 0;
 129
 130        GCR = GCR_COLD_RST;
 131}
 132#endif
 133
 134#ifdef CONFIG_PXA27x
 135static inline void pxa_ac97_warm_pxa27x(void)
 136{
 137        gsr_bits = 0;
 138
 139        /* warm reset broken on Bulverde, so manually keep AC97 reset high */
 140        pxa27x_configure_ac97reset(reset_gpio, true);
 141        udelay(10);
 142        GCR |= GCR_WARM_RST;
 143        pxa27x_configure_ac97reset(reset_gpio, false);
 144        udelay(500);
 145}
 146
 147static inline void pxa_ac97_cold_pxa27x(void)
 148{
 149        GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
 150        GCR &= ~GCR_COLD_RST;  /* then assert nCRST */
 151
 152        gsr_bits = 0;
 153
 154        /* PXA27x Developers Manual section 13.5.2.2.1 */
 155        clk_prepare_enable(ac97conf_clk);
 156        udelay(5);
 157        clk_disable_unprepare(ac97conf_clk);
 158        GCR = GCR_COLD_RST | GCR_WARM_RST;
 159}
 160#endif
 161
 162#ifdef CONFIG_PXA3xx
 163static inline void pxa_ac97_warm_pxa3xx(void)
 164{
 165        gsr_bits = 0;
 166
 167        /* Can't use interrupts */
 168        GCR |= GCR_WARM_RST;
 169}
 170
 171static inline void pxa_ac97_cold_pxa3xx(void)
 172{
 173        /* Hold CLKBPB for 100us */
 174        GCR = 0;
 175        GCR = GCR_CLKBPB;
 176        udelay(100);
 177        GCR = 0;
 178
 179        GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
 180        GCR &= ~GCR_COLD_RST;  /* then assert nCRST */
 181
 182        gsr_bits = 0;
 183
 184        /* Can't use interrupts on PXA3xx */
 185        GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
 186
 187        GCR = GCR_WARM_RST | GCR_COLD_RST;
 188}
 189#endif
 190
 191bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
 192{
 193        unsigned long gsr;
 194        unsigned int timeout = 100;
 195
 196#ifdef CONFIG_PXA25x
 197        if (cpu_is_pxa25x())
 198                pxa_ac97_warm_pxa25x();
 199        else
 200#endif
 201#ifdef CONFIG_PXA27x
 202        if (cpu_is_pxa27x())
 203                pxa_ac97_warm_pxa27x();
 204        else
 205#endif
 206#ifdef CONFIG_PXA3xx
 207        if (cpu_is_pxa3xx())
 208                pxa_ac97_warm_pxa3xx();
 209        else
 210#endif
 211                snd_BUG();
 212
 213        while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
 214                mdelay(1);
 215
 216        gsr = GSR | gsr_bits;
 217        if (!(gsr & (GSR_PCR | GSR_SCR))) {
 218                printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
 219                                 __func__, gsr);
 220
 221                return false;
 222        }
 223
 224        return true;
 225}
 226EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
 227
 228bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
 229{
 230        unsigned long gsr;
 231        unsigned int timeout = 1000;
 232
 233#ifdef CONFIG_PXA25x
 234        if (cpu_is_pxa25x())
 235                pxa_ac97_cold_pxa25x();
 236        else
 237#endif
 238#ifdef CONFIG_PXA27x
 239        if (cpu_is_pxa27x())
 240                pxa_ac97_cold_pxa27x();
 241        else
 242#endif
 243#ifdef CONFIG_PXA3xx
 244        if (cpu_is_pxa3xx())
 245                pxa_ac97_cold_pxa3xx();
 246        else
 247#endif
 248                snd_BUG();
 249
 250        while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
 251                mdelay(1);
 252
 253        gsr = GSR | gsr_bits;
 254        if (!(gsr & (GSR_PCR | GSR_SCR))) {
 255                printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
 256                                 __func__, gsr);
 257
 258                return false;
 259        }
 260
 261        return true;
 262}
 263EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
 264
 265
 266void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
 267{
 268        GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
 269        GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
 270}
 271EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
 272
 273static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
 274{
 275        long status;
 276
 277        status = GSR;
 278        if (status) {
 279                GSR = status;
 280                gsr_bits |= status;
 281                wake_up(&gsr_wq);
 282
 283                /* Although we don't use those we still need to clear them
 284                   since they tend to spuriously trigger when MMC is used
 285                   (hardware bug? go figure)... */
 286                if (cpu_is_pxa27x()) {
 287                        MISR = MISR_EOC;
 288                        PISR = PISR_EOC;
 289                        MCSR = MCSR_EOC;
 290                }
 291
 292                return IRQ_HANDLED;
 293        }
 294
 295        return IRQ_NONE;
 296}
 297
 298#ifdef CONFIG_PM
 299int pxa2xx_ac97_hw_suspend(void)
 300{
 301        GCR |= GCR_ACLINK_OFF;
 302        clk_disable_unprepare(ac97_clk);
 303        return 0;
 304}
 305EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
 306
 307int pxa2xx_ac97_hw_resume(void)
 308{
 309        clk_prepare_enable(ac97_clk);
 310        return 0;
 311}
 312EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
 313#endif
 314
 315int pxa2xx_ac97_hw_probe(struct platform_device *dev)
 316{
 317        int ret;
 318        pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
 319
 320        if (pdata) {
 321                switch (pdata->reset_gpio) {
 322                case 95:
 323                case 113:
 324                        reset_gpio = pdata->reset_gpio;
 325                        break;
 326                case 0:
 327                        reset_gpio = 113;
 328                        break;
 329                case -1:
 330                        break;
 331                default:
 332                        dev_err(&dev->dev, "Invalid reset GPIO %d\n",
 333                                pdata->reset_gpio);
 334                }
 335        } else {
 336                if (cpu_is_pxa27x())
 337                        reset_gpio = 113;
 338        }
 339
 340        if (cpu_is_pxa27x()) {
 341                /*
 342                 * This gpio is needed for a work-around to a bug in the ac97
 343                 * controller during warm reset.  The direction and level is set
 344                 * here so that it is an output driven high when switching from
 345                 * AC97_nRESET alt function to generic gpio.
 346                 */
 347                ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
 348                                       "pxa27x ac97 reset");
 349                if (ret < 0) {
 350                        pr_err("%s: gpio_request_one() failed: %d\n",
 351                               __func__, ret);
 352                        goto err_conf;
 353                }
 354                pxa27x_configure_ac97reset(reset_gpio, false);
 355
 356                ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
 357                if (IS_ERR(ac97conf_clk)) {
 358                        ret = PTR_ERR(ac97conf_clk);
 359                        ac97conf_clk = NULL;
 360                        goto err_conf;
 361                }
 362        }
 363
 364        ac97_clk = clk_get(&dev->dev, "AC97CLK");
 365        if (IS_ERR(ac97_clk)) {
 366                ret = PTR_ERR(ac97_clk);
 367                ac97_clk = NULL;
 368                goto err_clk;
 369        }
 370
 371        ret = clk_prepare_enable(ac97_clk);
 372        if (ret)
 373                goto err_clk2;
 374
 375        ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
 376        if (ret < 0)
 377                goto err_irq;
 378
 379        return 0;
 380
 381err_irq:
 382        GCR |= GCR_ACLINK_OFF;
 383err_clk2:
 384        clk_put(ac97_clk);
 385        ac97_clk = NULL;
 386err_clk:
 387        if (ac97conf_clk) {
 388                clk_put(ac97conf_clk);
 389                ac97conf_clk = NULL;
 390        }
 391err_conf:
 392        return ret;
 393}
 394EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
 395
 396void pxa2xx_ac97_hw_remove(struct platform_device *dev)
 397{
 398        if (cpu_is_pxa27x())
 399                gpio_free(reset_gpio);
 400        GCR |= GCR_ACLINK_OFF;
 401        free_irq(IRQ_AC97, NULL);
 402        if (ac97conf_clk) {
 403                clk_put(ac97conf_clk);
 404                ac97conf_clk = NULL;
 405        }
 406        clk_disable_unprepare(ac97_clk);
 407        clk_put(ac97_clk);
 408        ac97_clk = NULL;
 409}
 410EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
 411
 412MODULE_AUTHOR("Nicolas Pitre");
 413MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
 414MODULE_LICENSE("GPL");
 415
 416