LXR linux/virt/kvm/arm/vgic/vgic-mmio.h

   1/*
   2 * Copyright (C) 2015, 2016 ARM Ltd.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 as
   6 * published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 *
  13 * You should have received a copy of the GNU General Public License
  14 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15 */
  16#ifndef __KVM_ARM_VGIC_MMIO_H__
  17#define __KVM_ARM_VGIC_MMIO_H__
  18
  19struct vgic_register_region {
  20        unsigned int reg_offset;
  21        unsigned int len;
  22        unsigned int bits_per_irq;
  23        unsigned int access_flags;
  24        union {
  25                unsigned long (*read)(struct kvm_vcpu *vcpu, gpa_t addr,
  26                                      unsigned int len);
  27                unsigned long (*its_read)(struct kvm *kvm, struct vgic_its *its,
  28                                          gpa_t addr, unsigned int len);
  29        };
  30        union {
  31                void (*write)(struct kvm_vcpu *vcpu, gpa_t addr,
  32                              unsigned int len, unsigned long val);
  33                void (*its_write)(struct kvm *kvm, struct vgic_its *its,
  34                                  gpa_t addr, unsigned int len,
  35                                  unsigned long val);
  36        };
  37};
  38
  39extern struct kvm_io_device_ops kvm_io_gic_ops;
  40
  41#define VGIC_ACCESS_8bit        1
  42#define VGIC_ACCESS_32bit       2
  43#define VGIC_ACCESS_64bit       4
  44
  45/*
  46 * Generate a mask that covers the number of bytes required to address
  47 * up to 1024 interrupts, each represented by <bits> bits. This assumes
  48 * that <bits> is a power of two.
  49 */
  50#define VGIC_ADDR_IRQ_MASK(bits) (((bits) * 1024 / 8) - 1)
  51
  52/*
  53 * (addr & mask) gives us the _byte_ offset for the INT ID.
  54 * We multiply this by 8 the get the _bit_ offset, then divide this by
  55 * the number of bits to learn the actual INT ID.
  56 * But instead of a division (which requires a "long long div" implementation),
  57 * we shift by the binary logarithm of <bits>.
  58 * This assumes that <bits> is a power of two.
  59 */
  60#define VGIC_ADDR_TO_INTID(addr, bits)  (((addr) & VGIC_ADDR_IRQ_MASK(bits)) * \
  61                                        8 >> ilog2(bits))
  62
  63/*
  64 * Some VGIC registers store per-IRQ information, with a different number
  65 * of bits per IRQ. For those registers this macro is used.
  66 * The _WITH_LENGTH version instantiates registers with a fixed length
  67 * and is mutually exclusive with the _PER_IRQ version.
  68 */
  69#define REGISTER_DESC_WITH_BITS_PER_IRQ(off, rd, wr, bpi, acc)          \
  70        {                                                               \
  71                .reg_offset = off,                                      \
  72                .bits_per_irq = bpi,                                    \
  73                .len = bpi * 1024 / 8,                                  \
  74                .access_flags = acc,                                    \
  75                .read = rd,                                             \
  76                .write = wr,                                            \
  77        }
  78
  79#define REGISTER_DESC_WITH_LENGTH(off, rd, wr, length, acc)             \
  80        {                                                               \
  81                .reg_offset = off,                                      \
  82                .bits_per_irq = 0,                                      \
  83                .len = length,                                          \
  84                .access_flags = acc,                                    \
  85                .read = rd,                                             \
  86                .write = wr,                                            \
  87        }
  88
  89int kvm_vgic_register_mmio_region(struct kvm *kvm, struct kvm_vcpu *vcpu,
  90                                  struct vgic_register_region *reg_desc,
  91                                  struct vgic_io_device *region,
  92                                  int nr_irqs, bool offset_private);
  93
  94unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len);
  95
  96void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
  97                                unsigned long data);
  98
  99unsigned long extract_bytes(u64 data, unsigned int offset,
 100                            unsigned int num);
 101
 102u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
 103                     unsigned long val);
 104
 105unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
 106                                 gpa_t addr, unsigned int len);
 107
 108unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
 109                                 gpa_t addr, unsigned int len);
 110
 111void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
 112                        unsigned int len, unsigned long val);
 113
 114unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
 115                                    gpa_t addr, unsigned int len);
 116
 117void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
 118                             gpa_t addr, unsigned int len,
 119                             unsigned long val);
 120
 121void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
 122                             gpa_t addr, unsigned int len,
 123                             unsigned long val);
 124
 125unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
 126                                     gpa_t addr, unsigned int len);
 127
 128void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
 129                              gpa_t addr, unsigned int len,
 130                              unsigned long val);
 131
 132void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
 133                              gpa_t addr, unsigned int len,
 134                              unsigned long val);
 135
 136unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
 137                                    gpa_t addr, unsigned int len);
 138
 139void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
 140                             gpa_t addr, unsigned int len,
 141                             unsigned long val);
 142
 143void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
 144                             gpa_t addr, unsigned int len,
 145                             unsigned long val);
 146
 147unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
 148                                      gpa_t addr, unsigned int len);
 149
 150void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
 151                              gpa_t addr, unsigned int len,
 152                              unsigned long val);
 153
 154unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
 155                                    gpa_t addr, unsigned int len);
 156
 157void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
 158                            gpa_t addr, unsigned int len,
 159                            unsigned long val);
 160
 161unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev);
 162
 163unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);
 164
 165u64 vgic_sanitise_outer_cacheability(u64 reg);
 166u64 vgic_sanitise_inner_cacheability(u64 reg);
 167u64 vgic_sanitise_shareability(u64 reg);
 168u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
 169                        u64 (*sanitise_fn)(u64));
 170
 171#endif
 172