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12#include <linux/clk.h>
13#include <linux/clockchips.h>
14#include <linux/clocksource.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/io.h>
20#include <linux/kernel.h>
21#include <linux/of_irq.h>
22#include <linux/of_address.h>
23#include <linux/time.h>
24#include <linux/irq.h>
25#include <asm/mach/time.h>
26#include "generic.h"
27
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30
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32
33
34
35#define CLKEVT 0
36#define CLKSRC 1
37
38
39#define CR(x) ((x) * 0x80 + 0x80)
40#define IR(x) ((x) * 0x80 + 0x84)
41#define LOAD(x) ((x) * 0x80 + 0x88)
42#define COUNT(x) ((x) * 0x80 + 0x8C)
43
44
45#define CTRL_INT_ENABLE 0x0100
46#define CTRL_ENABLE 0x0020
47#define CTRL_ONE_SHOT 0x0010
48
49#define CTRL_PRESCALER1 0x0
50#define CTRL_PRESCALER2 0x1
51#define CTRL_PRESCALER4 0x2
52#define CTRL_PRESCALER8 0x3
53#define CTRL_PRESCALER16 0x4
54#define CTRL_PRESCALER32 0x5
55#define CTRL_PRESCALER64 0x6
56#define CTRL_PRESCALER128 0x7
57#define CTRL_PRESCALER256 0x8
58
59#define INT_STATUS 0x1
60
61
62
63
64#define SPEAR_MIN_RANGE 4
65
66static __iomem void *gpt_base;
67static struct clk *gpt_clk;
68
69static int clockevent_next_event(unsigned long evt,
70 struct clock_event_device *clk_event_dev);
71
72static void __init spear_clocksource_init(void)
73{
74 u32 tick_rate;
75 u16 val;
76
77
78 writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
79
80
81 tick_rate = clk_get_rate(gpt_clk);
82 tick_rate >>= CTRL_PRESCALER256;
83
84 writew(0xFFFF, gpt_base + LOAD(CLKSRC));
85
86 val = readw(gpt_base + CR(CLKSRC));
87 val &= ~CTRL_ONE_SHOT;
88 val |= CTRL_ENABLE ;
89 writew(val, gpt_base + CR(CLKSRC));
90
91
92 clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,
93 200, 16, clocksource_mmio_readw_up);
94}
95
96static inline void timer_shutdown(struct clock_event_device *evt)
97{
98 u16 val = readw(gpt_base + CR(CLKEVT));
99
100
101 val &= ~CTRL_ENABLE;
102 writew(val, gpt_base + CR(CLKEVT));
103}
104
105static int spear_shutdown(struct clock_event_device *evt)
106{
107 timer_shutdown(evt);
108
109 return 0;
110}
111
112static int spear_set_oneshot(struct clock_event_device *evt)
113{
114 u16 val;
115
116
117 timer_shutdown(evt);
118
119 val = readw(gpt_base + CR(CLKEVT));
120 val |= CTRL_ONE_SHOT;
121 writew(val, gpt_base + CR(CLKEVT));
122
123 return 0;
124}
125
126static int spear_set_periodic(struct clock_event_device *evt)
127{
128 u32 period;
129 u16 val;
130
131
132 timer_shutdown(evt);
133
134 period = clk_get_rate(gpt_clk) / HZ;
135 period >>= CTRL_PRESCALER16;
136 writew(period, gpt_base + LOAD(CLKEVT));
137
138 val = readw(gpt_base + CR(CLKEVT));
139 val &= ~CTRL_ONE_SHOT;
140 val |= CTRL_ENABLE | CTRL_INT_ENABLE;
141 writew(val, gpt_base + CR(CLKEVT));
142
143 return 0;
144}
145
146static struct clock_event_device clkevt = {
147 .name = "tmr0",
148 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
149 .set_state_shutdown = spear_shutdown,
150 .set_state_periodic = spear_set_periodic,
151 .set_state_oneshot = spear_set_oneshot,
152 .tick_resume = spear_shutdown,
153 .set_next_event = clockevent_next_event,
154 .shift = 0,
155};
156
157static int clockevent_next_event(unsigned long cycles,
158 struct clock_event_device *clk_event_dev)
159{
160 u16 val = readw(gpt_base + CR(CLKEVT));
161
162 if (val & CTRL_ENABLE)
163 writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT));
164
165 writew(cycles, gpt_base + LOAD(CLKEVT));
166
167 val |= CTRL_ENABLE | CTRL_INT_ENABLE;
168 writew(val, gpt_base + CR(CLKEVT));
169
170 return 0;
171}
172
173static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
174{
175 struct clock_event_device *evt = &clkevt;
176
177 writew(INT_STATUS, gpt_base + IR(CLKEVT));
178
179 evt->event_handler(evt);
180
181 return IRQ_HANDLED;
182}
183
184static struct irqaction spear_timer_irq = {
185 .name = "timer",
186 .flags = IRQF_TIMER,
187 .handler = spear_timer_interrupt
188};
189
190static void __init spear_clockevent_init(int irq)
191{
192 u32 tick_rate;
193
194
195 writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
196
197 tick_rate = clk_get_rate(gpt_clk);
198 tick_rate >>= CTRL_PRESCALER16;
199
200 clkevt.cpumask = cpumask_of(0);
201
202 clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0);
203
204 setup_irq(irq, &spear_timer_irq);
205}
206
207static const struct of_device_id const timer_of_match[] __initconst = {
208 { .compatible = "st,spear-timer", },
209 { },
210};
211
212void __init spear_setup_of_timer(void)
213{
214 struct device_node *np;
215 int irq, ret;
216
217 np = of_find_matching_node(NULL, timer_of_match);
218 if (!np) {
219 pr_err("%s: No timer passed via DT\n", __func__);
220 return;
221 }
222
223 irq = irq_of_parse_and_map(np, 0);
224 if (!irq) {
225 pr_err("%s: No irq passed for timer via DT\n", __func__);
226 return;
227 }
228
229 gpt_base = of_iomap(np, 0);
230 if (!gpt_base) {
231 pr_err("%s: of iomap failed\n", __func__);
232 return;
233 }
234
235 gpt_clk = clk_get_sys("gpt0", NULL);
236 if (!gpt_clk) {
237 pr_err("%s:couldn't get clk for gpt\n", __func__);
238 goto err_iomap;
239 }
240
241 ret = clk_prepare_enable(gpt_clk);
242 if (ret < 0) {
243 pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
244 goto err_prepare_enable_clk;
245 }
246
247 spear_clockevent_init(irq);
248 spear_clocksource_init();
249
250 return;
251
252err_prepare_enable_clk:
253 clk_put(gpt_clk);
254err_iomap:
255 iounmap(gpt_base);
256}
257
