1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_FPA_DEFS_H__ 29#define __CVMX_FPA_DEFS_H__ 30 31#define CVMX_FPA_ADDR_RANGE_ERROR (CVMX_ADD_IO_SEG(0x0001180028000458ull)) 32#define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull)) 33#define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull)) 34#define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull)) 35#define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull)) 36#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1) 37#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2) 38#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3) 39#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4) 40#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5) 41#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6) 42#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7) 43#define CVMX_FPA_FPF8_MARKS (CVMX_ADD_IO_SEG(0x0001180028000240ull)) 44#define CVMX_FPA_FPF8_SIZE (CVMX_ADD_IO_SEG(0x0001180028000248ull)) 45#define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1) 46#define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1) 47#define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull)) 48#define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull)) 49#define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull)) 50#define CVMX_FPA_POOLX_END_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8) 51#define CVMX_FPA_POOLX_START_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8) 52#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8) 53#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0) 54#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1) 55#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2) 56#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3) 57#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4) 58#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5) 59#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6) 60#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7) 61#define CVMX_FPA_QUE8_PAGE_INDEX (CVMX_ADD_IO_SEG(0x0001180028000250ull)) 62#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8) 63#define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8) 64#define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull)) 65#define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull)) 66#define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull)) 67#define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull)) 68#define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull)) 69#define CVMX_FPA_CLK_COUNT (CVMX_ADD_IO_SEG(0x00012800000000F0ull)) 70 71union cvmx_fpa_addr_range_error { 72 uint64_t u64; 73 struct cvmx_fpa_addr_range_error_s { 74#ifdef __BIG_ENDIAN_BITFIELD 75 uint64_t reserved_38_63:26; 76 uint64_t pool:5; 77 uint64_t addr:33; 78#else 79 uint64_t addr:33; 80 uint64_t pool:5; 81 uint64_t reserved_38_63:26; 82#endif 83 } s; 84 struct cvmx_fpa_addr_range_error_s cn61xx; 85 struct cvmx_fpa_addr_range_error_s cn66xx; 86 struct cvmx_fpa_addr_range_error_s cn68xx; 87 struct cvmx_fpa_addr_range_error_s cn68xxp1; 88 struct cvmx_fpa_addr_range_error_s cnf71xx; 89}; 90 91union cvmx_fpa_bist_status { 92 uint64_t u64; 93 struct cvmx_fpa_bist_status_s { 94#ifdef __BIG_ENDIAN_BITFIELD 95 uint64_t reserved_5_63:59; 96 uint64_t frd:1; 97 uint64_t fpf0:1; 98 uint64_t fpf1:1; 99 uint64_t ffr:1; 100 uint64_t fdr:1; 101#else 102 uint64_t fdr:1; 103 uint64_t ffr:1; 104 uint64_t fpf1:1; 105 uint64_t fpf0:1; 106 uint64_t frd:1; 107 uint64_t reserved_5_63:59; 108#endif 109 } s; 110 struct cvmx_fpa_bist_status_s cn30xx; 111 struct cvmx_fpa_bist_status_s cn31xx; 112 struct cvmx_fpa_bist_status_s cn38xx; 113 struct cvmx_fpa_bist_status_s cn38xxp2; 114 struct cvmx_fpa_bist_status_s cn50xx; 115 struct cvmx_fpa_bist_status_s cn52xx; 116 struct cvmx_fpa_bist_status_s cn52xxp1; 117 struct cvmx_fpa_bist_status_s cn56xx; 118 struct cvmx_fpa_bist_status_s cn56xxp1; 119 struct cvmx_fpa_bist_status_s cn58xx; 120 struct cvmx_fpa_bist_status_s cn58xxp1; 121 struct cvmx_fpa_bist_status_s cn61xx; 122 struct cvmx_fpa_bist_status_s cn63xx; 123 struct cvmx_fpa_bist_status_s cn63xxp1; 124 struct cvmx_fpa_bist_status_s cn66xx; 125 struct cvmx_fpa_bist_status_s cn68xx; 126 struct cvmx_fpa_bist_status_s cn68xxp1; 127 struct cvmx_fpa_bist_status_s cnf71xx; 128}; 129 130union cvmx_fpa_ctl_status { 131 uint64_t u64; 132 struct cvmx_fpa_ctl_status_s { 133#ifdef __BIG_ENDIAN_BITFIELD 134 uint64_t reserved_21_63:43; 135 uint64_t free_en:1; 136 uint64_t ret_off:1; 137 uint64_t req_off:1; 138 uint64_t reset:1; 139 uint64_t use_ldt:1; 140 uint64_t use_stt:1; 141 uint64_t enb:1; 142 uint64_t mem1_err:7; 143 uint64_t mem0_err:7; 144#else 145 uint64_t mem0_err:7; 146 uint64_t mem1_err:7; 147 uint64_t enb:1; 148 uint64_t use_stt:1; 149 uint64_t use_ldt:1; 150 uint64_t reset:1; 151 uint64_t req_off:1; 152 uint64_t ret_off:1; 153 uint64_t free_en:1; 154 uint64_t reserved_21_63:43; 155#endif 156 } s; 157 struct cvmx_fpa_ctl_status_cn30xx { 158#ifdef __BIG_ENDIAN_BITFIELD 159 uint64_t reserved_18_63:46; 160 uint64_t reset:1; 161 uint64_t use_ldt:1; 162 uint64_t use_stt:1; 163 uint64_t enb:1; 164 uint64_t mem1_err:7; 165 uint64_t mem0_err:7; 166#else 167 uint64_t mem0_err:7; 168 uint64_t mem1_err:7; 169 uint64_t enb:1; 170 uint64_t use_stt:1; 171 uint64_t use_ldt:1; 172 uint64_t reset:1; 173 uint64_t reserved_18_63:46; 174#endif 175 } cn30xx; 176 struct cvmx_fpa_ctl_status_cn30xx cn31xx; 177 struct cvmx_fpa_ctl_status_cn30xx cn38xx; 178 struct cvmx_fpa_ctl_status_cn30xx cn38xxp2; 179 struct cvmx_fpa_ctl_status_cn30xx cn50xx; 180 struct cvmx_fpa_ctl_status_cn30xx cn52xx; 181 struct cvmx_fpa_ctl_status_cn30xx cn52xxp1; 182 struct cvmx_fpa_ctl_status_cn30xx cn56xx; 183 struct cvmx_fpa_ctl_status_cn30xx cn56xxp1; 184 struct cvmx_fpa_ctl_status_cn30xx cn58xx; 185 struct cvmx_fpa_ctl_status_cn30xx cn58xxp1; 186 struct cvmx_fpa_ctl_status_s cn61xx; 187 struct cvmx_fpa_ctl_status_s cn63xx; 188 struct cvmx_fpa_ctl_status_cn30xx cn63xxp1; 189 struct cvmx_fpa_ctl_status_s cn66xx; 190 struct cvmx_fpa_ctl_status_s cn68xx; 191 struct cvmx_fpa_ctl_status_s cn68xxp1; 192 struct cvmx_fpa_ctl_status_s cnf71xx; 193}; 194 195union cvmx_fpa_fpfx_marks { 196 uint64_t u64; 197 struct cvmx_fpa_fpfx_marks_s { 198#ifdef __BIG_ENDIAN_BITFIELD 199 uint64_t reserved_22_63:42; 200 uint64_t fpf_wr:11; 201 uint64_t fpf_rd:11; 202#else 203 uint64_t fpf_rd:11; 204 uint64_t fpf_wr:11; 205 uint64_t reserved_22_63:42; 206#endif 207 } s; 208 struct cvmx_fpa_fpfx_marks_s cn38xx; 209 struct cvmx_fpa_fpfx_marks_s cn38xxp2; 210 struct cvmx_fpa_fpfx_marks_s cn56xx; 211 struct cvmx_fpa_fpfx_marks_s cn56xxp1; 212 struct cvmx_fpa_fpfx_marks_s cn58xx; 213 struct cvmx_fpa_fpfx_marks_s cn58xxp1; 214 struct cvmx_fpa_fpfx_marks_s cn61xx; 215 struct cvmx_fpa_fpfx_marks_s cn63xx; 216 struct cvmx_fpa_fpfx_marks_s cn63xxp1; 217 struct cvmx_fpa_fpfx_marks_s cn66xx; 218 struct cvmx_fpa_fpfx_marks_s cn68xx; 219 struct cvmx_fpa_fpfx_marks_s cn68xxp1; 220 struct cvmx_fpa_fpfx_marks_s cnf71xx; 221}; 222 223union cvmx_fpa_fpfx_size { 224 uint64_t u64; 225 struct cvmx_fpa_fpfx_size_s { 226#ifdef __BIG_ENDIAN_BITFIELD 227 uint64_t reserved_11_63:53; 228 uint64_t fpf_siz:11; 229#else 230 uint64_t fpf_siz:11; 231 uint64_t reserved_11_63:53; 232#endif 233 } s; 234 struct cvmx_fpa_fpfx_size_s cn38xx; 235 struct cvmx_fpa_fpfx_size_s cn38xxp2; 236 struct cvmx_fpa_fpfx_size_s cn56xx; 237 struct cvmx_fpa_fpfx_size_s cn56xxp1; 238 struct cvmx_fpa_fpfx_size_s cn58xx; 239 struct cvmx_fpa_fpfx_size_s cn58xxp1; 240 struct cvmx_fpa_fpfx_size_s cn61xx; 241 struct cvmx_fpa_fpfx_size_s cn63xx; 242 struct cvmx_fpa_fpfx_size_s cn63xxp1; 243 struct cvmx_fpa_fpfx_size_s cn66xx; 244 struct cvmx_fpa_fpfx_size_s cn68xx; 245 struct cvmx_fpa_fpfx_size_s cn68xxp1; 246 struct cvmx_fpa_fpfx_size_s cnf71xx; 247}; 248 249union cvmx_fpa_fpf0_marks { 250 uint64_t u64; 251 struct cvmx_fpa_fpf0_marks_s { 252#ifdef __BIG_ENDIAN_BITFIELD 253 uint64_t reserved_24_63:40; 254 uint64_t fpf_wr:12; 255 uint64_t fpf_rd:12; 256#else 257 uint64_t fpf_rd:12; 258 uint64_t fpf_wr:12; 259 uint64_t reserved_24_63:40; 260#endif 261 } s; 262 struct cvmx_fpa_fpf0_marks_s cn38xx; 263 struct cvmx_fpa_fpf0_marks_s cn38xxp2; 264 struct cvmx_fpa_fpf0_marks_s cn56xx; 265 struct cvmx_fpa_fpf0_marks_s cn56xxp1; 266 struct cvmx_fpa_fpf0_marks_s cn58xx; 267 struct cvmx_fpa_fpf0_marks_s cn58xxp1; 268 struct cvmx_fpa_fpf0_marks_s cn61xx; 269 struct cvmx_fpa_fpf0_marks_s cn63xx; 270 struct cvmx_fpa_fpf0_marks_s cn63xxp1; 271 struct cvmx_fpa_fpf0_marks_s cn66xx; 272 struct cvmx_fpa_fpf0_marks_s cn68xx; 273 struct cvmx_fpa_fpf0_marks_s cn68xxp1; 274 struct cvmx_fpa_fpf0_marks_s cnf71xx; 275}; 276 277union cvmx_fpa_fpf0_size { 278 uint64_t u64; 279 struct cvmx_fpa_fpf0_size_s { 280#ifdef __BIG_ENDIAN_BITFIELD 281 uint64_t reserved_12_63:52; 282 uint64_t fpf_siz:12; 283#else 284 uint64_t fpf_siz:12; 285 uint64_t reserved_12_63:52; 286#endif 287 } s; 288 struct cvmx_fpa_fpf0_size_s cn38xx; 289 struct cvmx_fpa_fpf0_size_s cn38xxp2; 290 struct cvmx_fpa_fpf0_size_s cn56xx; 291 struct cvmx_fpa_fpf0_size_s cn56xxp1; 292 struct cvmx_fpa_fpf0_size_s cn58xx; 293 struct cvmx_fpa_fpf0_size_s cn58xxp1; 294 struct cvmx_fpa_fpf0_size_s cn61xx; 295 struct cvmx_fpa_fpf0_size_s cn63xx; 296 struct cvmx_fpa_fpf0_size_s cn63xxp1; 297 struct cvmx_fpa_fpf0_size_s cn66xx; 298 struct cvmx_fpa_fpf0_size_s cn68xx; 299 struct cvmx_fpa_fpf0_size_s cn68xxp1; 300 struct cvmx_fpa_fpf0_size_s cnf71xx; 301}; 302 303union cvmx_fpa_fpf8_marks { 304 uint64_t u64; 305 struct cvmx_fpa_fpf8_marks_s { 306#ifdef __BIG_ENDIAN_BITFIELD 307 uint64_t reserved_22_63:42; 308 uint64_t fpf_wr:11; 309 uint64_t fpf_rd:11; 310#else 311 uint64_t fpf_rd:11; 312 uint64_t fpf_wr:11; 313 uint64_t reserved_22_63:42; 314#endif 315 } s; 316 struct cvmx_fpa_fpf8_marks_s cn68xx; 317 struct cvmx_fpa_fpf8_marks_s cn68xxp1; 318}; 319 320union cvmx_fpa_fpf8_size { 321 uint64_t u64; 322 struct cvmx_fpa_fpf8_size_s { 323#ifdef __BIG_ENDIAN_BITFIELD 324 uint64_t reserved_12_63:52; 325 uint64_t fpf_siz:12; 326#else 327 uint64_t fpf_siz:12; 328 uint64_t reserved_12_63:52; 329#endif 330 } s; 331 struct cvmx_fpa_fpf8_size_s cn68xx; 332 struct cvmx_fpa_fpf8_size_s cn68xxp1; 333}; 334 335union cvmx_fpa_int_enb { 336 uint64_t u64; 337 struct cvmx_fpa_int_enb_s { 338#ifdef __BIG_ENDIAN_BITFIELD 339 uint64_t reserved_50_63:14; 340 uint64_t paddr_e:1; 341 uint64_t reserved_44_48:5; 342 uint64_t free7:1; 343 uint64_t free6:1; 344 uint64_t free5:1; 345 uint64_t free4:1; 346 uint64_t free3:1; 347 uint64_t free2:1; 348 uint64_t free1:1; 349 uint64_t free0:1; 350 uint64_t pool7th:1; 351 uint64_t pool6th:1; 352 uint64_t pool5th:1; 353 uint64_t pool4th:1; 354 uint64_t pool3th:1; 355 uint64_t pool2th:1; 356 uint64_t pool1th:1; 357 uint64_t pool0th:1; 358 uint64_t q7_perr:1; 359 uint64_t q7_coff:1; 360 uint64_t q7_und:1; 361 uint64_t q6_perr:1; 362 uint64_t q6_coff:1; 363 uint64_t q6_und:1; 364 uint64_t q5_perr:1; 365 uint64_t q5_coff:1; 366 uint64_t q5_und:1; 367 uint64_t q4_perr:1; 368 uint64_t q4_coff:1; 369 uint64_t q4_und:1; 370 uint64_t q3_perr:1; 371 uint64_t q3_coff:1; 372 uint64_t q3_und:1; 373 uint64_t q2_perr:1; 374 uint64_t q2_coff:1; 375 uint64_t q2_und:1; 376 uint64_t q1_perr:1; 377 uint64_t q1_coff:1; 378 uint64_t q1_und:1; 379 uint64_t q0_perr:1; 380 uint64_t q0_coff:1; 381 uint64_t q0_und:1; 382 uint64_t fed1_dbe:1; 383 uint64_t fed1_sbe:1; 384 uint64_t fed0_dbe:1; 385 uint64_t fed0_sbe:1; 386#else 387 uint64_t fed0_sbe:1; 388 uint64_t fed0_dbe:1; 389 uint64_t fed1_sbe:1; 390 uint64_t fed1_dbe:1; 391 uint64_t q0_und:1; 392 uint64_t q0_coff:1; 393 uint64_t q0_perr:1; 394 uint64_t q1_und:1; 395 uint64_t q1_coff:1; 396 uint64_t q1_perr:1; 397 uint64_t q2_und:1; 398 uint64_t q2_coff:1; 399 uint64_t q2_perr:1; 400 uint64_t q3_und:1; 401 uint64_t q3_coff:1; 402 uint64_t q3_perr:1; 403 uint64_t q4_und:1; 404 uint64_t q4_coff:1; 405 uint64_t q4_perr:1; 406 uint64_t q5_und:1; 407 uint64_t q5_coff:1; 408 uint64_t q5_perr:1; 409 uint64_t q6_und:1; 410 uint64_t q6_coff:1; 411 uint64_t q6_perr:1; 412 uint64_t q7_und:1; 413 uint64_t q7_coff:1; 414 uint64_t q7_perr:1; 415 uint64_t pool0th:1; 416 uint64_t pool1th:1; 417 uint64_t pool2th:1; 418 uint64_t pool3th:1; 419 uint64_t pool4th:1; 420 uint64_t pool5th:1; 421 uint64_t pool6th:1; 422 uint64_t pool7th:1; 423 uint64_t free0:1; 424 uint64_t free1:1; 425 uint64_t free2:1; 426 uint64_t free3:1; 427 uint64_t free4:1; 428 uint64_t free5:1; 429 uint64_t free6:1; 430 uint64_t free7:1; 431 uint64_t reserved_44_48:5; 432 uint64_t paddr_e:1; 433 uint64_t reserved_50_63:14; 434#endif 435 } s; 436 struct cvmx_fpa_int_enb_cn30xx { 437#ifdef __BIG_ENDIAN_BITFIELD 438 uint64_t reserved_28_63:36; 439 uint64_t q7_perr:1; 440 uint64_t q7_coff:1; 441 uint64_t q7_und:1; 442 uint64_t q6_perr:1; 443 uint64_t q6_coff:1; 444 uint64_t q6_und:1; 445 uint64_t q5_perr:1; 446 uint64_t q5_coff:1; 447 uint64_t q5_und:1; 448 uint64_t q4_perr:1; 449 uint64_t q4_coff:1; 450 uint64_t q4_und:1; 451 uint64_t q3_perr:1; 452 uint64_t q3_coff:1; 453 uint64_t q3_und:1; 454 uint64_t q2_perr:1; 455 uint64_t q2_coff:1; 456 uint64_t q2_und:1; 457 uint64_t q1_perr:1; 458 uint64_t q1_coff:1; 459 uint64_t q1_und:1; 460 uint64_t q0_perr:1; 461 uint64_t q0_coff:1; 462 uint64_t q0_und:1; 463 uint64_t fed1_dbe:1; 464 uint64_t fed1_sbe:1; 465 uint64_t fed0_dbe:1; 466 uint64_t fed0_sbe:1; 467#else 468 uint64_t fed0_sbe:1; 469 uint64_t fed0_dbe:1; 470 uint64_t fed1_sbe:1; 471 uint64_t fed1_dbe:1; 472 uint64_t q0_und:1; 473 uint64_t q0_coff:1; 474 uint64_t q0_perr:1; 475 uint64_t q1_und:1; 476 uint64_t q1_coff:1; 477 uint64_t q1_perr:1; 478 uint64_t q2_und:1; 479 uint64_t q2_coff:1; 480 uint64_t q2_perr:1; 481 uint64_t q3_und:1; 482 uint64_t q3_coff:1; 483 uint64_t q3_perr:1; 484 uint64_t q4_und:1; 485 uint64_t q4_coff:1; 486 uint64_t q4_perr:1; 487 uint64_t q5_und:1; 488 uint64_t q5_coff:1; 489 uint64_t q5_perr:1; 490 uint64_t q6_und:1; 491 uint64_t q6_coff:1; 492 uint64_t q6_perr:1; 493 uint64_t q7_und:1; 494 uint64_t q7_coff:1; 495 uint64_t q7_perr:1; 496 uint64_t reserved_28_63:36; 497#endif 498 } cn30xx; 499 struct cvmx_fpa_int_enb_cn30xx cn31xx; 500 struct cvmx_fpa_int_enb_cn30xx cn38xx; 501 struct cvmx_fpa_int_enb_cn30xx cn38xxp2; 502 struct cvmx_fpa_int_enb_cn30xx cn50xx; 503 struct cvmx_fpa_int_enb_cn30xx cn52xx; 504 struct cvmx_fpa_int_enb_cn30xx cn52xxp1; 505 struct cvmx_fpa_int_enb_cn30xx cn56xx; 506 struct cvmx_fpa_int_enb_cn30xx cn56xxp1; 507 struct cvmx_fpa_int_enb_cn30xx cn58xx; 508 struct cvmx_fpa_int_enb_cn30xx cn58xxp1; 509 struct cvmx_fpa_int_enb_cn61xx { 510#ifdef __BIG_ENDIAN_BITFIELD 511 uint64_t reserved_50_63:14; 512 uint64_t paddr_e:1; 513 uint64_t res_44:5; 514 uint64_t free7:1; 515 uint64_t free6:1; 516 uint64_t free5:1; 517 uint64_t free4:1; 518 uint64_t free3:1; 519 uint64_t free2:1; 520 uint64_t free1:1; 521 uint64_t free0:1; 522 uint64_t pool7th:1; 523 uint64_t pool6th:1; 524 uint64_t pool5th:1; 525 uint64_t pool4th:1; 526 uint64_t pool3th:1; 527 uint64_t pool2th:1; 528 uint64_t pool1th:1; 529 uint64_t pool0th:1; 530 uint64_t q7_perr:1; 531 uint64_t q7_coff:1; 532 uint64_t q7_und:1; 533 uint64_t q6_perr:1; 534 uint64_t q6_coff:1; 535 uint64_t q6_und:1; 536 uint64_t q5_perr:1; 537 uint64_t q5_coff:1; 538 uint64_t q5_und:1; 539 uint64_t q4_perr:1; 540 uint64_t q4_coff:1; 541 uint64_t q4_und:1; 542 uint64_t q3_perr:1; 543 uint64_t q3_coff:1; 544 uint64_t q3_und:1; 545 uint64_t q2_perr:1; 546 uint64_t q2_coff:1; 547 uint64_t q2_und:1; 548 uint64_t q1_perr:1; 549 uint64_t q1_coff:1; 550 uint64_t q1_und:1; 551 uint64_t q0_perr:1; 552 uint64_t q0_coff:1; 553 uint64_t q0_und:1; 554 uint64_t fed1_dbe:1; 555 uint64_t fed1_sbe:1; 556 uint64_t fed0_dbe:1; 557 uint64_t fed0_sbe:1; 558#else 559 uint64_t fed0_sbe:1; 560 uint64_t fed0_dbe:1; 561 uint64_t fed1_sbe:1; 562 uint64_t fed1_dbe:1; 563 uint64_t q0_und:1; 564 uint64_t q0_coff:1; 565 uint64_t q0_perr:1; 566 uint64_t q1_und:1; 567 uint64_t q1_coff:1; 568 uint64_t q1_perr:1; 569 uint64_t q2_und:1; 570 uint64_t q2_coff:1; 571 uint64_t q2_perr:1; 572 uint64_t q3_und:1; 573 uint64_t q3_coff:1; 574 uint64_t q3_perr:1; 575 uint64_t q4_und:1; 576 uint64_t q4_coff:1; 577 uint64_t q4_perr:1; 578 uint64_t q5_und:1; 579 uint64_t q5_coff:1; 580 uint64_t q5_perr:1; 581 uint64_t q6_und:1; 582 uint64_t q6_coff:1; 583 uint64_t q6_perr:1; 584 uint64_t q7_und:1; 585 uint64_t q7_coff:1; 586 uint64_t q7_perr:1; 587 uint64_t pool0th:1; 588 uint64_t pool1th:1; 589 uint64_t pool2th:1; 590 uint64_t pool3th:1; 591 uint64_t pool4th:1; 592 uint64_t pool5th:1; 593 uint64_t pool6th:1; 594 uint64_t pool7th:1; 595 uint64_t free0:1; 596 uint64_t free1:1; 597 uint64_t free2:1; 598 uint64_t free3:1; 599 uint64_t free4:1; 600 uint64_t free5:1; 601 uint64_t free6:1; 602 uint64_t free7:1; 603 uint64_t res_44:5; 604 uint64_t paddr_e:1; 605 uint64_t reserved_50_63:14; 606#endif 607 } cn61xx; 608 struct cvmx_fpa_int_enb_cn63xx { 609#ifdef __BIG_ENDIAN_BITFIELD 610 uint64_t reserved_44_63:20; 611 uint64_t free7:1; 612 uint64_t free6:1; 613 uint64_t free5:1; 614 uint64_t free4:1; 615 uint64_t free3:1; 616 uint64_t free2:1; 617 uint64_t free1:1; 618 uint64_t free0:1; 619 uint64_t pool7th:1; 620 uint64_t pool6th:1; 621 uint64_t pool5th:1; 622 uint64_t pool4th:1; 623 uint64_t pool3th:1; 624 uint64_t pool2th:1; 625 uint64_t pool1th:1; 626 uint64_t pool0th:1; 627 uint64_t q7_perr:1; 628 uint64_t q7_coff:1; 629 uint64_t q7_und:1; 630 uint64_t q6_perr:1; 631 uint64_t q6_coff:1; 632 uint64_t q6_und:1; 633 uint64_t q5_perr:1; 634 uint64_t q5_coff:1; 635 uint64_t q5_und:1; 636 uint64_t q4_perr:1; 637 uint64_t q4_coff:1; 638 uint64_t q4_und:1; 639 uint64_t q3_perr:1; 640 uint64_t q3_coff:1; 641 uint64_t q3_und:1; 642 uint64_t q2_perr:1; 643 uint64_t q2_coff:1; 644 uint64_t q2_und:1; 645 uint64_t q1_perr:1; 646 uint64_t q1_coff:1; 647 uint64_t q1_und:1; 648 uint64_t q0_perr:1; 649 uint64_t q0_coff:1; 650 uint64_t q0_und:1; 651 uint64_t fed1_dbe:1; 652 uint64_t fed1_sbe:1; 653 uint64_t fed0_dbe:1; 654 uint64_t fed0_sbe:1; 655#else 656 uint64_t fed0_sbe:1; 657 uint64_t fed0_dbe:1; 658 uint64_t fed1_sbe:1; 659 uint64_t fed1_dbe:1; 660 uint64_t q0_und:1; 661 uint64_t q0_coff:1; 662 uint64_t q0_perr:1; 663 uint64_t q1_und:1; 664 uint64_t q1_coff:1; 665 uint64_t q1_perr:1; 666 uint64_t q2_und:1; 667 uint64_t q2_coff:1; 668 uint64_t q2_perr:1; 669 uint64_t q3_und:1; 670 uint64_t q3_coff:1; 671 uint64_t q3_perr:1; 672 uint64_t q4_und:1; 673 uint64_t q4_coff:1; 674 uint64_t q4_perr:1; 675 uint64_t q5_und:1; 676 uint64_t q5_coff:1; 677 uint64_t q5_perr:1; 678 uint64_t q6_und:1; 679 uint64_t q6_coff:1; 680 uint64_t q6_perr:1; 681 uint64_t q7_und:1; 682 uint64_t q7_coff:1; 683 uint64_t q7_perr:1; 684 uint64_t pool0th:1; 685 uint64_t pool1th:1; 686 uint64_t pool2th:1; 687 uint64_t pool3th:1; 688 uint64_t pool4th:1; 689 uint64_t pool5th:1; 690 uint64_t pool6th:1; 691 uint64_t pool7th:1; 692 uint64_t free0:1; 693 uint64_t free1:1; 694 uint64_t free2:1; 695 uint64_t free3:1; 696 uint64_t free4:1; 697 uint64_t free5:1; 698 uint64_t free6:1; 699 uint64_t free7:1; 700 uint64_t reserved_44_63:20; 701#endif 702 } cn63xx; 703 struct cvmx_fpa_int_enb_cn30xx cn63xxp1; 704 struct cvmx_fpa_int_enb_cn61xx cn66xx; 705 struct cvmx_fpa_int_enb_cn68xx { 706#ifdef __BIG_ENDIAN_BITFIELD 707 uint64_t reserved_50_63:14; 708 uint64_t paddr_e:1; 709 uint64_t pool8th:1; 710 uint64_t q8_perr:1; 711 uint64_t q8_coff:1; 712 uint64_t q8_und:1; 713 uint64_t free8:1; 714 uint64_t free7:1; 715 uint64_t free6:1; 716 uint64_t free5:1; 717 uint64_t free4:1; 718 uint64_t free3:1; 719 uint64_t free2:1; 720 uint64_t free1:1; 721 uint64_t free0:1; 722 uint64_t pool7th:1; 723 uint64_t pool6th:1; 724 uint64_t pool5th:1; 725 uint64_t pool4th:1; 726 uint64_t pool3th:1; 727 uint64_t pool2th:1; 728 uint64_t pool1th:1; 729 uint64_t pool0th:1; 730 uint64_t q7_perr:1; 731 uint64_t q7_coff:1; 732 uint64_t q7_und:1; 733 uint64_t q6_perr:1; 734 uint64_t q6_coff:1; 735 uint64_t q6_und:1; 736 uint64_t q5_perr:1; 737 uint64_t q5_coff:1; 738 uint64_t q5_und:1; 739 uint64_t q4_perr:1; 740 uint64_t q4_coff:1; 741 uint64_t q4_und:1; 742 uint64_t q3_perr:1; 743 uint64_t q3_coff:1; 744 uint64_t q3_und:1; 745 uint64_t q2_perr:1; 746 uint64_t q2_coff:1; 747 uint64_t q2_und:1; 748 uint64_t q1_perr:1; 749 uint64_t q1_coff:1; 750 uint64_t q1_und:1; 751 uint64_t q0_perr:1; 752 uint64_t q0_coff:1; 753 uint64_t q0_und:1; 754 uint64_t fed1_dbe:1; 755 uint64_t fed1_sbe:1; 756 uint64_t fed0_dbe:1; 757 uint64_t fed0_sbe:1; 758#else 759 uint64_t fed0_sbe:1; 760 uint64_t fed0_dbe:1; 761 uint64_t fed1_sbe:1; 762 uint64_t fed1_dbe:1; 763 uint64_t q0_und:1; 764 uint64_t q0_coff:1; 765 uint64_t q0_perr:1; 766 uint64_t q1_und:1; 767 uint64_t q1_coff:1; 768 uint64_t q1_perr:1; 769 uint64_t q2_und:1; 770 uint64_t q2_coff:1; 771 uint64_t q2_perr:1; 772 uint64_t q3_und:1; 773 uint64_t q3_coff:1; 774 uint64_t q3_perr:1; 775 uint64_t q4_und:1; 776 uint64_t q4_coff:1; 777 uint64_t q4_perr:1; 778 uint64_t q5_und:1; 779 uint64_t q5_coff:1; 780 uint64_t q5_perr:1; 781 uint64_t q6_und:1; 782 uint64_t q6_coff:1; 783 uint64_t q6_perr:1; 784 uint64_t q7_und:1; 785 uint64_t q7_coff:1; 786 uint64_t q7_perr:1; 787 uint64_t pool0th:1; 788 uint64_t pool1th:1; 789 uint64_t pool2th:1; 790 uint64_t pool3th:1; 791 uint64_t pool4th:1; 792 uint64_t pool5th:1; 793 uint64_t pool6th:1; 794 uint64_t pool7th:1; 795 uint64_t free0:1; 796 uint64_t free1:1; 797 uint64_t free2:1; 798 uint64_t free3:1; 799 uint64_t free4:1; 800 uint64_t free5:1; 801 uint64_t free6:1; 802 uint64_t free7:1; 803 uint64_t free8:1; 804 uint64_t q8_und:1; 805 uint64_t q8_coff:1; 806 uint64_t q8_perr:1; 807 uint64_t pool8th:1; 808 uint64_t paddr_e:1; 809 uint64_t reserved_50_63:14; 810#endif 811 } cn68xx; 812 struct cvmx_fpa_int_enb_cn68xx cn68xxp1; 813 struct cvmx_fpa_int_enb_cn61xx cnf71xx; 814}; 815 816union cvmx_fpa_int_sum { 817 uint64_t u64; 818 struct cvmx_fpa_int_sum_s { 819#ifdef __BIG_ENDIAN_BITFIELD 820 uint64_t reserved_50_63:14; 821 uint64_t paddr_e:1; 822 uint64_t pool8th:1; 823 uint64_t q8_perr:1; 824 uint64_t q8_coff:1; 825 uint64_t q8_und:1; 826 uint64_t free8:1; 827 uint64_t free7:1; 828 uint64_t free6:1; 829 uint64_t free5:1; 830 uint64_t free4:1; 831 uint64_t free3:1; 832 uint64_t free2:1; 833 uint64_t free1:1; 834 uint64_t free0:1; 835 uint64_t pool7th:1; 836 uint64_t pool6th:1; 837 uint64_t pool5th:1; 838 uint64_t pool4th:1; 839 uint64_t pool3th:1; 840 uint64_t pool2th:1; 841 uint64_t pool1th:1; 842 uint64_t pool0th:1; 843 uint64_t q7_perr:1; 844 uint64_t q7_coff:1; 845 uint64_t q7_und:1; 846 uint64_t q6_perr:1; 847 uint64_t q6_coff:1; 848 uint64_t q6_und:1; 849 uint64_t q5_perr:1; 850 uint64_t q5_coff:1; 851 uint64_t q5_und:1; 852 uint64_t q4_perr:1; 853 uint64_t q4_coff:1; 854 uint64_t q4_und:1; 855 uint64_t q3_perr:1; 856 uint64_t q3_coff:1; 857 uint64_t q3_und:1; 858 uint64_t q2_perr:1; 859 uint64_t q2_coff:1; 860 uint64_t q2_und:1; 861 uint64_t q1_perr:1; 862 uint64_t q1_coff:1; 863 uint64_t q1_und:1; 864 uint64_t q0_perr:1; 865 uint64_t q0_coff:1; 866 uint64_t q0_und:1; 867 uint64_t fed1_dbe:1; 868 uint64_t fed1_sbe:1; 869 uint64_t fed0_dbe:1; 870 uint64_t fed0_sbe:1; 871#else 872 uint64_t fed0_sbe:1; 873 uint64_t fed0_dbe:1; 874 uint64_t fed1_sbe:1; 875 uint64_t fed1_dbe:1; 876 uint64_t q0_und:1; 877 uint64_t q0_coff:1; 878 uint64_t q0_perr:1; 879 uint64_t q1_und:1; 880 uint64_t q1_coff:1; 881 uint64_t q1_perr:1; 882 uint64_t q2_und:1; 883 uint64_t q2_coff:1; 884 uint64_t q2_perr:1; 885 uint64_t q3_und:1; 886 uint64_t q3_coff:1; 887 uint64_t q3_perr:1; 888 uint64_t q4_und:1; 889 uint64_t q4_coff:1; 890 uint64_t q4_perr:1; 891 uint64_t q5_und:1; 892 uint64_t q5_coff:1; 893 uint64_t q5_perr:1; 894 uint64_t q6_und:1; 895 uint64_t q6_coff:1; 896 uint64_t q6_perr:1; 897 uint64_t q7_und:1; 898 uint64_t q7_coff:1; 899 uint64_t q7_perr:1; 900 uint64_t pool0th:1; 901 uint64_t pool1th:1; 902 uint64_t pool2th:1; 903 uint64_t pool3th:1; 904 uint64_t pool4th:1; 905 uint64_t pool5th:1; 906 uint64_t pool6th:1; 907 uint64_t pool7th:1; 908 uint64_t free0:1; 909 uint64_t free1:1; 910 uint64_t free2:1; 911 uint64_t free3:1; 912 uint64_t free4:1; 913 uint64_t free5:1; 914 uint64_t free6:1; 915 uint64_t free7:1; 916 uint64_t free8:1; 917 uint64_t q8_und:1; 918 uint64_t q8_coff:1; 919 uint64_t q8_perr:1; 920 uint64_t pool8th:1; 921 uint64_t paddr_e:1; 922 uint64_t reserved_50_63:14; 923#endif 924 } s; 925 struct cvmx_fpa_int_sum_cn30xx { 926#ifdef __BIG_ENDIAN_BITFIELD 927 uint64_t reserved_28_63:36; 928 uint64_t q7_perr:1; 929 uint64_t q7_coff:1; 930 uint64_t q7_und:1; 931 uint64_t q6_perr:1; 932 uint64_t q6_coff:1; 933 uint64_t q6_und:1; 934 uint64_t q5_perr:1; 935 uint64_t q5_coff:1; 936 uint64_t q5_und:1; 937 uint64_t q4_perr:1; 938 uint64_t q4_coff:1; 939 uint64_t q4_und:1; 940 uint64_t q3_perr:1; 941 uint64_t q3_coff:1; 942 uint64_t q3_und:1; 943 uint64_t q2_perr:1; 944 uint64_t q2_coff:1; 945 uint64_t q2_und:1; 946 uint64_t q1_perr:1; 947 uint64_t q1_coff:1; 948 uint64_t q1_und:1; 949 uint64_t q0_perr:1; 950 uint64_t q0_coff:1; 951 uint64_t q0_und:1; 952 uint64_t fed1_dbe:1; 953 uint64_t fed1_sbe:1; 954 uint64_t fed0_dbe:1; 955 uint64_t fed0_sbe:1; 956#else 957 uint64_t fed0_sbe:1; 958 uint64_t fed0_dbe:1; 959 uint64_t fed1_sbe:1; 960 uint64_t fed1_dbe:1; 961 uint64_t q0_und:1; 962 uint64_t q0_coff:1; 963 uint64_t q0_perr:1; 964 uint64_t q1_und:1; 965 uint64_t q1_coff:1; 966 uint64_t q1_perr:1; 967 uint64_t q2_und:1; 968 uint64_t q2_coff:1; 969 uint64_t q2_perr:1; 970 uint64_t q3_und:1; 971 uint64_t q3_coff:1; 972 uint64_t q3_perr:1; 973 uint64_t q4_und:1; 974 uint64_t q4_coff:1; 975 uint64_t q4_perr:1; 976 uint64_t q5_und:1; 977 uint64_t q5_coff:1; 978 uint64_t q5_perr:1; 979 uint64_t q6_und:1; 980 uint64_t q6_coff:1; 981 uint64_t q6_perr:1; 982 uint64_t q7_und:1; 983 uint64_t q7_coff:1; 984 uint64_t q7_perr:1; 985 uint64_t reserved_28_63:36; 986#endif 987 } cn30xx; 988 struct cvmx_fpa_int_sum_cn30xx cn31xx; 989 struct cvmx_fpa_int_sum_cn30xx cn38xx; 990 struct cvmx_fpa_int_sum_cn30xx cn38xxp2; 991 struct cvmx_fpa_int_sum_cn30xx cn50xx; 992 struct cvmx_fpa_int_sum_cn30xx cn52xx; 993 struct cvmx_fpa_int_sum_cn30xx cn52xxp1; 994 struct cvmx_fpa_int_sum_cn30xx cn56xx; 995 struct cvmx_fpa_int_sum_cn30xx cn56xxp1; 996 struct cvmx_fpa_int_sum_cn30xx cn58xx; 997 struct cvmx_fpa_int_sum_cn30xx cn58xxp1; 998 struct cvmx_fpa_int_sum_cn61xx { 999#ifdef __BIG_ENDIAN_BITFIELD 1000 uint64_t reserved_50_63:14;
1001 uint64_t paddr_e:1; 1002 uint64_t reserved_44_48:5; 1003 uint64_t free7:1; 1004 uint64_t free6:1; 1005 uint64_t free5:1; 1006 uint64_t free4:1; 1007 uint64_t free3:1; 1008 uint64_t free2:1; 1009 uint64_t free1:1; 1010 uint64_t free0:1; 1011 uint64_t pool7th:1; 1012 uint64_t pool6th:1; 1013 uint64_t pool5th:1; 1014 uint64_t pool4th:1; 1015 uint64_t pool3th:1; 1016 uint64_t pool2th:1; 1017 uint64_t pool1th:1; 1018 uint64_t pool0th:1; 1019 uint64_t q7_perr:1; 1020 uint64_t q7_coff:1; 1021 uint64_t q7_und:1; 1022 uint64_t q6_perr:1; 1023 uint64_t q6_coff:1; 1024 uint64_t q6_und:1; 1025 uint64_t q5_perr:1; 1026 uint64_t q5_coff:1; 1027 uint64_t q5_und:1; 1028 uint64_t q4_perr:1; 1029 uint64_t q4_coff:1; 1030 uint64_t q4_und:1; 1031 uint64_t q3_perr:1; 1032 uint64_t q3_coff:1; 1033 uint64_t q3_und:1; 1034 uint64_t q2_perr:1; 1035 uint64_t q2_coff:1; 1036 uint64_t q2_und:1; 1037 uint64_t q1_perr:1; 1038 uint64_t q1_coff:1; 1039 uint64_t q1_und:1; 1040 uint64_t q0_perr:1; 1041 uint64_t q0_coff:1; 1042 uint64_t q0_und:1; 1043 uint64_t fed1_dbe:1; 1044 uint64_t fed1_sbe:1; 1045 uint64_t fed0_dbe:1; 1046 uint64_t fed0_sbe:1; 1047#else 1048 uint64_t fed0_sbe:1; 1049 uint64_t fed0_dbe:1; 1050 uint64_t fed1_sbe:1; 1051 uint64_t fed1_dbe:1; 1052 uint64_t q0_und:1; 1053 uint64_t q0_coff:1; 1054 uint64_t q0_perr:1; 1055 uint64_t q1_und:1; 1056 uint64_t q1_coff:1; 1057 uint64_t q1_perr:1; 1058 uint64_t q2_und:1; 1059 uint64_t q2_coff:1; 1060 uint64_t q2_perr:1; 1061 uint64_t q3_und:1; 1062 uint64_t q3_coff:1; 1063 uint64_t q3_perr:1; 1064 uint64_t q4_und:1; 1065 uint64_t q4_coff:1; 1066 uint64_t q4_perr:1; 1067 uint64_t q5_und:1; 1068 uint64_t q5_coff:1; 1069 uint64_t q5_perr:1; 1070 uint64_t q6_und:1; 1071 uint64_t q6_coff:1; 1072 uint64_t q6_perr:1; 1073 uint64_t q7_und:1; 1074 uint64_t q7_coff:1; 1075 uint64_t q7_perr:1; 1076 uint64_t pool0th:1; 1077 uint64_t pool1th:1; 1078 uint64_t pool2th:1; 1079 uint64_t pool3th:1; 1080 uint64_t pool4th:1; 1081 uint64_t pool5th:1; 1082 uint64_t pool6th:1; 1083 uint64_t pool7th:1; 1084 uint64_t free0:1; 1085 uint64_t free1:1; 1086 uint64_t free2:1; 1087 uint64_t free3:1; 1088 uint64_t free4:1; 1089 uint64_t free5:1; 1090 uint64_t free6:1; 1091 uint64_t free7:1; 1092 uint64_t reserved_44_48:5; 1093 uint64_t paddr_e:1; 1094 uint64_t reserved_50_63:14; 1095#endif 1096 } cn61xx; 1097 struct cvmx_fpa_int_sum_cn63xx { 1098#ifdef __BIG_ENDIAN_BITFIELD 1099 uint64_t reserved_44_63:20; 1100 uint64_t free7:1; 1101 uint64_t free6:1; 1102 uint64_t free5:1; 1103 uint64_t free4:1; 1104 uint64_t free3:1; 1105 uint64_t free2:1; 1106 uint64_t free1:1; 1107 uint64_t free0:1; 1108 uint64_t pool7th:1; 1109 uint64_t pool6th:1; 1110 uint64_t pool5th:1; 1111 uint64_t pool4th:1; 1112 uint64_t pool3th:1; 1113 uint64_t pool2th:1; 1114 uint64_t pool1th:1; 1115 uint64_t pool0th:1; 1116 uint64_t q7_perr:1; 1117 uint64_t q7_coff:1; 1118 uint64_t q7_und:1; 1119 uint64_t q6_perr:1; 1120 uint64_t q6_coff:1; 1121 uint64_t q6_und:1; 1122 uint64_t q5_perr:1; 1123 uint64_t q5_coff:1; 1124 uint64_t q5_und:1; 1125 uint64_t q4_perr:1; 1126 uint64_t q4_coff:1; 1127 uint64_t q4_und:1; 1128 uint64_t q3_perr:1; 1129 uint64_t q3_coff:1; 1130 uint64_t q3_und:1; 1131 uint64_t q2_perr:1; 1132 uint64_t q2_coff:1; 1133 uint64_t q2_und:1; 1134 uint64_t q1_perr:1; 1135 uint64_t q1_coff:1; 1136 uint64_t q1_und:1; 1137 uint64_t q0_perr:1; 1138 uint64_t q0_coff:1; 1139 uint64_t q0_und:1; 1140 uint64_t fed1_dbe:1; 1141 uint64_t fed1_sbe:1; 1142 uint64_t fed0_dbe:1; 1143 uint64_t fed0_sbe:1; 1144#else 1145 uint64_t fed0_sbe:1; 1146 uint64_t fed0_dbe:1; 1147 uint64_t fed1_sbe:1; 1148 uint64_t fed1_dbe:1; 1149 uint64_t q0_und:1; 1150 uint64_t q0_coff:1; 1151 uint64_t q0_perr:1; 1152 uint64_t q1_und:1; 1153 uint64_t q1_coff:1; 1154 uint64_t q1_perr:1; 1155 uint64_t q2_und:1; 1156 uint64_t q2_coff:1; 1157 uint64_t q2_perr:1; 1158 uint64_t q3_und:1; 1159 uint64_t q3_coff:1; 1160 uint64_t q3_perr:1; 1161 uint64_t q4_und:1; 1162 uint64_t q4_coff:1; 1163 uint64_t q4_perr:1; 1164 uint64_t q5_und:1; 1165 uint64_t q5_coff:1; 1166 uint64_t q5_perr:1; 1167 uint64_t q6_und:1; 1168 uint64_t q6_coff:1; 1169 uint64_t q6_perr:1; 1170 uint64_t q7_und:1; 1171 uint64_t q7_coff:1; 1172 uint64_t q7_perr:1; 1173 uint64_t pool0th:1; 1174 uint64_t pool1th:1; 1175 uint64_t pool2th:1; 1176 uint64_t pool3th:1; 1177 uint64_t pool4th:1; 1178 uint64_t pool5th:1; 1179 uint64_t pool6th:1; 1180 uint64_t pool7th:1; 1181 uint64_t free0:1; 1182 uint64_t free1:1; 1183 uint64_t free2:1; 1184 uint64_t free3:1; 1185 uint64_t free4:1; 1186 uint64_t free5:1; 1187 uint64_t free6:1; 1188 uint64_t free7:1; 1189 uint64_t reserved_44_63:20; 1190#endif 1191 } cn63xx; 1192 struct cvmx_fpa_int_sum_cn30xx cn63xxp1; 1193 struct cvmx_fpa_int_sum_cn61xx cn66xx; 1194 struct cvmx_fpa_int_sum_s cn68xx; 1195 struct cvmx_fpa_int_sum_s cn68xxp1; 1196 struct cvmx_fpa_int_sum_cn61xx cnf71xx; 1197}; 1198 1199union cvmx_fpa_packet_threshold { 1200 uint64_t u64; 1201 struct cvmx_fpa_packet_threshold_s { 1202#ifdef __BIG_ENDIAN_BITFIELD 1203 uint64_t reserved_32_63:32; 1204 uint64_t thresh:32; 1205#else 1206 uint64_t thresh:32; 1207 uint64_t reserved_32_63:32; 1208#endif 1209 } s; 1210 struct cvmx_fpa_packet_threshold_s cn61xx; 1211 struct cvmx_fpa_packet_threshold_s cn63xx; 1212 struct cvmx_fpa_packet_threshold_s cn66xx; 1213 struct cvmx_fpa_packet_threshold_s cn68xx; 1214 struct cvmx_fpa_packet_threshold_s cn68xxp1; 1215 struct cvmx_fpa_packet_threshold_s cnf71xx; 1216}; 1217 1218union cvmx_fpa_poolx_end_addr { 1219 uint64_t u64; 1220 struct cvmx_fpa_poolx_end_addr_s { 1221#ifdef __BIG_ENDIAN_BITFIELD 1222 uint64_t reserved_33_63:31; 1223 uint64_t addr:33; 1224#else 1225 uint64_t addr:33; 1226 uint64_t reserved_33_63:31; 1227#endif 1228 } s; 1229 struct cvmx_fpa_poolx_end_addr_s cn61xx; 1230 struct cvmx_fpa_poolx_end_addr_s cn66xx; 1231 struct cvmx_fpa_poolx_end_addr_s cn68xx; 1232 struct cvmx_fpa_poolx_end_addr_s cn68xxp1; 1233 struct cvmx_fpa_poolx_end_addr_s cnf71xx; 1234}; 1235 1236union cvmx_fpa_poolx_start_addr { 1237 uint64_t u64; 1238 struct cvmx_fpa_poolx_start_addr_s { 1239#ifdef __BIG_ENDIAN_BITFIELD 1240 uint64_t reserved_33_63:31; 1241 uint64_t addr:33; 1242#else 1243 uint64_t addr:33; 1244 uint64_t reserved_33_63:31; 1245#endif 1246 } s; 1247 struct cvmx_fpa_poolx_start_addr_s cn61xx; 1248 struct cvmx_fpa_poolx_start_addr_s cn66xx; 1249 struct cvmx_fpa_poolx_start_addr_s cn68xx; 1250 struct cvmx_fpa_poolx_start_addr_s cn68xxp1; 1251 struct cvmx_fpa_poolx_start_addr_s cnf71xx; 1252}; 1253 1254union cvmx_fpa_poolx_threshold { 1255 uint64_t u64; 1256 struct cvmx_fpa_poolx_threshold_s { 1257#ifdef __BIG_ENDIAN_BITFIELD 1258 uint64_t reserved_32_63:32; 1259 uint64_t thresh:32; 1260#else 1261 uint64_t thresh:32; 1262 uint64_t reserved_32_63:32; 1263#endif 1264 } s; 1265 struct cvmx_fpa_poolx_threshold_cn61xx { 1266#ifdef __BIG_ENDIAN_BITFIELD 1267 uint64_t reserved_29_63:35; 1268 uint64_t thresh:29; 1269#else 1270 uint64_t thresh:29; 1271 uint64_t reserved_29_63:35; 1272#endif 1273 } cn61xx; 1274 struct cvmx_fpa_poolx_threshold_cn61xx cn63xx; 1275 struct cvmx_fpa_poolx_threshold_cn61xx cn66xx; 1276 struct cvmx_fpa_poolx_threshold_s cn68xx; 1277 struct cvmx_fpa_poolx_threshold_s cn68xxp1; 1278 struct cvmx_fpa_poolx_threshold_cn61xx cnf71xx; 1279}; 1280 1281union cvmx_fpa_quex_available { 1282 uint64_t u64; 1283 struct cvmx_fpa_quex_available_s { 1284#ifdef __BIG_ENDIAN_BITFIELD 1285 uint64_t reserved_32_63:32; 1286 uint64_t que_siz:32; 1287#else 1288 uint64_t que_siz:32; 1289 uint64_t reserved_32_63:32; 1290#endif 1291 } s; 1292 struct cvmx_fpa_quex_available_cn30xx { 1293#ifdef __BIG_ENDIAN_BITFIELD 1294 uint64_t reserved_29_63:35; 1295 uint64_t que_siz:29; 1296#else 1297 uint64_t que_siz:29; 1298 uint64_t reserved_29_63:35; 1299#endif 1300 } cn30xx; 1301 struct cvmx_fpa_quex_available_cn30xx cn31xx; 1302 struct cvmx_fpa_quex_available_cn30xx cn38xx; 1303 struct cvmx_fpa_quex_available_cn30xx cn38xxp2; 1304 struct cvmx_fpa_quex_available_cn30xx cn50xx; 1305 struct cvmx_fpa_quex_available_cn30xx cn52xx; 1306 struct cvmx_fpa_quex_available_cn30xx cn52xxp1; 1307 struct cvmx_fpa_quex_available_cn30xx cn56xx; 1308 struct cvmx_fpa_quex_available_cn30xx cn56xxp1; 1309 struct cvmx_fpa_quex_available_cn30xx cn58xx; 1310 struct cvmx_fpa_quex_available_cn30xx cn58xxp1; 1311 struct cvmx_fpa_quex_available_cn30xx cn61xx; 1312 struct cvmx_fpa_quex_available_cn30xx cn63xx; 1313 struct cvmx_fpa_quex_available_cn30xx cn63xxp1; 1314 struct cvmx_fpa_quex_available_cn30xx cn66xx; 1315 struct cvmx_fpa_quex_available_s cn68xx; 1316 struct cvmx_fpa_quex_available_s cn68xxp1; 1317 struct cvmx_fpa_quex_available_cn30xx cnf71xx; 1318}; 1319 1320union cvmx_fpa_quex_page_index { 1321 uint64_t u64; 1322 struct cvmx_fpa_quex_page_index_s { 1323#ifdef __BIG_ENDIAN_BITFIELD 1324 uint64_t reserved_25_63:39; 1325 uint64_t pg_num:25; 1326#else 1327 uint64_t pg_num:25; 1328 uint64_t reserved_25_63:39; 1329#endif 1330 } s; 1331 struct cvmx_fpa_quex_page_index_s cn30xx; 1332 struct cvmx_fpa_quex_page_index_s cn31xx; 1333 struct cvmx_fpa_quex_page_index_s cn38xx; 1334 struct cvmx_fpa_quex_page_index_s cn38xxp2; 1335 struct cvmx_fpa_quex_page_index_s cn50xx; 1336 struct cvmx_fpa_quex_page_index_s cn52xx; 1337 struct cvmx_fpa_quex_page_index_s cn52xxp1; 1338 struct cvmx_fpa_quex_page_index_s cn56xx; 1339 struct cvmx_fpa_quex_page_index_s cn56xxp1; 1340 struct cvmx_fpa_quex_page_index_s cn58xx; 1341 struct cvmx_fpa_quex_page_index_s cn58xxp1; 1342 struct cvmx_fpa_quex_page_index_s cn61xx; 1343 struct cvmx_fpa_quex_page_index_s cn63xx; 1344 struct cvmx_fpa_quex_page_index_s cn63xxp1; 1345 struct cvmx_fpa_quex_page_index_s cn66xx; 1346 struct cvmx_fpa_quex_page_index_s cn68xx; 1347 struct cvmx_fpa_quex_page_index_s cn68xxp1; 1348 struct cvmx_fpa_quex_page_index_s cnf71xx; 1349}; 1350 1351union cvmx_fpa_que8_page_index { 1352 uint64_t u64; 1353 struct cvmx_fpa_que8_page_index_s { 1354#ifdef __BIG_ENDIAN_BITFIELD 1355 uint64_t reserved_25_63:39; 1356 uint64_t pg_num:25; 1357#else 1358 uint64_t pg_num:25; 1359 uint64_t reserved_25_63:39; 1360#endif 1361 } s; 1362 struct cvmx_fpa_que8_page_index_s cn68xx; 1363 struct cvmx_fpa_que8_page_index_s cn68xxp1; 1364}; 1365 1366union cvmx_fpa_que_act { 1367 uint64_t u64; 1368 struct cvmx_fpa_que_act_s { 1369#ifdef __BIG_ENDIAN_BITFIELD 1370 uint64_t reserved_29_63:35; 1371 uint64_t act_que:3; 1372 uint64_t act_indx:26; 1373#else 1374 uint64_t act_indx:26; 1375 uint64_t act_que:3; 1376 uint64_t reserved_29_63:35; 1377#endif 1378 } s; 1379 struct cvmx_fpa_que_act_s cn30xx; 1380 struct cvmx_fpa_que_act_s cn31xx; 1381 struct cvmx_fpa_que_act_s cn38xx; 1382 struct cvmx_fpa_que_act_s cn38xxp2; 1383 struct cvmx_fpa_que_act_s cn50xx; 1384 struct cvmx_fpa_que_act_s cn52xx; 1385 struct cvmx_fpa_que_act_s cn52xxp1; 1386 struct cvmx_fpa_que_act_s cn56xx; 1387 struct cvmx_fpa_que_act_s cn56xxp1; 1388 struct cvmx_fpa_que_act_s cn58xx; 1389 struct cvmx_fpa_que_act_s cn58xxp1; 1390 struct cvmx_fpa_que_act_s cn61xx; 1391 struct cvmx_fpa_que_act_s cn63xx; 1392 struct cvmx_fpa_que_act_s cn63xxp1; 1393 struct cvmx_fpa_que_act_s cn66xx; 1394 struct cvmx_fpa_que_act_s cn68xx; 1395 struct cvmx_fpa_que_act_s cn68xxp1; 1396 struct cvmx_fpa_que_act_s cnf71xx; 1397}; 1398 1399union cvmx_fpa_que_exp { 1400 uint64_t u64; 1401 struct cvmx_fpa_que_exp_s { 1402#ifdef __BIG_ENDIAN_BITFIELD 1403 uint64_t reserved_29_63:35; 1404 uint64_t exp_que:3; 1405 uint64_t exp_indx:26; 1406#else 1407 uint64_t exp_indx:26; 1408 uint64_t exp_que:3; 1409 uint64_t reserved_29_63:35; 1410#endif 1411 } s; 1412 struct cvmx_fpa_que_exp_s cn30xx; 1413 struct cvmx_fpa_que_exp_s cn31xx; 1414 struct cvmx_fpa_que_exp_s cn38xx; 1415 struct cvmx_fpa_que_exp_s cn38xxp2; 1416 struct cvmx_fpa_que_exp_s cn50xx; 1417 struct cvmx_fpa_que_exp_s cn52xx; 1418 struct cvmx_fpa_que_exp_s cn52xxp1; 1419 struct cvmx_fpa_que_exp_s cn56xx; 1420 struct cvmx_fpa_que_exp_s cn56xxp1; 1421 struct cvmx_fpa_que_exp_s cn58xx; 1422 struct cvmx_fpa_que_exp_s cn58xxp1; 1423 struct cvmx_fpa_que_exp_s cn61xx; 1424 struct cvmx_fpa_que_exp_s cn63xx; 1425 struct cvmx_fpa_que_exp_s cn63xxp1; 1426 struct cvmx_fpa_que_exp_s cn66xx; 1427 struct cvmx_fpa_que_exp_s cn68xx; 1428 struct cvmx_fpa_que_exp_s cn68xxp1; 1429 struct cvmx_fpa_que_exp_s cnf71xx; 1430}; 1431 1432union cvmx_fpa_wart_ctl { 1433 uint64_t u64; 1434 struct cvmx_fpa_wart_ctl_s { 1435#ifdef __BIG_ENDIAN_BITFIELD 1436 uint64_t reserved_16_63:48; 1437 uint64_t ctl:16; 1438#else 1439 uint64_t ctl:16; 1440 uint64_t reserved_16_63:48; 1441#endif 1442 } s; 1443 struct cvmx_fpa_wart_ctl_s cn30xx; 1444 struct cvmx_fpa_wart_ctl_s cn31xx; 1445 struct cvmx_fpa_wart_ctl_s cn38xx; 1446 struct cvmx_fpa_wart_ctl_s cn38xxp2; 1447 struct cvmx_fpa_wart_ctl_s cn50xx; 1448 struct cvmx_fpa_wart_ctl_s cn52xx; 1449 struct cvmx_fpa_wart_ctl_s cn52xxp1; 1450 struct cvmx_fpa_wart_ctl_s cn56xx; 1451 struct cvmx_fpa_wart_ctl_s cn56xxp1; 1452 struct cvmx_fpa_wart_ctl_s cn58xx; 1453 struct cvmx_fpa_wart_ctl_s cn58xxp1; 1454}; 1455 1456union cvmx_fpa_wart_status { 1457 uint64_t u64; 1458 struct cvmx_fpa_wart_status_s { 1459#ifdef __BIG_ENDIAN_BITFIELD 1460 uint64_t reserved_32_63:32; 1461 uint64_t status:32; 1462#else 1463 uint64_t status:32; 1464 uint64_t reserved_32_63:32; 1465#endif 1466 } s; 1467 struct cvmx_fpa_wart_status_s cn30xx; 1468 struct cvmx_fpa_wart_status_s cn31xx; 1469 struct cvmx_fpa_wart_status_s cn38xx; 1470 struct cvmx_fpa_wart_status_s cn38xxp2; 1471 struct cvmx_fpa_wart_status_s cn50xx; 1472 struct cvmx_fpa_wart_status_s cn52xx; 1473 struct cvmx_fpa_wart_status_s cn52xxp1; 1474 struct cvmx_fpa_wart_status_s cn56xx; 1475 struct cvmx_fpa_wart_status_s cn56xxp1; 1476 struct cvmx_fpa_wart_status_s cn58xx; 1477 struct cvmx_fpa_wart_status_s cn58xxp1; 1478}; 1479 1480union cvmx_fpa_wqe_threshold { 1481 uint64_t u64; 1482 struct cvmx_fpa_wqe_threshold_s { 1483#ifdef __BIG_ENDIAN_BITFIELD 1484 uint64_t reserved_32_63:32; 1485 uint64_t thresh:32; 1486#else 1487 uint64_t thresh:32; 1488 uint64_t reserved_32_63:32; 1489#endif 1490 } s; 1491 struct cvmx_fpa_wqe_threshold_s cn61xx; 1492 struct cvmx_fpa_wqe_threshold_s cn63xx; 1493 struct cvmx_fpa_wqe_threshold_s cn66xx; 1494 struct cvmx_fpa_wqe_threshold_s cn68xx; 1495 struct cvmx_fpa_wqe_threshold_s cn68xxp1; 1496 struct cvmx_fpa_wqe_threshold_s cnf71xx; 1497}; 1498 1499#endif 1500