LXR linux/arch/mips/include/asm/processor.h

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 1994 Waldorf GMBH
   7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
   8 * Copyright (C) 1996 Paul M. Antoine
   9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  10 */
  11#ifndef _ASM_PROCESSOR_H
  12#define _ASM_PROCESSOR_H
  13
  14#include <linux/atomic.h>
  15#include <linux/cpumask.h>
  16#include <linux/threads.h>
  17
  18#include <asm/cachectl.h>
  19#include <asm/cpu.h>
  20#include <asm/cpu-info.h>
  21#include <asm/dsemul.h>
  22#include <asm/mipsregs.h>
  23#include <asm/prefetch.h>
  24
  25/*
  26 * Return current * instruction pointer ("program counter").
  27 */
  28#define current_text_addr() ({ __label__ _l; _l: &&_l;})
  29
  30/*
  31 * System setup and hardware flags..
  32 */
  33
  34extern unsigned int vced_count, vcei_count;
  35
  36/*
  37 * MIPS does have an arch_pick_mmap_layout()
  38 */
  39#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
  40
  41#ifdef CONFIG_32BIT
  42#ifdef CONFIG_KVM_GUEST
  43/* User space process size is limited to 1GB in KVM Guest Mode */
  44#define TASK_SIZE       0x3fff8000UL
  45#else
  46/*
  47 * User space process size: 2GB. This is hardcoded into a few places,
  48 * so don't change it unless you know what you are doing.
  49 */
  50#define TASK_SIZE       0x80000000UL
  51#endif
  52
  53#define STACK_TOP_MAX   TASK_SIZE
  54
  55#define TASK_IS_32BIT_ADDR 1
  56
  57#endif
  58
  59#ifdef CONFIG_64BIT
  60/*
  61 * User space process size: 1TB. This is hardcoded into a few places,
  62 * so don't change it unless you know what you are doing.  TASK_SIZE
  63 * is limited to 1TB by the R4000 architecture; R10000 and better can
  64 * support 16TB; the architectural reserve for future expansion is
  65 * 8192EB ...
  66 */
  67#define TASK_SIZE32     0x7fff8000UL
  68#ifdef CONFIG_MIPS_VA_BITS_48
  69#define TASK_SIZE64     (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
  70#else
  71#define TASK_SIZE64     0x10000000000UL
  72#endif
  73#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
  74#define STACK_TOP_MAX   TASK_SIZE64
  75
  76#define TASK_SIZE_OF(tsk)                                               \
  77        (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
  78
  79#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
  80
  81#endif
  82
  83/*
  84 * One page above the stack is used for branch delay slot "emulation".
  85 * See dsemul.c for details.
  86 */
  87#define STACK_TOP       ((TASK_SIZE & PAGE_MASK) - PAGE_SIZE)
  88
  89/*
  90 * This decides where the kernel will search for a free chunk of vm
  91 * space during mmap's.
  92 */
  93#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
  94
  95
  96#define NUM_FPU_REGS    32
  97
  98#ifdef CONFIG_CPU_HAS_MSA
  99# define FPU_REG_WIDTH  128
 100#else
 101# define FPU_REG_WIDTH  64
 102#endif
 103
 104union fpureg {
 105        __u32   val32[FPU_REG_WIDTH / 32];
 106        __u64   val64[FPU_REG_WIDTH / 64];
 107};
 108
 109#ifdef CONFIG_CPU_LITTLE_ENDIAN
 110# define FPR_IDX(width, idx)    (idx)
 111#else
 112# define FPR_IDX(width, idx)    ((idx) ^ ((64 / (width)) - 1))
 113#endif
 114
 115#define BUILD_FPR_ACCESS(width) \
 116static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx)  \
 117{                                                                       \
 118        return fpr->val##width[FPR_IDX(width, idx)];                    \
 119}                                                                       \
 120                                                                        \
 121static inline void set_fpr##width(union fpureg *fpr, unsigned idx,      \
 122                                  u##width val)                         \
 123{                                                                       \
 124        fpr->val##width[FPR_IDX(width, idx)] = val;                     \
 125}
 126
 127BUILD_FPR_ACCESS(32)
 128BUILD_FPR_ACCESS(64)
 129
 130/*
 131 * It would be nice to add some more fields for emulator statistics,
 132 * the additional information is private to the FPU emulator for now.
 133 * See arch/mips/include/asm/fpu_emulator.h.
 134 */
 135
 136struct mips_fpu_struct {
 137        union fpureg    fpr[NUM_FPU_REGS];
 138        unsigned int    fcr31;
 139        unsigned int    msacsr;
 140};
 141
 142#define NUM_DSP_REGS   6
 143
 144typedef __u32 dspreg_t;
 145
 146struct mips_dsp_state {
 147        dspreg_t        dspr[NUM_DSP_REGS];
 148        unsigned int    dspcontrol;
 149};
 150
 151#define INIT_CPUMASK { \
 152        {0,} \
 153}
 154
 155struct mips3264_watch_reg_state {
 156        /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
 157           64 bit kernel.  We use unsigned long as it has the same
 158           property. */
 159        unsigned long watchlo[NUM_WATCH_REGS];
 160        /* Only the mask and IRW bits from watchhi. */
 161        u16 watchhi[NUM_WATCH_REGS];
 162};
 163
 164union mips_watch_reg_state {
 165        struct mips3264_watch_reg_state mips3264;
 166};
 167
 168#if defined(CONFIG_CPU_CAVIUM_OCTEON)
 169
 170struct octeon_cop2_state {
 171        /* DMFC2 rt, 0x0201 */
 172        unsigned long   cop2_crc_iv;
 173        /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
 174        unsigned long   cop2_crc_length;
 175        /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
 176        unsigned long   cop2_crc_poly;
 177        /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
 178        unsigned long   cop2_llm_dat[2];
 179       /* DMFC2 rt, 0x0084 */
 180        unsigned long   cop2_3des_iv;
 181        /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
 182        unsigned long   cop2_3des_key[3];
 183        /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
 184        unsigned long   cop2_3des_result;
 185        /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
 186        unsigned long   cop2_aes_inp0;
 187        /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
 188        unsigned long   cop2_aes_iv[2];
 189        /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
 190         * rt, 0x0107 */
 191        unsigned long   cop2_aes_key[4];
 192        /* DMFC2 rt, 0x0110 */
 193        unsigned long   cop2_aes_keylen;
 194        /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
 195        unsigned long   cop2_aes_result[2];
 196        /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
 197         * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
 198         * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
 199         * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
 200         * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
 201        unsigned long   cop2_hsh_datw[15];
 202        /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
 203         * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
 204         * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
 205        unsigned long   cop2_hsh_ivw[8];
 206        /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
 207        unsigned long   cop2_gfm_mult[2];
 208        /* DMFC2 rt, 0x025E - Pass2 */
 209        unsigned long   cop2_gfm_poly;
 210        /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
 211        unsigned long   cop2_gfm_result[2];
 212        /* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
 213        unsigned long   cop2_sha3[2];
 214};
 215#define COP2_INIT                                               \
 216        .cp2                    = {0,},
 217
 218struct octeon_cvmseg_state {
 219        unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
 220                            [cpu_dcache_line_size() / sizeof(unsigned long)];
 221};
 222
 223#elif defined(CONFIG_CPU_XLP)
 224struct nlm_cop2_state {
 225        u64     rx[4];
 226        u64     tx[4];
 227        u32     tx_msg_status;
 228        u32     rx_msg_status;
 229};
 230
 231#define COP2_INIT                                               \
 232        .cp2                    = {{0}, {0}, 0, 0},
 233#else
 234#define COP2_INIT
 235#endif
 236
 237typedef struct {
 238        unsigned long seg;
 239} mm_segment_t;
 240
 241#ifdef CONFIG_CPU_HAS_MSA
 242# define ARCH_MIN_TASKALIGN     16
 243# define FPU_ALIGN              __aligned(16)
 244#else
 245# define ARCH_MIN_TASKALIGN     8
 246# define FPU_ALIGN
 247#endif
 248
 249struct mips_abi;
 250
 251/*
 252 * If you change thread_struct remember to change the #defines below too!
 253 */
 254struct thread_struct {
 255        /* Saved main processor registers. */
 256        unsigned long reg16;
 257        unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
 258        unsigned long reg29, reg30, reg31;
 259
 260        /* Saved cp0 stuff. */
 261        unsigned long cp0_status;
 262
 263        /* Saved fpu/fpu emulator stuff. */
 264        struct mips_fpu_struct fpu FPU_ALIGN;
 265        /* Assigned branch delay slot 'emulation' frame */
 266        atomic_t bd_emu_frame;
 267        /* PC of the branch from a branch delay slot 'emulation' */
 268        unsigned long bd_emu_branch_pc;
 269        /* PC to continue from following a branch delay slot 'emulation' */
 270        unsigned long bd_emu_cont_pc;
 271#ifdef CONFIG_MIPS_MT_FPAFF
 272        /* Emulated instruction count */
 273        unsigned long emulated_fp;
 274        /* Saved per-thread scheduler affinity mask */
 275        cpumask_t user_cpus_allowed;
 276#endif /* CONFIG_MIPS_MT_FPAFF */
 277
 278        /* Saved state of the DSP ASE, if available. */
 279        struct mips_dsp_state dsp;
 280
 281        /* Saved watch register state, if available. */
 282        union mips_watch_reg_state watch;
 283
 284        /* Other stuff associated with the thread. */
 285        unsigned long cp0_badvaddr;     /* Last user fault */
 286        unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
 287        unsigned long error_code;
 288        unsigned long trap_nr;
 289#ifdef CONFIG_CPU_CAVIUM_OCTEON
 290        struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
 291        struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
 292#endif
 293#ifdef CONFIG_CPU_XLP
 294        struct nlm_cop2_state cp2;
 295#endif
 296        struct mips_abi *abi;
 297};
 298
 299#ifdef CONFIG_MIPS_MT_FPAFF
 300#define FPAFF_INIT                                              \
 301        .emulated_fp                    = 0,                    \
 302        .user_cpus_allowed              = INIT_CPUMASK,
 303#else
 304#define FPAFF_INIT
 305#endif /* CONFIG_MIPS_MT_FPAFF */
 306
 307#define INIT_THREAD  {                                          \
 308        /*                                                      \
 309         * Saved main processor registers                       \
 310         */                                                     \
 311        .reg16                  = 0,                            \
 312        .reg17                  = 0,                            \
 313        .reg18                  = 0,                            \
 314        .reg19                  = 0,                            \
 315        .reg20                  = 0,                            \
 316        .reg21                  = 0,                            \
 317        .reg22                  = 0,                            \
 318        .reg23                  = 0,                            \
 319        .reg29                  = 0,                            \
 320        .reg30                  = 0,                            \
 321        .reg31                  = 0,                            \
 322        /*                                                      \
 323         * Saved cp0 stuff                                      \
 324         */                                                     \
 325        .cp0_status             = 0,                            \
 326        /*                                                      \
 327         * Saved FPU/FPU emulator stuff                         \
 328         */                                                     \
 329        .fpu                    = {                             \
 330                .fpr            = {{{0,},},},                   \
 331                .fcr31          = 0,                            \
 332                .msacsr         = 0,                            \
 333        },                                                      \
 334        /*                                                      \
 335         * FPU affinity state (null if not FPAFF)               \
 336         */                                                     \
 337        FPAFF_INIT                                              \
 338        /* Delay slot emulation */                              \
 339        .bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE),          \
 340        .bd_emu_branch_pc = 0,                                  \
 341        .bd_emu_cont_pc = 0,                                    \
 342        /*                                                      \
 343         * Saved DSP stuff                                      \
 344         */                                                     \
 345        .dsp                    = {                             \
 346                .dspr           = {0, },                        \
 347                .dspcontrol     = 0,                            \
 348        },                                                      \
 349        /*                                                      \
 350         * saved watch register stuff                           \
 351         */                                                     \
 352        .watch = {{{0,},},},                                    \
 353        /*                                                      \
 354         * Other stuff associated with the process              \
 355         */                                                     \
 356        .cp0_badvaddr           = 0,                            \
 357        .cp0_baduaddr           = 0,                            \
 358        .error_code             = 0,                            \
 359        .trap_nr                = 0,                            \
 360        /*                                                      \
 361         * Platform specific cop2 registers(null if no COP2)    \
 362         */                                                     \
 363        COP2_INIT                                               \
 364}
 365
 366struct task_struct;
 367
 368/* Free all resources held by a thread. */
 369#define release_thread(thread) do { } while(0)
 370
 371extern unsigned long thread_saved_pc(struct task_struct *tsk);
 372
 373/*
 374 * Do necessary setup to start up a newly executed thread.
 375 */
 376extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
 377
 378static inline void flush_thread(void)
 379{
 380}
 381
 382unsigned long get_wchan(struct task_struct *p);
 383
 384#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
 385                         THREAD_SIZE - 32 - sizeof(struct pt_regs))
 386#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
 387#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
 388#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
 389#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
 390
 391#define cpu_relax()     barrier()
 392#define cpu_relax_lowlatency() cpu_relax()
 393
 394/*
 395 * Return_address is a replacement for __builtin_return_address(count)
 396 * which on certain architectures cannot reasonably be implemented in GCC
 397 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
 398 * Note that __builtin_return_address(x>=1) is forbidden because GCC
 399 * aborts compilation on some CPUs.  It's simply not possible to unwind
 400 * some CPU's stackframes.
 401 *
 402 * __builtin_return_address works only for non-leaf functions.  We avoid the
 403 * overhead of a function call by forcing the compiler to save the return
 404 * address register on the stack.
 405 */
 406#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
 407
 408#ifdef CONFIG_CPU_HAS_PREFETCH
 409
 410#define ARCH_HAS_PREFETCH
 411#define prefetch(x) __builtin_prefetch((x), 0, 1)
 412
 413#define ARCH_HAS_PREFETCHW
 414#define prefetchw(x) __builtin_prefetch((x), 1, 1)
 415
 416#endif
 417
 418/*
 419 * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options
 420 * to the prctl syscall.
 421 */
 422extern int mips_get_process_fp_mode(struct task_struct *task);
 423extern int mips_set_process_fp_mode(struct task_struct *task,
 424                                    unsigned int value);
 425
 426#define GET_FP_MODE(task)               mips_get_process_fp_mode(task)
 427#define SET_FP_MODE(task,value)         mips_set_process_fp_mode(task, value)
 428
 429#endif /* _ASM_PROCESSOR_H */
 430