1#ifndef _SPARC64_CHMCTRL_H 2#define _SPARC64_CHMCTRL_H 3 4/* Cheetah memory controller programmable registers. */ 5#define CHMCTRL_TCTRL1 0x00 /* Memory Timing Control I */ 6#define CHMCTRL_TCTRL2 0x08 /* Memory Timing Control II */ 7#define CHMCTRL_TCTRL3 0x38 /* Memory Timing Control III */ 8#define CHMCTRL_TCTRL4 0x40 /* Memory Timing Control IV */ 9#define CHMCTRL_DECODE1 0x10 /* Memory Address Decode I */ 10#define CHMCTRL_DECODE2 0x18 /* Memory Address Decode II */ 11#define CHMCTRL_DECODE3 0x20 /* Memory Address Decode III */ 12#define CHMCTRL_DECODE4 0x28 /* Memory Address Decode IV */ 13#define CHMCTRL_MACTRL 0x30 /* Memory Address Control */ 14 15/* Memory Timing Control I */ 16#define TCTRL1_SDRAMCTL_DLY 0xf000000000000000UL 17#define TCTRL1_SDRAMCTL_DLY_SHIFT 60 18#define TCTRL1_SDRAMCLK_DLY 0x0e00000000000000UL 19#define TCTRL1_SDRAMCLK_DLY_SHIFT 57 20#define TCTRL1_R 0x0100000000000000UL 21#define TCTRL1_R_SHIFT 56 22#define TCTRL1_AUTORFR_CYCLE 0x00fe000000000000UL 23#define TCTRL1_AUTORFR_CYCLE_SHIFT 49 24#define TCTRL1_RD_WAIT 0x0001f00000000000UL 25#define TCTRL1_RD_WAIT_SHIFT 44 26#define TCTRL1_PC_CYCLE 0x00000fc000000000UL 27#define TCTRL1_PC_CYCLE_SHIFT 38 28#define TCTRL1_WR_MORE_RAS_PW 0x0000003f00000000UL 29#define TCTRL1_WR_MORE_RAS_PW_SHIFT 32 30#define TCTRL1_RD_MORE_RAW_PW 0x00000000fc000000UL 31#define TCTRL1_RD_MORE_RAS_PW_SHIFT 26 32#define TCTRL1_ACT_WR_DLY 0x0000000003f00000UL 33#define TCTRL1_ACT_WR_DLY_SHIFT 20 34#define TCTRL1_ACT_RD_DLY 0x00000000000fc000UL 35#define TCTRL1_ACT_RD_DLY_SHIFT 14 36#define TCTRL1_BANK_PRESENT 0x0000000000003000UL 37#define TCTRL1_BANK_PRESENT_SHIFT 12 38#define TCTRL1_RFR_INT 0x0000000000000ff8UL 39#define TCTRL1_RFR_INT_SHIFT 3 40#define TCTRL1_SET_MODE_REG 0x0000000000000004UL 41#define TCTRL1_SET_MODE_REG_SHIFT 2 42#define TCTRL1_RFR_ENABLE 0x0000000000000002UL 43#define TCTRL1_RFR_ENABLE_SHIFT 1 44#define TCTRL1_PRECHG_ALL 0x0000000000000001UL 45#define TCTRL1_PRECHG_ALL_SHIFT 0 46 47/* Memory Timing Control II */ 48#define TCTRL2_WR_MSEL_DLY 0xfc00000000000000UL 49#define TCTRL2_WR_MSEL_DLY_SHIFT 58 50#define TCTRL2_RD_MSEL_DLY 0x03f0000000000000UL 51#define TCTRL2_RD_MSEL_DLY_SHIFT 52 52#define TCTRL2_WRDATA_THLD 0x000c000000000000UL 53#define TCTRL2_WRDATA_THLD_SHIFT 50 54#define TCTRL2_RDWR_RD_TI_DLY 0x0003f00000000000UL 55#define TCTRL2_RDWR_RD_TI_DLY_SHIFT 44 56#define TCTRL2_AUTOPRECHG_ENBL 0x0000080000000000UL 57#define TCTRL2_AUTOPRECHG_ENBL_SHIFT 43 58#define TCTRL2_RDWR_PI_MORE_DLY 0x000007c000000000UL 59#define TCTRL2_RDWR_PI_MORE_DLY_SHIFT 38 60#define TCTRL2_RDWR_1_DLY 0x0000003f00000000UL 61#define TCTRL2_RDWR_1_DLY_SHIFT 32 62#define TCTRL2_WRWR_PI_MORE_DLY 0x00000000f8000000UL 63#define TCTRL2_WRWR_PI_MORE_DLY_SHIFT 27 64#define TCTRL2_WRWR_1_DLY 0x0000000007e00000UL 65#define TCTRL2_WRWR_1_DLY_SHIFT 21 66#define TCTRL2_RDWR_RD_PI_MORE_DLY 0x00000000001f0000UL 67#define TCTRL2_RDWR_RD_PI_MORE_DLY_SHIFT 16 68#define TCTRL2_R 0x0000000000008000UL 69#define TCTRL2_R_SHIFT 15 70#define TCTRL2_SDRAM_MODE_REG_DATA 0x0000000000007fffUL 71#define TCTRL2_SDRAM_MODE_REG_DATA_SHIFT 0 72 73/* Memory Timing Control III */ 74#define TCTRL3_SDRAM_CTL_DLY 0xf000000000000000UL 75#define TCTRL3_SDRAM_CTL_DLY_SHIFT 60 76#define TCTRL3_SDRAM_CLK_DLY 0x0e00000000000000UL 77#define TCTRL3_SDRAM_CLK_DLY_SHIFT 57 78#define TCTRL3_R 0x0100000000000000UL 79#define TCTRL3_R_SHIFT 56 80#define TCTRL3_AUTO_RFR_CYCLE 0x00fe000000000000UL 81#define TCTRL3_AUTO_RFR_CYCLE_SHIFT 49 82#define TCTRL3_RD_WAIT 0x0001f00000000000UL 83#define TCTRL3_RD_WAIT_SHIFT 44 84#define TCTRL3_PC_CYCLE 0x00000fc000000000UL 85#define TCTRL3_PC_CYCLE_SHIFT 38 86#define TCTRL3_WR_MORE_RAW_PW 0x0000003f00000000UL 87#define TCTRL3_WR_MORE_RAW_PW_SHIFT 32 88#define TCTRL3_RD_MORE_RAW_PW 0x00000000fc000000UL 89#define TCTRL3_RD_MORE_RAW_PW_SHIFT 26 90#define TCTRL3_ACT_WR_DLY 0x0000000003f00000UL 91#define TCTRL3_ACT_WR_DLY_SHIFT 20 92#define TCTRL3_ACT_RD_DLY 0x00000000000fc000UL 93#define TCTRL3_ACT_RD_DLY_SHIFT 14 94#define TCTRL3_BANK_PRESENT 0x0000000000003000UL 95#define TCTRL3_BANK_PRESENT_SHIFT 12 96#define TCTRL3_RFR_INT 0x0000000000000ff8UL 97#define TCTRL3_RFR_INT_SHIFT 3 98#define TCTRL3_SET_MODE_REG 0x0000000000000004UL 99#define TCTRL3_SET_MODE_REG_SHIFT 2 100#define TCTRL3_RFR_ENABLE 0x0000000000000002UL 101#define TCTRL3_RFR_ENABLE_SHIFT 1 102#define TCTRL3_PRECHG_ALL 0x0000000000000001UL 103#define TCTRL3_PRECHG_ALL_SHIFT 0 104 105/* Memory Timing Control IV */ 106#define TCTRL4_WR_MSEL_DLY 0xfc00000000000000UL 107#define TCTRL4_WR_MSEL_DLY_SHIFT 58 108#define TCTRL4_RD_MSEL_DLY 0x03f0000000000000UL 109#define TCTRL4_RD_MSEL_DLY_SHIFT 52 110#define TCTRL4_WRDATA_THLD 0x000c000000000000UL 111#define TCTRL4_WRDATA_THLD_SHIFT 50 112#define TCTRL4_RDWR_RD_RI_DLY 0x0003f00000000000UL 113#define TCTRL4_RDWR_RD_RI_DLY_SHIFT 44 114#define TCTRL4_AUTO_PRECHG_ENBL 0x0000080000000000UL 115#define TCTRL4_AUTO_PRECHG_ENBL_SHIFT 43 116#define TCTRL4_RD_WR_PI_MORE_DLY 0x000007c000000000UL 117#define TCTRL4_RD_WR_PI_MORE_DLY_SHIFT 38 118#define TCTRL4_RD_WR_TI_DLY 0x0000003f00000000UL 119#define TCTRL4_RD_WR_TI_DLY_SHIFT 32 120#define TCTRL4_WR_WR_PI_MORE_DLY 0x00000000f8000000UL 121#define TCTRL4_WR_WR_PI_MORE_DLY_SHIFT 27 122#define TCTRL4_WR_WR_TI_DLY 0x0000000007e00000UL 123#define TCTRL4_WR_WR_TI_DLY_SHIFT 21 124#define TCTRL4_RDWR_RD_PI_MORE_DLY 0x00000000001f000UL0 125#define TCTRL4_RDWR_RD_PI_MORE_DLY_SHIFT 16 126#define TCTRL4_R 0x0000000000008000UL 127#define TCTRL4_R_SHIFT 15 128#define TCTRL4_SDRAM_MODE_REG_DATA 0x0000000000007fffUL 129#define TCTRL4_SDRAM_MODE_REG_DATA_SHIFT 0 130 131/* All 4 memory address decoding registers have the 132 * same layout. 133 */ 134#define MEM_DECODE_VALID 0x8000000000000000UL /* Valid */ 135#define MEM_DECODE_VALID_SHIFT 63 136#define MEM_DECODE_UK 0x001ffe0000000000UL /* Upper mask */ 137#define MEM_DECODE_UK_SHIFT 41 138#define MEM_DECODE_UM 0x0000001ffff00000UL /* Upper match */ 139#define MEM_DECODE_UM_SHIFT 20 140#define MEM_DECODE_LK 0x000000000003c000UL /* Lower mask */ 141#define MEM_DECODE_LK_SHIFT 14 142#define MEM_DECODE_LM 0x0000000000000f00UL /* Lower match */ 143#define MEM_DECODE_LM_SHIFT 8 144 145#define PA_UPPER_BITS 0x000007fffc000000UL 146#define PA_UPPER_BITS_SHIFT 26 147#define PA_LOWER_BITS 0x00000000000003c0UL 148#define PA_LOWER_BITS_SHIFT 6 149 150#define MACTRL_R0 0x8000000000000000UL 151#define MACTRL_R0_SHIFT 63 152#define MACTRL_ADDR_LE_PW 0x7000000000000000UL 153#define MACTRL_ADDR_LE_PW_SHIFT 60 154#define MACTRL_CMD_PW 0x0f00000000000000UL 155#define MACTRL_CMD_PW_SHIFT 56 156#define MACTRL_HALF_MODE_WR_MSEL_DLY 0x00fc000000000000UL 157#define MACTRL_HALF_MODE_WR_MSEL_DLY_SHIFT 50 158#define MACTRL_HALF_MODE_RD_MSEL_DLY 0x0003f00000000000UL 159#define MACTRL_HALF_MODE_RD_MSEL_DLY_SHIFT 44 160#define MACTRL_HALF_MODE_SDRAM_CTL_DLY 0x00000f0000000000UL 161#define MACTRL_HALF_MODE_SDRAM_CTL_DLY_SHIFT 40 162#define MACTRL_HALF_MODE_SDRAM_CLK_DLY 0x000000e000000000UL 163#define MACTRL_HALF_MODE_SDRAM_CLK_DLY_SHIFT 37 164#define MACTRL_R1 0x0000001000000000UL 165#define MACTRL_R1_SHIFT 36 166#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3 0x0000000f00000000UL 167#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3_SHIFT 32 168#define MACTRL_ENC_INTLV_B3 0x00000000f8000000UL 169#define MACTRL_ENC_INTLV_B3_SHIFT 27 170#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2 0x0000000007800000UL 171#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2_SHIFT 23 172#define MACTRL_ENC_INTLV_B2 0x00000000007c0000UL 173#define MACTRL_ENC_INTLV_B2_SHIFT 18 174#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1 0x000000000003c000UL 175#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1_SHIFT 14 176#define MACTRL_ENC_INTLV_B1 0x0000000000003e00UL 177#define MACTRL_ENC_INTLV_B1_SHIFT 9 178#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0 0x00000000000001e0UL 179#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0_SHIFT 5 180#define MACTRL_ENC_INTLV_B0 0x000000000000001fUL 181#define MACTRL_ENC_INTLV_B0_SHIFT 0 182 183#endif /* _SPARC64_CHMCTRL_H */ 184