1/* 2 * Copyright 2012 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 */ 14 15/** 16 * Interface definitions for the trio driver. 17 */ 18 19#ifndef _SYS_HV_DRV_TRIO_INTF_H 20#define _SYS_HV_DRV_TRIO_INTF_H 21 22#include <arch/trio.h> 23 24/** The vendor ID for all Tilera processors. */ 25#define TILERA_VENDOR_ID 0x1a41 26 27/** The device ID for the Gx36 processor. */ 28#define TILERA_GX36_DEV_ID 0x0200 29 30/** Device ID for our internal bridge when running as RC. */ 31#define TILERA_GX36_RC_DEV_ID 0x2000 32 33/** Maximum number of TRIO interfaces. */ 34#define TILEGX_NUM_TRIO 2 35 36/** Gx36 has max 3 PCIe MACs per TRIO interface. */ 37#define TILEGX_TRIO_PCIES 3 38 39/** Specify port properties for a PCIe MAC. */ 40struct pcie_port_property 41{ 42 /** If true, the link can be configured in PCIe root complex mode. */ 43 uint8_t allow_rc: 1; 44 45 /** If true, the link can be configured in PCIe endpoint mode. */ 46 uint8_t allow_ep: 1; 47 48 /** If true, the link can be configured in StreamIO mode. */ 49 uint8_t allow_sio: 1; 50 51 /** If true, the link is allowed to support 1-lane operation. Software 52 * will not consider it an error if the link comes up as a x1 link. */ 53 uint8_t allow_x1: 1; 54 55 /** If true, the link is allowed to support 2-lane operation. Software 56 * will not consider it an error if the link comes up as a x2 link. */ 57 uint8_t allow_x2: 1; 58 59 /** If true, the link is allowed to support 4-lane operation. Software 60 * will not consider it an error if the link comes up as a x4 link. */ 61 uint8_t allow_x4: 1; 62 63 /** If true, the link is allowed to support 8-lane operation. Software 64 * will not consider it an error if the link comes up as a x8 link. */ 65 uint8_t allow_x8: 1; 66 67 /** If true, this link is connected to a device which may or may not 68 * be present. */ 69 uint8_t removable: 1; 70 71}; 72 73/** Configurations can be issued to configure a char stream interrupt. */ 74typedef enum pcie_stream_intr_config_sel_e 75{ 76 /** Interrupt configuration for memory map regions. */ 77 MEM_MAP_SEL, 78 79 /** Interrupt configuration for push DMAs. */ 80 PUSH_DMA_SEL, 81 82 /** Interrupt configuration for pull DMAs. */ 83 PULL_DMA_SEL, 84} 85pcie_stream_intr_config_sel_t; 86 87 88/** The mmap file offset (PA) of the TRIO config region. */ 89#define HV_TRIO_CONFIG_OFFSET \ 90 ((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_CFG << \ 91 TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) 92 93/** The maximum size of the TRIO config region. */ 94#define HV_TRIO_CONFIG_SIZE \ 95 (1ULL << TRIO_CFG_REGION_ADDR__REGION_SHIFT) 96 97/** Size of the config region mapped into client. We can't use 98 * TRIO_MMIO_ADDRESS_SPACE__OFFSET_WIDTH because it 99 * will require the kernel to allocate 4GB VA space 100 * from the VMALLOC region which has a total range 101 * of 4GB. 102 */ 103#define HV_TRIO_CONFIG_IOREMAP_SIZE \ 104 ((uint64_t) 1 << TRIO_CFG_REGION_ADDR__PROT_SHIFT) 105 106/** The mmap file offset (PA) of a scatter queue region. */ 107#define HV_TRIO_SQ_OFFSET(queue) \ 108 (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_MAP_SQ << \ 109 TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \ 110 ((queue) << TRIO_MAP_SQ_REGION_ADDR__SQ_SEL_SHIFT)) 111 112/** The maximum size of a scatter queue region. */ 113#define HV_TRIO_SQ_SIZE \ 114 (1ULL << TRIO_MAP_SQ_REGION_ADDR__SQ_SEL_SHIFT) 115 116 117/** The "hardware MMIO region" of the first PIO region. */ 118#define HV_TRIO_FIRST_PIO_REGION 8 119 120/** The mmap file offset (PA) of a PIO region. */ 121#define HV_TRIO_PIO_OFFSET(region) \ 122 (((unsigned long long)(region) + HV_TRIO_FIRST_PIO_REGION) \ 123 << TRIO_PIO_REGIONS_ADDR__REGION_SHIFT) 124 125/** The maximum size of a PIO region. */ 126#define HV_TRIO_PIO_SIZE (1ULL << TRIO_PIO_REGIONS_ADDR__ADDR_WIDTH) 127 128 129/** The mmap file offset (PA) of a push DMA region. */ 130#define HV_TRIO_PUSH_DMA_OFFSET(ring) \ 131 (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_PUSH_DMA << \ 132 TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \ 133 ((ring) << TRIO_PUSH_DMA_REGION_ADDR__RING_SEL_SHIFT)) 134 135/** The mmap file offset (PA) of a pull DMA region. */ 136#define HV_TRIO_PULL_DMA_OFFSET(ring) \ 137 (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_PULL_DMA << \ 138 TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \ 139 ((ring) << TRIO_PULL_DMA_REGION_ADDR__RING_SEL_SHIFT)) 140 141/** The maximum size of a DMA region. */ 142#define HV_TRIO_DMA_REGION_SIZE \ 143 (1ULL << TRIO_PUSH_DMA_REGION_ADDR__RING_SEL_SHIFT) 144 145 146/** The mmap file offset (PA) of a Mem-Map interrupt region. */ 147#define HV_TRIO_MEM_MAP_INTR_OFFSET(map) \ 148 (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_MAP_MEM << \ 149 TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \ 150 ((map) << TRIO_MAP_MEM_REGION_ADDR__MAP_SEL_SHIFT)) 151 152/** The maximum size of a Mem-Map interrupt region. */ 153#define HV_TRIO_MEM_MAP_INTR_SIZE \ 154 (1ULL << TRIO_MAP_MEM_REGION_ADDR__MAP_SEL_SHIFT) 155 156 157/** A flag bit indicating a fixed resource allocation. */ 158#define HV_TRIO_ALLOC_FIXED 0x01 159 160/** TRIO requires that all mappings have 4kB aligned start addresses. */ 161#define HV_TRIO_PAGE_SHIFT 12 162 163/** TRIO requires that all mappings have 4kB aligned start addresses. */ 164#define HV_TRIO_PAGE_SIZE (1ull << HV_TRIO_PAGE_SHIFT) 165 166 167/* Specify all PCIe port properties for a TRIO. */ 168struct pcie_trio_ports_property 169{ 170 struct pcie_port_property ports[TILEGX_TRIO_PCIES]; 171 172 /** Set if this TRIO belongs to a Gx72 device. */ 173 uint8_t is_gx72; 174}; 175 176/* Flags indicating traffic class. */ 177#define HV_TRIO_FLAG_TC_SHIFT 4 178#define HV_TRIO_FLAG_TC_RMASK 0xf 179#define HV_TRIO_FLAG_TC(N) \ 180 ((((N) & HV_TRIO_FLAG_TC_RMASK) + 1) << HV_TRIO_FLAG_TC_SHIFT) 181 182/* Flags indicating virtual functions. */ 183#define HV_TRIO_FLAG_VFUNC_SHIFT 8 184#define HV_TRIO_FLAG_VFUNC_RMASK 0xff 185#define HV_TRIO_FLAG_VFUNC(N) \ 186 ((((N) & HV_TRIO_FLAG_VFUNC_RMASK) + 1) << HV_TRIO_FLAG_VFUNC_SHIFT) 187 188 189/* Flag indicating an ordered PIO region. */ 190#define HV_TRIO_PIO_FLAG_ORDERED (1 << 16) 191 192/* Flags indicating special types of PIO regions. */ 193#define HV_TRIO_PIO_FLAG_SPACE_SHIFT 17 194#define HV_TRIO_PIO_FLAG_SPACE_MASK (0x3 << HV_TRIO_PIO_FLAG_SPACE_SHIFT) 195#define HV_TRIO_PIO_FLAG_CONFIG_SPACE (0x1 << HV_TRIO_PIO_FLAG_SPACE_SHIFT) 196#define HV_TRIO_PIO_FLAG_IO_SPACE (0x2 << HV_TRIO_PIO_FLAG_SPACE_SHIFT) 197 198 199#endif /* _SYS_HV_DRV_TRIO_INTF_H */ 200