LXR linux/arch/xtensa/include/asm/cacheasm.h

   1/*
   2 * include/asm-xtensa/cacheasm.h
   3 *
   4 * This file is subject to the terms and conditions of the GNU General Public
   5 * License.  See the file "COPYING" in the main directory of this archive
   6 * for more details.
   7 *
   8 * Copyright (C) 2006 Tensilica Inc.
   9 */
  10
  11#include <asm/cache.h>
  12#include <asm/asmmacro.h>
  13#include <linux/stringify.h>
  14
  15/*
  16 * Define cache functions as macros here so that they can be used
  17 * by the kernel and boot loader. We should consider moving them to a
  18 * library that can be linked by both.
  19 *
  20 * Locking
  21 *
  22 *   ___unlock_dcache_all
  23 *   ___unlock_icache_all
  24 *
  25 * Flush and invaldating
  26 *
  27 *   ___flush_invalidate_dcache_{all|range|page}
  28 *   ___flush_dcache_{all|range|page}
  29 *   ___invalidate_dcache_{all|range|page}
  30 *   ___invalidate_icache_{all|range|page}
  31 *
  32 */
  33
  34        .macro  __loop_cache_all ar at insn size line_width
  35
  36        movi    \ar, 0
  37
  38        __loopi \ar, \at, \size, (4 << (\line_width))
  39        \insn   \ar, 0 << (\line_width)
  40        \insn   \ar, 1 << (\line_width)
  41        \insn   \ar, 2 << (\line_width)
  42        \insn   \ar, 3 << (\line_width)
  43        __endla \ar, \at, 4 << (\line_width)
  44
  45        .endm
  46
  47
  48        .macro  __loop_cache_range ar as at insn line_width
  49
  50        extui   \at, \ar, 0, \line_width
  51        add     \as, \as, \at
  52
  53        __loops \ar, \as, \at, \line_width
  54        \insn   \ar, 0
  55        __endla \ar, \at, (1 << (\line_width))
  56
  57        .endm
  58
  59
  60        .macro  __loop_cache_page ar at insn line_width
  61
  62        __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width)
  63        \insn   \ar, 0 << (\line_width)
  64        \insn   \ar, 1 << (\line_width)
  65        \insn   \ar, 2 << (\line_width)
  66        \insn   \ar, 3 << (\line_width)
  67        __endla \ar, \at, 4 << (\line_width)
  68
  69        .endm
  70
  71
  72        .macro  ___unlock_dcache_all ar at
  73
  74#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE
  75        __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
  76#endif
  77
  78        .endm
  79
  80
  81        .macro  ___unlock_icache_all ar at
  82
  83#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
  84        __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
  85#endif
  86
  87        .endm
  88
  89
  90        .macro  ___flush_invalidate_dcache_all ar at
  91
  92#if XCHAL_DCACHE_SIZE
  93        __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
  94#endif
  95
  96        .endm
  97
  98
  99        .macro  ___flush_dcache_all ar at
 100
 101#if XCHAL_DCACHE_SIZE
 102        __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
 103#endif
 104
 105        .endm
 106
 107
 108        .macro  ___invalidate_dcache_all ar at
 109
 110#if XCHAL_DCACHE_SIZE
 111        __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
 112                         XCHAL_DCACHE_LINEWIDTH
 113#endif
 114
 115        .endm
 116
 117
 118        .macro  ___invalidate_icache_all ar at
 119
 120#if XCHAL_ICACHE_SIZE
 121        __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
 122                         XCHAL_ICACHE_LINEWIDTH
 123#endif
 124
 125        .endm
 126
 127
 128
 129        .macro  ___flush_invalidate_dcache_range ar as at
 130
 131#if XCHAL_DCACHE_SIZE
 132        __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
 133#endif
 134
 135        .endm
 136
 137
 138        .macro  ___flush_dcache_range ar as at
 139
 140#if XCHAL_DCACHE_SIZE
 141        __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
 142#endif
 143
 144        .endm
 145
 146
 147        .macro  ___invalidate_dcache_range ar as at
 148
 149#if XCHAL_DCACHE_SIZE
 150        __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
 151#endif
 152
 153        .endm
 154
 155
 156        .macro  ___invalidate_icache_range ar as at
 157
 158#if XCHAL_ICACHE_SIZE
 159        __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
 160#endif
 161
 162        .endm
 163
 164
 165
 166        .macro  ___flush_invalidate_dcache_page ar as
 167
 168#if XCHAL_DCACHE_SIZE
 169        __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
 170#endif
 171
 172        .endm
 173
 174
 175        .macro ___flush_dcache_page ar as
 176
 177#if XCHAL_DCACHE_SIZE
 178        __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
 179#endif
 180
 181        .endm
 182
 183
 184        .macro  ___invalidate_dcache_page ar as
 185
 186#if XCHAL_DCACHE_SIZE
 187        __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
 188#endif
 189
 190        .endm
 191
 192
 193        .macro  ___invalidate_icache_page ar as
 194
 195#if XCHAL_ICACHE_SIZE
 196        __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
 197#endif
 198
 199        .endm
 200