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13#include <linux/clk-provider.h>
14#include <linux/delay.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <linux/jiffies.h>
18#include <linux/err.h>
19#include "clk.h"
20
21#define PLL_NUM_OFFSET 0x10
22#define PLL_DENOM_OFFSET 0x20
23
24#define BM_PLL_POWER (0x1 << 12)
25#define BM_PLL_LOCK (0x1 << 31)
26#define IMX7_ENET_PLL_POWER (0x1 << 5)
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38
39
40struct clk_pllv3 {
41 struct clk_hw hw;
42 void __iomem *base;
43 u32 power_bit;
44 bool powerup_set;
45 u32 div_mask;
46 u32 div_shift;
47 unsigned long ref_clock;
48};
49
50#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
51
52static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
53{
54 unsigned long timeout = jiffies + msecs_to_jiffies(10);
55 u32 val = readl_relaxed(pll->base) & pll->power_bit;
56
57
58 if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
59 return 0;
60
61
62 do {
63 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
64 break;
65 if (time_after(jiffies, timeout))
66 break;
67 usleep_range(50, 500);
68 } while (1);
69
70 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
71}
72
73static int clk_pllv3_prepare(struct clk_hw *hw)
74{
75 struct clk_pllv3 *pll = to_clk_pllv3(hw);
76 u32 val;
77
78 val = readl_relaxed(pll->base);
79 if (pll->powerup_set)
80 val |= pll->power_bit;
81 else
82 val &= ~pll->power_bit;
83 writel_relaxed(val, pll->base);
84
85 return clk_pllv3_wait_lock(pll);
86}
87
88static void clk_pllv3_unprepare(struct clk_hw *hw)
89{
90 struct clk_pllv3 *pll = to_clk_pllv3(hw);
91 u32 val;
92
93 val = readl_relaxed(pll->base);
94 if (pll->powerup_set)
95 val &= ~pll->power_bit;
96 else
97 val |= pll->power_bit;
98 writel_relaxed(val, pll->base);
99}
100
101static int clk_pllv3_is_prepared(struct clk_hw *hw)
102{
103 struct clk_pllv3 *pll = to_clk_pllv3(hw);
104
105 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
106 return 1;
107
108 return 0;
109}
110
111static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
112 unsigned long parent_rate)
113{
114 struct clk_pllv3 *pll = to_clk_pllv3(hw);
115 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
116
117 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
118}
119
120static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
121 unsigned long *prate)
122{
123 unsigned long parent_rate = *prate;
124
125 return (rate >= parent_rate * 22) ? parent_rate * 22 :
126 parent_rate * 20;
127}
128
129static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
130 unsigned long parent_rate)
131{
132 struct clk_pllv3 *pll = to_clk_pllv3(hw);
133 u32 val, div;
134
135 if (rate == parent_rate * 22)
136 div = 1;
137 else if (rate == parent_rate * 20)
138 div = 0;
139 else
140 return -EINVAL;
141
142 val = readl_relaxed(pll->base);
143 val &= ~(pll->div_mask << pll->div_shift);
144 val |= (div << pll->div_shift);
145 writel_relaxed(val, pll->base);
146
147 return clk_pllv3_wait_lock(pll);
148}
149
150static const struct clk_ops clk_pllv3_ops = {
151 .prepare = clk_pllv3_prepare,
152 .unprepare = clk_pllv3_unprepare,
153 .is_prepared = clk_pllv3_is_prepared,
154 .recalc_rate = clk_pllv3_recalc_rate,
155 .round_rate = clk_pllv3_round_rate,
156 .set_rate = clk_pllv3_set_rate,
157};
158
159static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
160 unsigned long parent_rate)
161{
162 struct clk_pllv3 *pll = to_clk_pllv3(hw);
163 u32 div = readl_relaxed(pll->base) & pll->div_mask;
164
165 return parent_rate * div / 2;
166}
167
168static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
169 unsigned long *prate)
170{
171 unsigned long parent_rate = *prate;
172 unsigned long min_rate = parent_rate * 54 / 2;
173 unsigned long max_rate = parent_rate * 108 / 2;
174 u32 div;
175
176 if (rate > max_rate)
177 rate = max_rate;
178 else if (rate < min_rate)
179 rate = min_rate;
180 div = rate * 2 / parent_rate;
181
182 return parent_rate * div / 2;
183}
184
185static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
186 unsigned long parent_rate)
187{
188 struct clk_pllv3 *pll = to_clk_pllv3(hw);
189 unsigned long min_rate = parent_rate * 54 / 2;
190 unsigned long max_rate = parent_rate * 108 / 2;
191 u32 val, div;
192
193 if (rate < min_rate || rate > max_rate)
194 return -EINVAL;
195
196 div = rate * 2 / parent_rate;
197 val = readl_relaxed(pll->base);
198 val &= ~pll->div_mask;
199 val |= div;
200 writel_relaxed(val, pll->base);
201
202 return clk_pllv3_wait_lock(pll);
203}
204
205static const struct clk_ops clk_pllv3_sys_ops = {
206 .prepare = clk_pllv3_prepare,
207 .unprepare = clk_pllv3_unprepare,
208 .is_prepared = clk_pllv3_is_prepared,
209 .recalc_rate = clk_pllv3_sys_recalc_rate,
210 .round_rate = clk_pllv3_sys_round_rate,
211 .set_rate = clk_pllv3_sys_set_rate,
212};
213
214static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
215 unsigned long parent_rate)
216{
217 struct clk_pllv3 *pll = to_clk_pllv3(hw);
218 u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
219 u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
220 u32 div = readl_relaxed(pll->base) & pll->div_mask;
221 u64 temp64 = (u64)parent_rate;
222
223 temp64 *= mfn;
224 do_div(temp64, mfd);
225
226 return parent_rate * div + (unsigned long)temp64;
227}
228
229static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
230 unsigned long *prate)
231{
232 unsigned long parent_rate = *prate;
233 unsigned long min_rate = parent_rate * 27;
234 unsigned long max_rate = parent_rate * 54;
235 u32 div;
236 u32 mfn, mfd = 1000000;
237 u64 temp64;
238
239 if (rate > max_rate)
240 rate = max_rate;
241 else if (rate < min_rate)
242 rate = min_rate;
243
244 div = rate / parent_rate;
245 temp64 = (u64) (rate - div * parent_rate);
246 temp64 *= mfd;
247 do_div(temp64, parent_rate);
248 mfn = temp64;
249
250 temp64 = (u64)parent_rate;
251 temp64 *= mfn;
252 do_div(temp64, mfd);
253
254 return parent_rate * div + (unsigned long)temp64;
255}
256
257static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
258 unsigned long parent_rate)
259{
260 struct clk_pllv3 *pll = to_clk_pllv3(hw);
261 unsigned long min_rate = parent_rate * 27;
262 unsigned long max_rate = parent_rate * 54;
263 u32 val, div;
264 u32 mfn, mfd = 1000000;
265 u64 temp64;
266
267 if (rate < min_rate || rate > max_rate)
268 return -EINVAL;
269
270 div = rate / parent_rate;
271 temp64 = (u64) (rate - div * parent_rate);
272 temp64 *= mfd;
273 do_div(temp64, parent_rate);
274 mfn = temp64;
275
276 val = readl_relaxed(pll->base);
277 val &= ~pll->div_mask;
278 val |= div;
279 writel_relaxed(val, pll->base);
280 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
281 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
282
283 return clk_pllv3_wait_lock(pll);
284}
285
286static const struct clk_ops clk_pllv3_av_ops = {
287 .prepare = clk_pllv3_prepare,
288 .unprepare = clk_pllv3_unprepare,
289 .is_prepared = clk_pllv3_is_prepared,
290 .recalc_rate = clk_pllv3_av_recalc_rate,
291 .round_rate = clk_pllv3_av_round_rate,
292 .set_rate = clk_pllv3_av_set_rate,
293};
294
295static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
296 unsigned long parent_rate)
297{
298 struct clk_pllv3 *pll = to_clk_pllv3(hw);
299
300 return pll->ref_clock;
301}
302
303static const struct clk_ops clk_pllv3_enet_ops = {
304 .prepare = clk_pllv3_prepare,
305 .unprepare = clk_pllv3_unprepare,
306 .is_prepared = clk_pllv3_is_prepared,
307 .recalc_rate = clk_pllv3_enet_recalc_rate,
308};
309
310struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
311 const char *parent_name, void __iomem *base,
312 u32 div_mask)
313{
314 struct clk_pllv3 *pll;
315 const struct clk_ops *ops;
316 struct clk *clk;
317 struct clk_init_data init;
318
319 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
320 if (!pll)
321 return ERR_PTR(-ENOMEM);
322
323 pll->power_bit = BM_PLL_POWER;
324
325 switch (type) {
326 case IMX_PLLV3_SYS:
327 ops = &clk_pllv3_sys_ops;
328 break;
329 case IMX_PLLV3_USB_VF610:
330 pll->div_shift = 1;
331 case IMX_PLLV3_USB:
332 ops = &clk_pllv3_ops;
333 pll->powerup_set = true;
334 break;
335 case IMX_PLLV3_AV:
336 ops = &clk_pllv3_av_ops;
337 break;
338 case IMX_PLLV3_ENET_IMX7:
339 pll->power_bit = IMX7_ENET_PLL_POWER;
340 pll->ref_clock = 1000000000;
341 ops = &clk_pllv3_enet_ops;
342 break;
343 case IMX_PLLV3_ENET:
344 pll->ref_clock = 500000000;
345 ops = &clk_pllv3_enet_ops;
346 break;
347 default:
348 ops = &clk_pllv3_ops;
349 }
350 pll->base = base;
351 pll->div_mask = div_mask;
352
353 init.name = name;
354 init.ops = ops;
355 init.flags = 0;
356 init.parent_names = &parent_name;
357 init.num_parents = 1;
358
359 pll->hw.init = &init;
360
361 clk = clk_register(NULL, &pll->hw);
362 if (IS_ERR(clk))
363 kfree(pll);
364
365 return clk;
366}
367
