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10#include <linux/of.h>
11#include <linux/of_address.h>
12#include <linux/clk-provider.h>
13#include <linux/mfd/dbx500-prcmu.h>
14#include "clk.h"
15
16#define PRCC_NUM_PERIPH_CLUSTERS 6
17#define PRCC_PERIPHS_PER_CLUSTER 32
18
19static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
20static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
21static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22
23#define PRCC_SHOW(clk, base, bit) \
24 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
25#define PRCC_PCLK_STORE(clk, base, bit) \
26 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
27#define PRCC_KCLK_STORE(clk, base, bit) \
28 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
29
30static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec,
31 void *data)
32{
33 struct clk **clk_data = data;
34 unsigned int base, bit;
35
36 if (clkspec->args_count != 2)
37 return ERR_PTR(-EINVAL);
38
39 base = clkspec->args[0];
40 bit = clkspec->args[1];
41
42 if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) {
43 pr_err("%s: invalid PRCC base %d\n", __func__, base);
44 return ERR_PTR(-EINVAL);
45 }
46
47 return PRCC_SHOW(clk_data, base, bit);
48}
49
50
51enum clkrst_index {
52 CLKRST1_INDEX = 0,
53 CLKRST2_INDEX,
54 CLKRST3_INDEX,
55 CLKRST5_INDEX,
56 CLKRST6_INDEX,
57 CLKRST_MAX,
58};
59
60static void u8500_clk_init(struct device_node *np)
61{
62 struct prcmu_fw_version *fw_version;
63 struct device_node *child = NULL;
64 const char *sgaclk_parent = NULL;
65 struct clk *clk, *rtc_clk, *twd_clk;
66 u32 bases[CLKRST_MAX];
67 int i;
68
69 for (i = 0; i < ARRAY_SIZE(bases); i++) {
70 struct resource r;
71
72 if (of_address_to_resource(np, i, &r))
73
74 pr_err("failed to get CLKRST %d base address\n",
75 i + 1);
76 bases[i] = r.start;
77 }
78
79
80 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
81 CLK_IGNORE_UNUSED);
82 prcmu_clk[PRCMU_PLLSOC0] = clk;
83
84 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
85 CLK_IGNORE_UNUSED);
86 prcmu_clk[PRCMU_PLLSOC1] = clk;
87
88 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
89 CLK_IGNORE_UNUSED);
90 prcmu_clk[PRCMU_PLLDDR] = clk;
91
92
93
94 rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
95 CLK_IGNORE_UNUSED,
96 32768);
97
98
99 fw_version = prcmu_get_fw_version();
100 if (fw_version != NULL) {
101 switch (fw_version->project) {
102 case PRCMU_FW_PROJECT_U8500_C2:
103 case PRCMU_FW_PROJECT_U8520:
104 case PRCMU_FW_PROJECT_U8420:
105 sgaclk_parent = "soc0_pll";
106 break;
107 default:
108 break;
109 }
110 }
111
112 if (sgaclk_parent)
113 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
114 PRCMU_SGACLK, 0);
115 else
116 clk = clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, 0);
117 prcmu_clk[PRCMU_SGACLK] = clk;
118
119 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0);
120 prcmu_clk[PRCMU_UARTCLK] = clk;
121
122 clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, 0);
123 prcmu_clk[PRCMU_MSP02CLK] = clk;
124
125 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0);
126 prcmu_clk[PRCMU_MSP1CLK] = clk;
127
128 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0);
129 prcmu_clk[PRCMU_I2CCLK] = clk;
130
131 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0);
132 prcmu_clk[PRCMU_SLIMCLK] = clk;
133
134 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0);
135 prcmu_clk[PRCMU_PER1CLK] = clk;
136
137 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0);
138 prcmu_clk[PRCMU_PER2CLK] = clk;
139
140 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0);
141 prcmu_clk[PRCMU_PER3CLK] = clk;
142
143 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0);
144 prcmu_clk[PRCMU_PER5CLK] = clk;
145
146 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0);
147 prcmu_clk[PRCMU_PER6CLK] = clk;
148
149 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0);
150 prcmu_clk[PRCMU_PER7CLK] = clk;
151
152 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
153 CLK_SET_RATE_GATE);
154 prcmu_clk[PRCMU_LCDCLK] = clk;
155
156 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0);
157 prcmu_clk[PRCMU_BMLCLK] = clk;
158
159 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
160 CLK_SET_RATE_GATE);
161 prcmu_clk[PRCMU_HSITXCLK] = clk;
162
163 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
164 CLK_SET_RATE_GATE);
165 prcmu_clk[PRCMU_HSIRXCLK] = clk;
166
167 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
168 CLK_SET_RATE_GATE);
169 prcmu_clk[PRCMU_HDMICLK] = clk;
170
171 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0);
172 prcmu_clk[PRCMU_APEATCLK] = clk;
173
174 clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
175 CLK_SET_RATE_GATE);
176 prcmu_clk[PRCMU_APETRACECLK] = clk;
177
178 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0);
179 prcmu_clk[PRCMU_MCDECLK] = clk;
180
181 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0);
182 prcmu_clk[PRCMU_IPI2CCLK] = clk;
183
184 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0);
185 prcmu_clk[PRCMU_DSIALTCLK] = clk;
186
187 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0);
188 prcmu_clk[PRCMU_DMACLK] = clk;
189
190 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0);
191 prcmu_clk[PRCMU_B2R2CLK] = clk;
192
193 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
194 CLK_SET_RATE_GATE);
195 prcmu_clk[PRCMU_TVCLK] = clk;
196
197 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0);
198 prcmu_clk[PRCMU_SSPCLK] = clk;
199
200 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0);
201 prcmu_clk[PRCMU_RNGCLK] = clk;
202
203 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0);
204 prcmu_clk[PRCMU_UICCCLK] = clk;
205
206 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
207 prcmu_clk[PRCMU_TIMCLK] = clk;
208
209 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
210 100000000, CLK_SET_RATE_GATE);
211 prcmu_clk[PRCMU_SDMMCCLK] = clk;
212
213 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
214 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
215 prcmu_clk[PRCMU_PLLDSI] = clk;
216
217 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
218 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
219 prcmu_clk[PRCMU_DSI0CLK] = clk;
220
221 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
222 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
223 prcmu_clk[PRCMU_DSI1CLK] = clk;
224
225 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
226 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
227 prcmu_clk[PRCMU_DSI0ESCCLK] = clk;
228
229 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
230 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
231 prcmu_clk[PRCMU_DSI1ESCCLK] = clk;
232
233 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
234 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
235 prcmu_clk[PRCMU_DSI2ESCCLK] = clk;
236
237 clk = clk_reg_prcmu_scalable_rate("armss", NULL,
238 PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED);
239 prcmu_clk[PRCMU_ARMSS] = clk;
240
241 twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
242 CLK_IGNORE_UNUSED, 1, 2);
243
244
245
246
247
248
249
250
251 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
252 BIT(0), 0);
253 PRCC_PCLK_STORE(clk, 1, 0);
254
255 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
256 BIT(1), 0);
257 PRCC_PCLK_STORE(clk, 1, 1);
258
259 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
260 BIT(2), 0);
261 PRCC_PCLK_STORE(clk, 1, 2);
262
263 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
264 BIT(3), 0);
265 PRCC_PCLK_STORE(clk, 1, 3);
266
267 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
268 BIT(4), 0);
269 PRCC_PCLK_STORE(clk, 1, 4);
270
271 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
272 BIT(5), 0);
273 PRCC_PCLK_STORE(clk, 1, 5);
274
275 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],
276 BIT(6), 0);
277 PRCC_PCLK_STORE(clk, 1, 6);
278
279 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],
280 BIT(7), 0);
281 PRCC_PCLK_STORE(clk, 1, 7);
282
283 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],
284 BIT(8), 0);
285 PRCC_PCLK_STORE(clk, 1, 8);
286
287 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],
288 BIT(9), 0);
289 PRCC_PCLK_STORE(clk, 1, 9);
290
291 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],
292 BIT(10), 0);
293 PRCC_PCLK_STORE(clk, 1, 10);
294
295 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],
296 BIT(11), 0);
297 PRCC_PCLK_STORE(clk, 1, 11);
298
299 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX],
300 BIT(0), 0);
301 PRCC_PCLK_STORE(clk, 2, 0);
302
303 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX],
304 BIT(1), 0);
305 PRCC_PCLK_STORE(clk, 2, 1);
306
307 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX],
308 BIT(2), 0);
309 PRCC_PCLK_STORE(clk, 2, 2);
310
311 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX],
312 BIT(3), 0);
313 PRCC_PCLK_STORE(clk, 2, 3);
314
315 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX],
316 BIT(4), 0);
317 PRCC_PCLK_STORE(clk, 2, 4);
318
319 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX],
320 BIT(5), 0);
321 PRCC_PCLK_STORE(clk, 2, 5);
322
323 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX],
324 BIT(6), 0);
325 PRCC_PCLK_STORE(clk, 2, 6);
326
327 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX],
328 BIT(7), 0);
329 PRCC_PCLK_STORE(clk, 2, 7);
330
331 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX],
332 BIT(8), 0);
333 PRCC_PCLK_STORE(clk, 2, 8);
334
335 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX],
336 BIT(9), 0);
337 PRCC_PCLK_STORE(clk, 2, 9);
338
339 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX],
340 BIT(10), 0);
341 PRCC_PCLK_STORE(clk, 2, 10);
342
343 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX],
344 BIT(11), 0);
345 PRCC_PCLK_STORE(clk, 2, 11);
346
347 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX],
348 BIT(12), 0);
349 PRCC_PCLK_STORE(clk, 2, 12);
350
351 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX],
352 BIT(0), 0);
353 PRCC_PCLK_STORE(clk, 3, 0);
354
355 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX],
356 BIT(1), 0);
357 PRCC_PCLK_STORE(clk, 3, 1);
358
359 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX],
360 BIT(2), 0);
361 PRCC_PCLK_STORE(clk, 3, 2);
362
363 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX],
364 BIT(3), 0);
365 PRCC_PCLK_STORE(clk, 3, 3);
366
367 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX],
368 BIT(4), 0);
369 PRCC_PCLK_STORE(clk, 3, 4);
370
371 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX],
372 BIT(5), 0);
373 PRCC_PCLK_STORE(clk, 3, 5);
374
375 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX],
376 BIT(6), 0);
377 PRCC_PCLK_STORE(clk, 3, 6);
378
379 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX],
380 BIT(7), 0);
381 PRCC_PCLK_STORE(clk, 3, 7);
382
383 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX],
384 BIT(8), 0);
385 PRCC_PCLK_STORE(clk, 3, 8);
386
387 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX],
388 BIT(0), 0);
389 PRCC_PCLK_STORE(clk, 5, 0);
390
391 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX],
392 BIT(1), 0);
393 PRCC_PCLK_STORE(clk, 5, 1);
394
395 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX],
396 BIT(0), 0);
397 PRCC_PCLK_STORE(clk, 6, 0);
398
399 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX],
400 BIT(1), 0);
401 PRCC_PCLK_STORE(clk, 6, 1);
402
403 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX],
404 BIT(2), 0);
405 PRCC_PCLK_STORE(clk, 6, 2);
406
407 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX],
408 BIT(3), 0);
409 PRCC_PCLK_STORE(clk, 6, 3);
410
411 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX],
412 BIT(4), 0);
413 PRCC_PCLK_STORE(clk, 6, 4);
414
415 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX],
416 BIT(5), 0);
417 PRCC_PCLK_STORE(clk, 6, 5);
418
419 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX],
420 BIT(6), 0);
421 PRCC_PCLK_STORE(clk, 6, 6);
422
423 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX],
424 BIT(7), 0);
425 PRCC_PCLK_STORE(clk, 6, 7);
426
427
428
429
430
431
432
433
434
435
436 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
437 bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);
438 PRCC_KCLK_STORE(clk, 1, 0);
439
440 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
441 bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);
442 PRCC_KCLK_STORE(clk, 1, 1);
443
444 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
445 bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);
446 PRCC_KCLK_STORE(clk, 1, 2);
447
448 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
449 bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);
450 PRCC_KCLK_STORE(clk, 1, 3);
451
452 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
453 bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);
454 PRCC_KCLK_STORE(clk, 1, 4);
455
456 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
457 bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);
458 PRCC_KCLK_STORE(clk, 1, 5);
459
460 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
461 bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);
462 PRCC_KCLK_STORE(clk, 1, 6);
463
464 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
465 bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);
466 PRCC_KCLK_STORE(clk, 1, 8);
467
468 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
469 bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);
470 PRCC_KCLK_STORE(clk, 1, 9);
471
472 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
473 bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);
474 PRCC_KCLK_STORE(clk, 1, 10);
475
476
477 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
478 bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);
479 PRCC_KCLK_STORE(clk, 2, 0);
480
481 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
482 bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);
483 PRCC_KCLK_STORE(clk, 2, 2);
484
485 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
486 bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);
487 PRCC_KCLK_STORE(clk, 2, 3);
488
489 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
490 bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);
491 PRCC_KCLK_STORE(clk, 2, 4);
492
493 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
494 bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);
495 PRCC_KCLK_STORE(clk, 2, 5);
496
497
498 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
499 bases[CLKRST2_INDEX], BIT(6),
500 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
501 PRCC_KCLK_STORE(clk, 2, 6);
502
503 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
504 bases[CLKRST2_INDEX], BIT(7),
505 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
506 PRCC_KCLK_STORE(clk, 2, 7);
507
508
509 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
510 bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);
511 PRCC_KCLK_STORE(clk, 3, 1);
512
513 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
514 bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);
515 PRCC_KCLK_STORE(clk, 3, 2);
516
517 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
518 bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);
519 PRCC_KCLK_STORE(clk, 3, 3);
520
521 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
522 bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);
523 PRCC_KCLK_STORE(clk, 3, 4);
524
525 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
526 bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);
527 PRCC_KCLK_STORE(clk, 3, 5);
528
529 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
530 bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);
531 PRCC_KCLK_STORE(clk, 3, 6);
532
533 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
534 bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);
535 PRCC_KCLK_STORE(clk, 3, 7);
536
537
538 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
539 bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);
540 PRCC_KCLK_STORE(clk, 6, 0);
541
542 for_each_child_of_node(np, child) {
543 static struct clk_onecell_data clk_data;
544
545 if (!of_node_cmp(child->name, "prcmu-clock")) {
546 clk_data.clks = prcmu_clk;
547 clk_data.clk_num = ARRAY_SIZE(prcmu_clk);
548 of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data);
549 }
550 if (!of_node_cmp(child->name, "prcc-periph-clock"))
551 of_clk_add_provider(child, ux500_twocell_get, prcc_pclk);
552
553 if (!of_node_cmp(child->name, "prcc-kernel-clock"))
554 of_clk_add_provider(child, ux500_twocell_get, prcc_kclk);
555
556 if (!of_node_cmp(child->name, "rtc32k-clock"))
557 of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk);
558
559 if (!of_node_cmp(child->name, "smp-twd-clock"))
560 of_clk_add_provider(child, of_clk_src_simple_get, twd_clk);
561 }
562}
563CLK_OF_DECLARE(u8500_clks, "stericsson,u8500-clks", u8500_clk_init);
564
