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14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/i2c.h>
17#include <linux/err.h>
18#include <linux/delay.h>
19#include <linux/sysfs.h>
20#include <linux/jiffies.h>
21#include <linux/irq.h>
22#include <linux/interrupt.h>
23#include <linux/kfifo.h>
24#include <linux/spinlock.h>
25#include <linux/iio/iio.h>
26#include <linux/acpi.h>
27#include "inv_mpu_iio.h"
28
29
30
31
32
33static const int gyro_scale_6050[] = {133090, 266181, 532362, 1064724};
34
35
36
37
38
39static const int accel_scale[] = {598, 1196, 2392, 4785};
40
41static const struct inv_mpu6050_reg_map reg_set_6500 = {
42 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
43 .lpf = INV_MPU6050_REG_CONFIG,
44 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
45 .fifo_en = INV_MPU6050_REG_FIFO_EN,
46 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
47 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
48 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
49 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
50 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
51 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
52 .temperature = INV_MPU6050_REG_TEMPERATURE,
53 .int_enable = INV_MPU6050_REG_INT_ENABLE,
54 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
55 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
56 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
57 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
58 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
59};
60
61static const struct inv_mpu6050_reg_map reg_set_6050 = {
62 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
63 .lpf = INV_MPU6050_REG_CONFIG,
64 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
65 .fifo_en = INV_MPU6050_REG_FIFO_EN,
66 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
67 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
68 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
69 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
70 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
71 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
72 .temperature = INV_MPU6050_REG_TEMPERATURE,
73 .int_enable = INV_MPU6050_REG_INT_ENABLE,
74 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
75 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
76 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
77 .accl_offset = INV_MPU6050_REG_ACCEL_OFFSET,
78 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
79};
80
81static const struct inv_mpu6050_chip_config chip_config_6050 = {
82 .fsr = INV_MPU6050_FSR_2000DPS,
83 .lpf = INV_MPU6050_FILTER_20HZ,
84 .fifo_rate = INV_MPU6050_INIT_FIFO_RATE,
85 .gyro_fifo_enable = false,
86 .accl_fifo_enable = false,
87 .accl_fs = INV_MPU6050_FS_02G,
88};
89
90
91static const struct inv_mpu6050_hw hw_info[] = {
92 {
93 .whoami = INV_MPU6050_WHOAMI_VALUE,
94 .name = "MPU6050",
95 .reg = ®_set_6050,
96 .config = &chip_config_6050,
97 },
98 {
99 .whoami = INV_MPU6500_WHOAMI_VALUE,
100 .name = "MPU6500",
101 .reg = ®_set_6500,
102 .config = &chip_config_6050,
103 },
104 {
105 .whoami = INV_MPU6000_WHOAMI_VALUE,
106 .name = "MPU6000",
107 .reg = ®_set_6050,
108 .config = &chip_config_6050,
109 },
110 {
111 .whoami = INV_MPU9150_WHOAMI_VALUE,
112 .name = "MPU9150",
113 .reg = ®_set_6050,
114 .config = &chip_config_6050,
115 },
116 {
117 .whoami = INV_ICM20608_WHOAMI_VALUE,
118 .name = "ICM20608",
119 .reg = ®_set_6500,
120 .config = &chip_config_6050,
121 },
122};
123
124int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask)
125{
126 unsigned int d, mgmt_1;
127 int result;
128
129
130
131
132
133 if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) {
134 result = regmap_read(st->map, st->reg->pwr_mgmt_1, &mgmt_1);
135 if (result)
136 return result;
137
138 mgmt_1 &= ~INV_MPU6050_BIT_CLK_MASK;
139 }
140
141 if ((mask == INV_MPU6050_BIT_PWR_GYRO_STBY) && (!en)) {
142
143
144
145
146 mgmt_1 |= INV_CLK_INTERNAL;
147 result = regmap_write(st->map, st->reg->pwr_mgmt_1, mgmt_1);
148 if (result)
149 return result;
150 }
151
152 result = regmap_read(st->map, st->reg->pwr_mgmt_2, &d);
153 if (result)
154 return result;
155 if (en)
156 d &= ~mask;
157 else
158 d |= mask;
159 result = regmap_write(st->map, st->reg->pwr_mgmt_2, d);
160 if (result)
161 return result;
162
163 if (en) {
164
165 msleep(INV_MPU6050_TEMP_UP_TIME);
166 if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) {
167
168 mgmt_1 |= INV_CLK_PLL;
169 result = regmap_write(st->map,
170 st->reg->pwr_mgmt_1, mgmt_1);
171 if (result)
172 return result;
173 }
174 }
175
176 return 0;
177}
178
179int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on)
180{
181 int result = 0;
182
183 if (power_on) {
184
185 if (!st->powerup_count)
186 result = regmap_write(st->map, st->reg->pwr_mgmt_1, 0);
187 if (!result)
188 st->powerup_count++;
189 } else {
190 st->powerup_count--;
191 if (!st->powerup_count)
192 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
193 INV_MPU6050_BIT_SLEEP);
194 }
195
196 if (result)
197 return result;
198
199 if (power_on)
200 usleep_range(INV_MPU6050_REG_UP_TIME_MIN,
201 INV_MPU6050_REG_UP_TIME_MAX);
202
203 return 0;
204}
205EXPORT_SYMBOL_GPL(inv_mpu6050_set_power_itg);
206
207
208
209
210
211
212
213
214
215
216static int inv_mpu6050_init_config(struct iio_dev *indio_dev)
217{
218 int result;
219 u8 d;
220 struct inv_mpu6050_state *st = iio_priv(indio_dev);
221
222 result = inv_mpu6050_set_power_itg(st, true);
223 if (result)
224 return result;
225 d = (INV_MPU6050_FSR_2000DPS << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
226 result = regmap_write(st->map, st->reg->gyro_config, d);
227 if (result)
228 return result;
229
230 d = INV_MPU6050_FILTER_20HZ;
231 result = regmap_write(st->map, st->reg->lpf, d);
232 if (result)
233 return result;
234
235 d = INV_MPU6050_ONE_K_HZ / INV_MPU6050_INIT_FIFO_RATE - 1;
236 result = regmap_write(st->map, st->reg->sample_rate_div, d);
237 if (result)
238 return result;
239
240 d = (INV_MPU6050_FS_02G << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
241 result = regmap_write(st->map, st->reg->accl_config, d);
242 if (result)
243 return result;
244
245 memcpy(&st->chip_config, hw_info[st->chip_type].config,
246 sizeof(struct inv_mpu6050_chip_config));
247 result = inv_mpu6050_set_power_itg(st, false);
248
249 return result;
250}
251
252static int inv_mpu6050_sensor_set(struct inv_mpu6050_state *st, int reg,
253 int axis, int val)
254{
255 int ind, result;
256 __be16 d = cpu_to_be16(val);
257
258 ind = (axis - IIO_MOD_X) * 2;
259 result = regmap_bulk_write(st->map, reg + ind, (u8 *)&d, 2);
260 if (result)
261 return -EINVAL;
262
263 return 0;
264}
265
266static int inv_mpu6050_sensor_show(struct inv_mpu6050_state *st, int reg,
267 int axis, int *val)
268{
269 int ind, result;
270 __be16 d;
271
272 ind = (axis - IIO_MOD_X) * 2;
273 result = regmap_bulk_read(st->map, reg + ind, (u8 *)&d, 2);
274 if (result)
275 return -EINVAL;
276 *val = (short)be16_to_cpup(&d);
277
278 return IIO_VAL_INT;
279}
280
281static int
282inv_mpu6050_read_raw(struct iio_dev *indio_dev,
283 struct iio_chan_spec const *chan,
284 int *val, int *val2, long mask)
285{
286 struct inv_mpu6050_state *st = iio_priv(indio_dev);
287 int ret = 0;
288
289 switch (mask) {
290 case IIO_CHAN_INFO_RAW:
291 {
292 int result;
293
294 ret = IIO_VAL_INT;
295 result = 0;
296 mutex_lock(&indio_dev->mlock);
297 if (!st->chip_config.enable) {
298 result = inv_mpu6050_set_power_itg(st, true);
299 if (result)
300 goto error_read_raw;
301 }
302
303 switch (chan->type) {
304 case IIO_ANGL_VEL:
305 if (!st->chip_config.gyro_fifo_enable ||
306 !st->chip_config.enable) {
307 result = inv_mpu6050_switch_engine(st, true,
308 INV_MPU6050_BIT_PWR_GYRO_STBY);
309 if (result)
310 goto error_read_raw;
311 }
312 ret = inv_mpu6050_sensor_show(st, st->reg->raw_gyro,
313 chan->channel2, val);
314 if (!st->chip_config.gyro_fifo_enable ||
315 !st->chip_config.enable) {
316 result = inv_mpu6050_switch_engine(st, false,
317 INV_MPU6050_BIT_PWR_GYRO_STBY);
318 if (result)
319 goto error_read_raw;
320 }
321 break;
322 case IIO_ACCEL:
323 if (!st->chip_config.accl_fifo_enable ||
324 !st->chip_config.enable) {
325 result = inv_mpu6050_switch_engine(st, true,
326 INV_MPU6050_BIT_PWR_ACCL_STBY);
327 if (result)
328 goto error_read_raw;
329 }
330 ret = inv_mpu6050_sensor_show(st, st->reg->raw_accl,
331 chan->channel2, val);
332 if (!st->chip_config.accl_fifo_enable ||
333 !st->chip_config.enable) {
334 result = inv_mpu6050_switch_engine(st, false,
335 INV_MPU6050_BIT_PWR_ACCL_STBY);
336 if (result)
337 goto error_read_raw;
338 }
339 break;
340 case IIO_TEMP:
341
342 msleep(INV_MPU6050_SENSOR_UP_TIME);
343 ret = inv_mpu6050_sensor_show(st, st->reg->temperature,
344 IIO_MOD_X, val);
345 break;
346 default:
347 ret = -EINVAL;
348 break;
349 }
350error_read_raw:
351 if (!st->chip_config.enable)
352 result |= inv_mpu6050_set_power_itg(st, false);
353 mutex_unlock(&indio_dev->mlock);
354 if (result)
355 return result;
356
357 return ret;
358 }
359 case IIO_CHAN_INFO_SCALE:
360 switch (chan->type) {
361 case IIO_ANGL_VEL:
362 *val = 0;
363 *val2 = gyro_scale_6050[st->chip_config.fsr];
364
365 return IIO_VAL_INT_PLUS_NANO;
366 case IIO_ACCEL:
367 *val = 0;
368 *val2 = accel_scale[st->chip_config.accl_fs];
369
370 return IIO_VAL_INT_PLUS_MICRO;
371 case IIO_TEMP:
372 *val = 0;
373 *val2 = INV_MPU6050_TEMP_SCALE;
374
375 return IIO_VAL_INT_PLUS_MICRO;
376 default:
377 return -EINVAL;
378 }
379 case IIO_CHAN_INFO_OFFSET:
380 switch (chan->type) {
381 case IIO_TEMP:
382 *val = INV_MPU6050_TEMP_OFFSET;
383
384 return IIO_VAL_INT;
385 default:
386 return -EINVAL;
387 }
388 case IIO_CHAN_INFO_CALIBBIAS:
389 switch (chan->type) {
390 case IIO_ANGL_VEL:
391 ret = inv_mpu6050_sensor_show(st, st->reg->gyro_offset,
392 chan->channel2, val);
393 return IIO_VAL_INT;
394 case IIO_ACCEL:
395 ret = inv_mpu6050_sensor_show(st, st->reg->accl_offset,
396 chan->channel2, val);
397 return IIO_VAL_INT;
398
399 default:
400 return -EINVAL;
401 }
402 default:
403 return -EINVAL;
404 }
405}
406
407static int inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state *st, int val)
408{
409 int result, i;
410 u8 d;
411
412 for (i = 0; i < ARRAY_SIZE(gyro_scale_6050); ++i) {
413 if (gyro_scale_6050[i] == val) {
414 d = (i << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
415 result = regmap_write(st->map, st->reg->gyro_config, d);
416 if (result)
417 return result;
418
419 st->chip_config.fsr = i;
420 return 0;
421 }
422 }
423
424 return -EINVAL;
425}
426
427static int inv_write_raw_get_fmt(struct iio_dev *indio_dev,
428 struct iio_chan_spec const *chan, long mask)
429{
430 switch (mask) {
431 case IIO_CHAN_INFO_SCALE:
432 switch (chan->type) {
433 case IIO_ANGL_VEL:
434 return IIO_VAL_INT_PLUS_NANO;
435 default:
436 return IIO_VAL_INT_PLUS_MICRO;
437 }
438 default:
439 return IIO_VAL_INT_PLUS_MICRO;
440 }
441
442 return -EINVAL;
443}
444
445static int inv_mpu6050_write_accel_scale(struct inv_mpu6050_state *st, int val)
446{
447 int result, i;
448 u8 d;
449
450 for (i = 0; i < ARRAY_SIZE(accel_scale); ++i) {
451 if (accel_scale[i] == val) {
452 d = (i << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
453 result = regmap_write(st->map, st->reg->accl_config, d);
454 if (result)
455 return result;
456
457 st->chip_config.accl_fs = i;
458 return 0;
459 }
460 }
461
462 return -EINVAL;
463}
464
465static int inv_mpu6050_write_raw(struct iio_dev *indio_dev,
466 struct iio_chan_spec const *chan,
467 int val, int val2, long mask)
468{
469 struct inv_mpu6050_state *st = iio_priv(indio_dev);
470 int result;
471
472 mutex_lock(&indio_dev->mlock);
473
474
475
476
477 if (st->chip_config.enable) {
478 result = -EBUSY;
479 goto error_write_raw;
480 }
481 result = inv_mpu6050_set_power_itg(st, true);
482 if (result)
483 goto error_write_raw;
484
485 switch (mask) {
486 case IIO_CHAN_INFO_SCALE:
487 switch (chan->type) {
488 case IIO_ANGL_VEL:
489 result = inv_mpu6050_write_gyro_scale(st, val2);
490 break;
491 case IIO_ACCEL:
492 result = inv_mpu6050_write_accel_scale(st, val2);
493 break;
494 default:
495 result = -EINVAL;
496 break;
497 }
498 break;
499 case IIO_CHAN_INFO_CALIBBIAS:
500 switch (chan->type) {
501 case IIO_ANGL_VEL:
502 result = inv_mpu6050_sensor_set(st,
503 st->reg->gyro_offset,
504 chan->channel2, val);
505 break;
506 case IIO_ACCEL:
507 result = inv_mpu6050_sensor_set(st,
508 st->reg->accl_offset,
509 chan->channel2, val);
510 break;
511 default:
512 result = -EINVAL;
513 }
514 default:
515 result = -EINVAL;
516 break;
517 }
518
519error_write_raw:
520 result |= inv_mpu6050_set_power_itg(st, false);
521 mutex_unlock(&indio_dev->mlock);
522
523 return result;
524}
525
526
527
528
529
530
531
532
533
534
535static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate)
536{
537 const int hz[] = {188, 98, 42, 20, 10, 5};
538 const int d[] = {INV_MPU6050_FILTER_188HZ, INV_MPU6050_FILTER_98HZ,
539 INV_MPU6050_FILTER_42HZ, INV_MPU6050_FILTER_20HZ,
540 INV_MPU6050_FILTER_10HZ, INV_MPU6050_FILTER_5HZ};
541 int i, h, result;
542 u8 data;
543
544 h = (rate >> 1);
545 i = 0;
546 while ((h < hz[i]) && (i < ARRAY_SIZE(d) - 1))
547 i++;
548 data = d[i];
549 result = regmap_write(st->map, st->reg->lpf, data);
550 if (result)
551 return result;
552 st->chip_config.lpf = data;
553
554 return 0;
555}
556
557
558
559
560static ssize_t
561inv_mpu6050_fifo_rate_store(struct device *dev, struct device_attribute *attr,
562 const char *buf, size_t count)
563{
564 s32 fifo_rate;
565 u8 d;
566 int result;
567 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
568 struct inv_mpu6050_state *st = iio_priv(indio_dev);
569
570 if (kstrtoint(buf, 10, &fifo_rate))
571 return -EINVAL;
572 if (fifo_rate < INV_MPU6050_MIN_FIFO_RATE ||
573 fifo_rate > INV_MPU6050_MAX_FIFO_RATE)
574 return -EINVAL;
575 if (fifo_rate == st->chip_config.fifo_rate)
576 return count;
577
578 mutex_lock(&indio_dev->mlock);
579 if (st->chip_config.enable) {
580 result = -EBUSY;
581 goto fifo_rate_fail;
582 }
583 result = inv_mpu6050_set_power_itg(st, true);
584 if (result)
585 goto fifo_rate_fail;
586
587 d = INV_MPU6050_ONE_K_HZ / fifo_rate - 1;
588 result = regmap_write(st->map, st->reg->sample_rate_div, d);
589 if (result)
590 goto fifo_rate_fail;
591 st->chip_config.fifo_rate = fifo_rate;
592
593 result = inv_mpu6050_set_lpf(st, fifo_rate);
594 if (result)
595 goto fifo_rate_fail;
596
597fifo_rate_fail:
598 result |= inv_mpu6050_set_power_itg(st, false);
599 mutex_unlock(&indio_dev->mlock);
600 if (result)
601 return result;
602
603 return count;
604}
605
606
607
608
609static ssize_t
610inv_fifo_rate_show(struct device *dev, struct device_attribute *attr,
611 char *buf)
612{
613 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
614
615 return sprintf(buf, "%d\n", st->chip_config.fifo_rate);
616}
617
618
619
620
621
622
623
624
625
626static ssize_t inv_attr_show(struct device *dev, struct device_attribute *attr,
627 char *buf)
628{
629 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
630 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
631 s8 *m;
632
633 switch (this_attr->address) {
634
635
636
637
638 case ATTR_GYRO_MATRIX:
639 case ATTR_ACCL_MATRIX:
640 m = st->plat_data.orientation;
641
642 return sprintf(buf, "%d, %d, %d; %d, %d, %d; %d, %d, %d\n",
643 m[0], m[1], m[2], m[3], m[4], m[5], m[6], m[7], m[8]);
644 default:
645 return -EINVAL;
646 }
647}
648
649
650
651
652
653
654
655
656
657
658static int inv_mpu6050_validate_trigger(struct iio_dev *indio_dev,
659 struct iio_trigger *trig)
660{
661 struct inv_mpu6050_state *st = iio_priv(indio_dev);
662
663 if (st->trig != trig)
664 return -EINVAL;
665
666 return 0;
667}
668
669static const struct iio_mount_matrix *
670inv_get_mount_matrix(const struct iio_dev *indio_dev,
671 const struct iio_chan_spec *chan)
672{
673 return &((struct inv_mpu6050_state *)iio_priv(indio_dev))->orientation;
674}
675
676static const struct iio_chan_spec_ext_info inv_ext_info[] = {
677 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, inv_get_mount_matrix),
678 { },
679};
680
681#define INV_MPU6050_CHAN(_type, _channel2, _index) \
682 { \
683 .type = _type, \
684 .modified = 1, \
685 .channel2 = _channel2, \
686 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
687 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
688 BIT(IIO_CHAN_INFO_CALIBBIAS), \
689 .scan_index = _index, \
690 .scan_type = { \
691 .sign = 's', \
692 .realbits = 16, \
693 .storagebits = 16, \
694 .shift = 0, \
695 .endianness = IIO_BE, \
696 }, \
697 .ext_info = inv_ext_info, \
698 }
699
700static const struct iio_chan_spec inv_mpu_channels[] = {
701 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
702
703
704
705
706 {
707 .type = IIO_TEMP,
708 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)
709 | BIT(IIO_CHAN_INFO_OFFSET)
710 | BIT(IIO_CHAN_INFO_SCALE),
711 .scan_index = -1,
712 },
713 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
714 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
715 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
716
717 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
718 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
719 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
720};
721
722
723static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 20 50 100 200 500");
724static IIO_CONST_ATTR(in_anglvel_scale_available,
725 "0.000133090 0.000266181 0.000532362 0.001064724");
726static IIO_CONST_ATTR(in_accel_scale_available,
727 "0.000598 0.001196 0.002392 0.004785");
728static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, inv_fifo_rate_show,
729 inv_mpu6050_fifo_rate_store);
730
731
732static IIO_DEVICE_ATTR(in_gyro_matrix, S_IRUGO, inv_attr_show, NULL,
733 ATTR_GYRO_MATRIX);
734static IIO_DEVICE_ATTR(in_accel_matrix, S_IRUGO, inv_attr_show, NULL,
735 ATTR_ACCL_MATRIX);
736
737static struct attribute *inv_attributes[] = {
738 &iio_dev_attr_in_gyro_matrix.dev_attr.attr,
739 &iio_dev_attr_in_accel_matrix.dev_attr.attr,
740 &iio_dev_attr_sampling_frequency.dev_attr.attr,
741 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
742 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
743 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
744 NULL,
745};
746
747static const struct attribute_group inv_attribute_group = {
748 .attrs = inv_attributes
749};
750
751static const struct iio_info mpu_info = {
752 .driver_module = THIS_MODULE,
753 .read_raw = &inv_mpu6050_read_raw,
754 .write_raw = &inv_mpu6050_write_raw,
755 .write_raw_get_fmt = &inv_write_raw_get_fmt,
756 .attrs = &inv_attribute_group,
757 .validate_trigger = inv_mpu6050_validate_trigger,
758};
759
760
761
762
763static int inv_check_and_setup_chip(struct inv_mpu6050_state *st)
764{
765 int result;
766 unsigned int regval;
767
768 st->hw = &hw_info[st->chip_type];
769 st->reg = hw_info[st->chip_type].reg;
770
771
772 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
773 INV_MPU6050_BIT_H_RESET);
774 if (result)
775 return result;
776 msleep(INV_MPU6050_POWER_UP_TIME);
777
778
779 result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, ®val);
780 if (result)
781 return result;
782 if (regval != st->hw->whoami) {
783 dev_warn(regmap_get_device(st->map),
784 "whoami mismatch got %#02x expected %#02hhx for %s\n",
785 regval, st->hw->whoami, st->hw->name);
786 }
787
788
789
790
791
792
793
794 result = inv_mpu6050_set_power_itg(st, false);
795 if (result)
796 return result;
797 result = inv_mpu6050_set_power_itg(st, true);
798 if (result)
799 return result;
800
801 result = inv_mpu6050_switch_engine(st, false,
802 INV_MPU6050_BIT_PWR_ACCL_STBY);
803 if (result)
804 return result;
805 result = inv_mpu6050_switch_engine(st, false,
806 INV_MPU6050_BIT_PWR_GYRO_STBY);
807 if (result)
808 return result;
809
810 return 0;
811}
812
813int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
814 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type)
815{
816 struct inv_mpu6050_state *st;
817 struct iio_dev *indio_dev;
818 struct inv_mpu6050_platform_data *pdata;
819 struct device *dev = regmap_get_device(regmap);
820 int result;
821
822 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
823 if (!indio_dev)
824 return -ENOMEM;
825
826 BUILD_BUG_ON(ARRAY_SIZE(hw_info) != INV_NUM_PARTS);
827 if (chip_type < 0 || chip_type >= INV_NUM_PARTS) {
828 dev_err(dev, "Bad invensense chip_type=%d name=%s\n",
829 chip_type, name);
830 return -ENODEV;
831 }
832 st = iio_priv(indio_dev);
833 st->chip_type = chip_type;
834 st->powerup_count = 0;
835 st->irq = irq;
836 st->map = regmap;
837
838 pdata = dev_get_platdata(dev);
839 if (!pdata) {
840 result = of_iio_read_mount_matrix(dev, "mount-matrix",
841 &st->orientation);
842 if (result) {
843 dev_err(dev, "Failed to retrieve mounting matrix %d\n",
844 result);
845 return result;
846 }
847 } else {
848 st->plat_data = *pdata;
849 }
850
851
852 result = inv_check_and_setup_chip(st);
853 if (result)
854 return result;
855
856 if (inv_mpu_bus_setup)
857 inv_mpu_bus_setup(indio_dev);
858
859 result = inv_mpu6050_init_config(indio_dev);
860 if (result) {
861 dev_err(dev, "Could not initialize device.\n");
862 return result;
863 }
864
865 dev_set_drvdata(dev, indio_dev);
866 indio_dev->dev.parent = dev;
867
868 if (name)
869 indio_dev->name = name;
870 else
871 indio_dev->name = dev_name(dev);
872 indio_dev->channels = inv_mpu_channels;
873 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
874
875 indio_dev->info = &mpu_info;
876 indio_dev->modes = INDIO_BUFFER_TRIGGERED;
877
878 result = iio_triggered_buffer_setup(indio_dev,
879 inv_mpu6050_irq_handler,
880 inv_mpu6050_read_fifo,
881 NULL);
882 if (result) {
883 dev_err(dev, "configure buffer fail %d\n", result);
884 return result;
885 }
886 result = inv_mpu6050_probe_trigger(indio_dev);
887 if (result) {
888 dev_err(dev, "trigger probe fail %d\n", result);
889 goto out_unreg_ring;
890 }
891
892 INIT_KFIFO(st->timestamps);
893 spin_lock_init(&st->time_stamp_lock);
894 result = iio_device_register(indio_dev);
895 if (result) {
896 dev_err(dev, "IIO register fail %d\n", result);
897 goto out_remove_trigger;
898 }
899
900 return 0;
901
902out_remove_trigger:
903 inv_mpu6050_remove_trigger(st);
904out_unreg_ring:
905 iio_triggered_buffer_cleanup(indio_dev);
906 return result;
907}
908EXPORT_SYMBOL_GPL(inv_mpu_core_probe);
909
910int inv_mpu_core_remove(struct device *dev)
911{
912 struct iio_dev *indio_dev = dev_get_drvdata(dev);
913
914 iio_device_unregister(indio_dev);
915 inv_mpu6050_remove_trigger(iio_priv(indio_dev));
916 iio_triggered_buffer_cleanup(indio_dev);
917
918 return 0;
919}
920EXPORT_SYMBOL_GPL(inv_mpu_core_remove);
921
922#ifdef CONFIG_PM_SLEEP
923
924static int inv_mpu_resume(struct device *dev)
925{
926 return inv_mpu6050_set_power_itg(iio_priv(dev_get_drvdata(dev)), true);
927}
928
929static int inv_mpu_suspend(struct device *dev)
930{
931 return inv_mpu6050_set_power_itg(iio_priv(dev_get_drvdata(dev)), false);
932}
933#endif
934
935SIMPLE_DEV_PM_OPS(inv_mpu_pmops, inv_mpu_suspend, inv_mpu_resume);
936EXPORT_SYMBOL_GPL(inv_mpu_pmops);
937
938MODULE_AUTHOR("Invensense Corporation");
939MODULE_DESCRIPTION("Invensense device MPU6050 driver");
940MODULE_LICENSE("GPL");
941
