linux/drivers/media/platform/marvell-ccic/mcam-core.c
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   1/*
   2 * The Marvell camera core.  This device appears in a number of settings,
   3 * so it needs platform-specific support outside of the core.
   4 *
   5 * Copyright 2011 Jonathan Corbet corbet@lwn.net
   6 */
   7#include <linux/kernel.h>
   8#include <linux/module.h>
   9#include <linux/fs.h>
  10#include <linux/mm.h>
  11#include <linux/i2c.h>
  12#include <linux/interrupt.h>
  13#include <linux/spinlock.h>
  14#include <linux/slab.h>
  15#include <linux/device.h>
  16#include <linux/wait.h>
  17#include <linux/list.h>
  18#include <linux/dma-mapping.h>
  19#include <linux/delay.h>
  20#include <linux/vmalloc.h>
  21#include <linux/io.h>
  22#include <linux/clk.h>
  23#include <linux/videodev2.h>
  24#include <media/v4l2-device.h>
  25#include <media/v4l2-ioctl.h>
  26#include <media/v4l2-ctrls.h>
  27#include <media/v4l2-event.h>
  28#include <media/i2c/ov7670.h>
  29#include <media/videobuf2-vmalloc.h>
  30#include <media/videobuf2-dma-contig.h>
  31#include <media/videobuf2-dma-sg.h>
  32
  33#include "mcam-core.h"
  34
  35#ifdef MCAM_MODE_VMALLOC
  36/*
  37 * Internal DMA buffer management.  Since the controller cannot do S/G I/O,
  38 * we must have physically contiguous buffers to bring frames into.
  39 * These parameters control how many buffers we use, whether we
  40 * allocate them at load time (better chance of success, but nails down
  41 * memory) or when somebody tries to use the camera (riskier), and,
  42 * for load-time allocation, how big they should be.
  43 *
  44 * The controller can cycle through three buffers.  We could use
  45 * more by flipping pointers around, but it probably makes little
  46 * sense.
  47 */
  48
  49static bool alloc_bufs_at_read;
  50module_param(alloc_bufs_at_read, bool, 0444);
  51MODULE_PARM_DESC(alloc_bufs_at_read,
  52                "Non-zero value causes DMA buffers to be allocated when the "
  53                "video capture device is read, rather than at module load "
  54                "time.  This saves memory, but decreases the chances of "
  55                "successfully getting those buffers.  This parameter is "
  56                "only used in the vmalloc buffer mode");
  57
  58static int n_dma_bufs = 3;
  59module_param(n_dma_bufs, uint, 0644);
  60MODULE_PARM_DESC(n_dma_bufs,
  61                "The number of DMA buffers to allocate.  Can be either two "
  62                "(saves memory, makes timing tighter) or three.");
  63
  64static int dma_buf_size = VGA_WIDTH * VGA_HEIGHT * 2;  /* Worst case */
  65module_param(dma_buf_size, uint, 0444);
  66MODULE_PARM_DESC(dma_buf_size,
  67                "The size of the allocated DMA buffers.  If actual operating "
  68                "parameters require larger buffers, an attempt to reallocate "
  69                "will be made.");
  70#else /* MCAM_MODE_VMALLOC */
  71static const bool alloc_bufs_at_read;
  72static const int n_dma_bufs = 3;  /* Used by S/G_PARM */
  73#endif /* MCAM_MODE_VMALLOC */
  74
  75static bool flip;
  76module_param(flip, bool, 0444);
  77MODULE_PARM_DESC(flip,
  78                "If set, the sensor will be instructed to flip the image "
  79                "vertically.");
  80
  81static int buffer_mode = -1;
  82module_param(buffer_mode, int, 0444);
  83MODULE_PARM_DESC(buffer_mode,
  84                "Set the buffer mode to be used; default is to go with what "
  85                "the platform driver asks for.  Set to 0 for vmalloc, 1 for "
  86                "DMA contiguous.");
  87
  88/*
  89 * Status flags.  Always manipulated with bit operations.
  90 */
  91#define CF_BUF0_VALID    0      /* Buffers valid - first three */
  92#define CF_BUF1_VALID    1
  93#define CF_BUF2_VALID    2
  94#define CF_DMA_ACTIVE    3      /* A frame is incoming */
  95#define CF_CONFIG_NEEDED 4      /* Must configure hardware */
  96#define CF_SINGLE_BUFFER 5      /* Running with a single buffer */
  97#define CF_SG_RESTART    6      /* SG restart needed */
  98#define CF_FRAME_SOF0    7      /* Frame 0 started */
  99#define CF_FRAME_SOF1    8
 100#define CF_FRAME_SOF2    9
 101
 102#define sensor_call(cam, o, f, args...) \
 103        v4l2_subdev_call(cam->sensor, o, f, ##args)
 104
 105static struct mcam_format_struct {
 106        __u8 *desc;
 107        __u32 pixelformat;
 108        int bpp;   /* Bytes per pixel */
 109        bool planar;
 110        u32 mbus_code;
 111} mcam_formats[] = {
 112        {
 113                .desc           = "YUYV 4:2:2",
 114                .pixelformat    = V4L2_PIX_FMT_YUYV,
 115                .mbus_code      = MEDIA_BUS_FMT_YUYV8_2X8,
 116                .bpp            = 2,
 117                .planar         = false,
 118        },
 119        {
 120                .desc           = "YVYU 4:2:2",
 121                .pixelformat    = V4L2_PIX_FMT_YVYU,
 122                .mbus_code      = MEDIA_BUS_FMT_YUYV8_2X8,
 123                .bpp            = 2,
 124                .planar         = false,
 125        },
 126        {
 127                .desc           = "YUV 4:2:0 PLANAR",
 128                .pixelformat    = V4L2_PIX_FMT_YUV420,
 129                .mbus_code      = MEDIA_BUS_FMT_YUYV8_2X8,
 130                .bpp            = 1,
 131                .planar         = true,
 132        },
 133        {
 134                .desc           = "YVU 4:2:0 PLANAR",
 135                .pixelformat    = V4L2_PIX_FMT_YVU420,
 136                .mbus_code      = MEDIA_BUS_FMT_YUYV8_2X8,
 137                .bpp            = 1,
 138                .planar         = true,
 139        },
 140        {
 141                .desc           = "XRGB 444",
 142                .pixelformat    = V4L2_PIX_FMT_XRGB444,
 143                .mbus_code      = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
 144                .bpp            = 2,
 145                .planar         = false,
 146        },
 147        {
 148                .desc           = "RGB 565",
 149                .pixelformat    = V4L2_PIX_FMT_RGB565,
 150                .mbus_code      = MEDIA_BUS_FMT_RGB565_2X8_LE,
 151                .bpp            = 2,
 152                .planar         = false,
 153        },
 154        {
 155                .desc           = "Raw RGB Bayer",
 156                .pixelformat    = V4L2_PIX_FMT_SBGGR8,
 157                .mbus_code      = MEDIA_BUS_FMT_SBGGR8_1X8,
 158                .bpp            = 1,
 159                .planar         = false,
 160        },
 161};
 162#define N_MCAM_FMTS ARRAY_SIZE(mcam_formats)
 163
 164static struct mcam_format_struct *mcam_find_format(u32 pixelformat)
 165{
 166        unsigned i;
 167
 168        for (i = 0; i < N_MCAM_FMTS; i++)
 169                if (mcam_formats[i].pixelformat == pixelformat)
 170                        return mcam_formats + i;
 171        /* Not found? Then return the first format. */
 172        return mcam_formats;
 173}
 174
 175/*
 176 * The default format we use until somebody says otherwise.
 177 */
 178static const struct v4l2_pix_format mcam_def_pix_format = {
 179        .width          = VGA_WIDTH,
 180        .height         = VGA_HEIGHT,
 181        .pixelformat    = V4L2_PIX_FMT_YUYV,
 182        .field          = V4L2_FIELD_NONE,
 183        .bytesperline   = VGA_WIDTH*2,
 184        .sizeimage      = VGA_WIDTH*VGA_HEIGHT*2,
 185        .colorspace     = V4L2_COLORSPACE_SRGB,
 186};
 187
 188static const u32 mcam_def_mbus_code = MEDIA_BUS_FMT_YUYV8_2X8;
 189
 190
 191/*
 192 * The two-word DMA descriptor format used by the Armada 610 and like.  There
 193 * Is a three-word format as well (set C1_DESC_3WORD) where the third
 194 * word is a pointer to the next descriptor, but we don't use it.  Two-word
 195 * descriptors have to be contiguous in memory.
 196 */
 197struct mcam_dma_desc {
 198        u32 dma_addr;
 199        u32 segment_len;
 200};
 201
 202/*
 203 * Our buffer type for working with videobuf2.  Note that the vb2
 204 * developers have decreed that struct vb2_v4l2_buffer must be at the
 205 * beginning of this structure.
 206 */
 207struct mcam_vb_buffer {
 208        struct vb2_v4l2_buffer vb_buf;
 209        struct list_head queue;
 210        struct mcam_dma_desc *dma_desc; /* Descriptor virtual address */
 211        dma_addr_t dma_desc_pa;         /* Descriptor physical address */
 212        int dma_desc_nent;              /* Number of mapped descriptors */
 213};
 214
 215static inline struct mcam_vb_buffer *vb_to_mvb(struct vb2_v4l2_buffer *vb)
 216{
 217        return container_of(vb, struct mcam_vb_buffer, vb_buf);
 218}
 219
 220/*
 221 * Hand a completed buffer back to user space.
 222 */
 223static void mcam_buffer_done(struct mcam_camera *cam, int frame,
 224                struct vb2_v4l2_buffer *vbuf)
 225{
 226        vbuf->vb2_buf.planes[0].bytesused = cam->pix_format.sizeimage;
 227        vbuf->sequence = cam->buf_seq[frame];
 228        vbuf->field = V4L2_FIELD_NONE;
 229        vbuf->vb2_buf.timestamp = ktime_get_ns();
 230        vb2_set_plane_payload(&vbuf->vb2_buf, 0, cam->pix_format.sizeimage);
 231        vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_DONE);
 232}
 233
 234
 235
 236/*
 237 * Debugging and related.
 238 */
 239#define cam_err(cam, fmt, arg...) \
 240        dev_err((cam)->dev, fmt, ##arg);
 241#define cam_warn(cam, fmt, arg...) \
 242        dev_warn((cam)->dev, fmt, ##arg);
 243#define cam_dbg(cam, fmt, arg...) \
 244        dev_dbg((cam)->dev, fmt, ##arg);
 245
 246
 247/*
 248 * Flag manipulation helpers
 249 */
 250static void mcam_reset_buffers(struct mcam_camera *cam)
 251{
 252        int i;
 253
 254        cam->next_buf = -1;
 255        for (i = 0; i < cam->nbufs; i++) {
 256                clear_bit(i, &cam->flags);
 257                clear_bit(CF_FRAME_SOF0 + i, &cam->flags);
 258        }
 259}
 260
 261static inline int mcam_needs_config(struct mcam_camera *cam)
 262{
 263        return test_bit(CF_CONFIG_NEEDED, &cam->flags);
 264}
 265
 266static void mcam_set_config_needed(struct mcam_camera *cam, int needed)
 267{
 268        if (needed)
 269                set_bit(CF_CONFIG_NEEDED, &cam->flags);
 270        else
 271                clear_bit(CF_CONFIG_NEEDED, &cam->flags);
 272}
 273
 274/* ------------------------------------------------------------------- */
 275/*
 276 * Make the controller start grabbing images.  Everything must
 277 * be set up before doing this.
 278 */
 279static void mcam_ctlr_start(struct mcam_camera *cam)
 280{
 281        /* set_bit performs a read, so no other barrier should be
 282           needed here */
 283        mcam_reg_set_bit(cam, REG_CTRL0, C0_ENABLE);
 284}
 285
 286static void mcam_ctlr_stop(struct mcam_camera *cam)
 287{
 288        mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
 289}
 290
 291static void mcam_enable_mipi(struct mcam_camera *mcam)
 292{
 293        /* Using MIPI mode and enable MIPI */
 294        cam_dbg(mcam, "camera: DPHY3=0x%x, DPHY5=0x%x, DPHY6=0x%x\n",
 295                        mcam->dphy[0], mcam->dphy[1], mcam->dphy[2]);
 296        mcam_reg_write(mcam, REG_CSI2_DPHY3, mcam->dphy[0]);
 297        mcam_reg_write(mcam, REG_CSI2_DPHY5, mcam->dphy[1]);
 298        mcam_reg_write(mcam, REG_CSI2_DPHY6, mcam->dphy[2]);
 299
 300        if (!mcam->mipi_enabled) {
 301                if (mcam->lane > 4 || mcam->lane <= 0) {
 302                        cam_warn(mcam, "lane number error\n");
 303                        mcam->lane = 1; /* set the default value */
 304                }
 305                /*
 306                 * 0x41 actives 1 lane
 307                 * 0x43 actives 2 lanes
 308                 * 0x45 actives 3 lanes (never happen)
 309                 * 0x47 actives 4 lanes
 310                 */
 311                mcam_reg_write(mcam, REG_CSI2_CTRL0,
 312                        CSI2_C0_MIPI_EN | CSI2_C0_ACT_LANE(mcam->lane));
 313                mcam_reg_write(mcam, REG_CLKCTRL,
 314                        (mcam->mclk_src << 29) | mcam->mclk_div);
 315
 316                mcam->mipi_enabled = true;
 317        }
 318}
 319
 320static void mcam_disable_mipi(struct mcam_camera *mcam)
 321{
 322        /* Using Parallel mode or disable MIPI */
 323        mcam_reg_write(mcam, REG_CSI2_CTRL0, 0x0);
 324        mcam_reg_write(mcam, REG_CSI2_DPHY3, 0x0);
 325        mcam_reg_write(mcam, REG_CSI2_DPHY5, 0x0);
 326        mcam_reg_write(mcam, REG_CSI2_DPHY6, 0x0);
 327        mcam->mipi_enabled = false;
 328}
 329
 330static bool mcam_fmt_is_planar(__u32 pfmt)
 331{
 332        struct mcam_format_struct *f;
 333
 334        f = mcam_find_format(pfmt);
 335        return f->planar;
 336}
 337
 338static void mcam_write_yuv_bases(struct mcam_camera *cam,
 339                                 unsigned frame, dma_addr_t base)
 340{
 341        struct v4l2_pix_format *fmt = &cam->pix_format;
 342        u32 pixel_count = fmt->width * fmt->height;
 343        dma_addr_t y, u = 0, v = 0;
 344
 345        y = base;
 346
 347        switch (fmt->pixelformat) {
 348        case V4L2_PIX_FMT_YUV420:
 349                u = y + pixel_count;
 350                v = u + pixel_count / 4;
 351                break;
 352        case V4L2_PIX_FMT_YVU420:
 353                v = y + pixel_count;
 354                u = v + pixel_count / 4;
 355                break;
 356        default:
 357                break;
 358        }
 359
 360        mcam_reg_write(cam, REG_Y0BAR + frame * 4, y);
 361        if (mcam_fmt_is_planar(fmt->pixelformat)) {
 362                mcam_reg_write(cam, REG_U0BAR + frame * 4, u);
 363                mcam_reg_write(cam, REG_V0BAR + frame * 4, v);
 364        }
 365}
 366
 367/* ------------------------------------------------------------------- */
 368
 369#ifdef MCAM_MODE_VMALLOC
 370/*
 371 * Code specific to the vmalloc buffer mode.
 372 */
 373
 374/*
 375 * Allocate in-kernel DMA buffers for vmalloc mode.
 376 */
 377static int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
 378{
 379        int i;
 380
 381        mcam_set_config_needed(cam, 1);
 382        if (loadtime)
 383                cam->dma_buf_size = dma_buf_size;
 384        else
 385                cam->dma_buf_size = cam->pix_format.sizeimage;
 386        if (n_dma_bufs > 3)
 387                n_dma_bufs = 3;
 388
 389        cam->nbufs = 0;
 390        for (i = 0; i < n_dma_bufs; i++) {
 391                cam->dma_bufs[i] = dma_alloc_coherent(cam->dev,
 392                                cam->dma_buf_size, cam->dma_handles + i,
 393                                GFP_KERNEL);
 394                if (cam->dma_bufs[i] == NULL) {
 395                        cam_warn(cam, "Failed to allocate DMA buffer\n");
 396                        break;
 397                }
 398                (cam->nbufs)++;
 399        }
 400
 401        switch (cam->nbufs) {
 402        case 1:
 403                dma_free_coherent(cam->dev, cam->dma_buf_size,
 404                                cam->dma_bufs[0], cam->dma_handles[0]);
 405                cam->nbufs = 0;
 406        case 0:
 407                cam_err(cam, "Insufficient DMA buffers, cannot operate\n");
 408                return -ENOMEM;
 409
 410        case 2:
 411                if (n_dma_bufs > 2)
 412                        cam_warn(cam, "Will limp along with only 2 buffers\n");
 413                break;
 414        }
 415        return 0;
 416}
 417
 418static void mcam_free_dma_bufs(struct mcam_camera *cam)
 419{
 420        int i;
 421
 422        for (i = 0; i < cam->nbufs; i++) {
 423                dma_free_coherent(cam->dev, cam->dma_buf_size,
 424                                cam->dma_bufs[i], cam->dma_handles[i]);
 425                cam->dma_bufs[i] = NULL;
 426        }
 427        cam->nbufs = 0;
 428}
 429
 430
 431/*
 432 * Set up DMA buffers when operating in vmalloc mode
 433 */
 434static void mcam_ctlr_dma_vmalloc(struct mcam_camera *cam)
 435{
 436        /*
 437         * Store the first two YUV buffers. Then either
 438         * set the third if it exists, or tell the controller
 439         * to just use two.
 440         */
 441        mcam_write_yuv_bases(cam, 0, cam->dma_handles[0]);
 442        mcam_write_yuv_bases(cam, 1, cam->dma_handles[1]);
 443        if (cam->nbufs > 2) {
 444                mcam_write_yuv_bases(cam, 2, cam->dma_handles[2]);
 445                mcam_reg_clear_bit(cam, REG_CTRL1, C1_TWOBUFS);
 446        } else
 447                mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
 448        if (cam->chip_id == MCAM_CAFE)
 449                mcam_reg_write(cam, REG_UBAR, 0); /* 32 bits only */
 450}
 451
 452/*
 453 * Copy data out to user space in the vmalloc case
 454 */
 455static void mcam_frame_tasklet(unsigned long data)
 456{
 457        struct mcam_camera *cam = (struct mcam_camera *) data;
 458        int i;
 459        unsigned long flags;
 460        struct mcam_vb_buffer *buf;
 461
 462        spin_lock_irqsave(&cam->dev_lock, flags);
 463        for (i = 0; i < cam->nbufs; i++) {
 464                int bufno = cam->next_buf;
 465
 466                if (cam->state != S_STREAMING || bufno < 0)
 467                        break;  /* I/O got stopped */
 468                if (++(cam->next_buf) >= cam->nbufs)
 469                        cam->next_buf = 0;
 470                if (!test_bit(bufno, &cam->flags))
 471                        continue;
 472                if (list_empty(&cam->buffers)) {
 473                        cam->frame_state.singles++;
 474                        break;  /* Leave it valid, hope for better later */
 475                }
 476                cam->frame_state.delivered++;
 477                clear_bit(bufno, &cam->flags);
 478                buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer,
 479                                queue);
 480                list_del_init(&buf->queue);
 481                /*
 482                 * Drop the lock during the big copy.  This *should* be safe...
 483                 */
 484                spin_unlock_irqrestore(&cam->dev_lock, flags);
 485                memcpy(vb2_plane_vaddr(&buf->vb_buf.vb2_buf, 0),
 486                                cam->dma_bufs[bufno],
 487                                cam->pix_format.sizeimage);
 488                mcam_buffer_done(cam, bufno, &buf->vb_buf);
 489                spin_lock_irqsave(&cam->dev_lock, flags);
 490        }
 491        spin_unlock_irqrestore(&cam->dev_lock, flags);
 492}
 493
 494
 495/*
 496 * Make sure our allocated buffers are up to the task.
 497 */
 498static int mcam_check_dma_buffers(struct mcam_camera *cam)
 499{
 500        if (cam->nbufs > 0 && cam->dma_buf_size < cam->pix_format.sizeimage)
 501                        mcam_free_dma_bufs(cam);
 502        if (cam->nbufs == 0)
 503                return mcam_alloc_dma_bufs(cam, 0);
 504        return 0;
 505}
 506
 507static void mcam_vmalloc_done(struct mcam_camera *cam, int frame)
 508{
 509        tasklet_schedule(&cam->s_tasklet);
 510}
 511
 512#else /* MCAM_MODE_VMALLOC */
 513
 514static inline int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
 515{
 516        return 0;
 517}
 518
 519static inline void mcam_free_dma_bufs(struct mcam_camera *cam)
 520{
 521        return;
 522}
 523
 524static inline int mcam_check_dma_buffers(struct mcam_camera *cam)
 525{
 526        return 0;
 527}
 528
 529
 530
 531#endif /* MCAM_MODE_VMALLOC */
 532
 533
 534#ifdef MCAM_MODE_DMA_CONTIG
 535/* ---------------------------------------------------------------------- */
 536/*
 537 * DMA-contiguous code.
 538 */
 539
 540/*
 541 * Set up a contiguous buffer for the given frame.  Here also is where
 542 * the underrun strategy is set: if there is no buffer available, reuse
 543 * the buffer from the other BAR and set the CF_SINGLE_BUFFER flag to
 544 * keep the interrupt handler from giving that buffer back to user
 545 * space.  In this way, we always have a buffer to DMA to and don't
 546 * have to try to play games stopping and restarting the controller.
 547 */
 548static void mcam_set_contig_buffer(struct mcam_camera *cam, int frame)
 549{
 550        struct mcam_vb_buffer *buf;
 551        dma_addr_t dma_handle;
 552        struct vb2_v4l2_buffer *vb;
 553
 554        /*
 555         * If there are no available buffers, go into single mode
 556         */
 557        if (list_empty(&cam->buffers)) {
 558                buf = cam->vb_bufs[frame ^ 0x1];
 559                set_bit(CF_SINGLE_BUFFER, &cam->flags);
 560                cam->frame_state.singles++;
 561        } else {
 562                /*
 563                 * OK, we have a buffer we can use.
 564                 */
 565                buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer,
 566                                        queue);
 567                list_del_init(&buf->queue);
 568                clear_bit(CF_SINGLE_BUFFER, &cam->flags);
 569        }
 570
 571        cam->vb_bufs[frame] = buf;
 572        vb = &buf->vb_buf;
 573
 574        dma_handle = vb2_dma_contig_plane_dma_addr(&vb->vb2_buf, 0);
 575        mcam_write_yuv_bases(cam, frame, dma_handle);
 576}
 577
 578/*
 579 * Initial B_DMA_contig setup.
 580 */
 581static void mcam_ctlr_dma_contig(struct mcam_camera *cam)
 582{
 583        mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
 584        cam->nbufs = 2;
 585        mcam_set_contig_buffer(cam, 0);
 586        mcam_set_contig_buffer(cam, 1);
 587}
 588
 589/*
 590 * Frame completion handling.
 591 */
 592static void mcam_dma_contig_done(struct mcam_camera *cam, int frame)
 593{
 594        struct mcam_vb_buffer *buf = cam->vb_bufs[frame];
 595
 596        if (!test_bit(CF_SINGLE_BUFFER, &cam->flags)) {
 597                cam->frame_state.delivered++;
 598                cam->vb_bufs[frame] = NULL;
 599                mcam_buffer_done(cam, frame, &buf->vb_buf);
 600        }
 601        mcam_set_contig_buffer(cam, frame);
 602}
 603
 604#endif /* MCAM_MODE_DMA_CONTIG */
 605
 606#ifdef MCAM_MODE_DMA_SG
 607/* ---------------------------------------------------------------------- */
 608/*
 609 * Scatter/gather-specific code.
 610 */
 611
 612/*
 613 * Set up the next buffer for S/G I/O; caller should be sure that
 614 * the controller is stopped and a buffer is available.
 615 */
 616static void mcam_sg_next_buffer(struct mcam_camera *cam)
 617{
 618        struct mcam_vb_buffer *buf;
 619
 620        buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, queue);
 621        list_del_init(&buf->queue);
 622        /*
 623         * Very Bad Not Good Things happen if you don't clear
 624         * C1_DESC_ENA before making any descriptor changes.
 625         */
 626        mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_ENA);
 627        mcam_reg_write(cam, REG_DMA_DESC_Y, buf->dma_desc_pa);
 628        mcam_reg_write(cam, REG_DESC_LEN_Y,
 629                        buf->dma_desc_nent*sizeof(struct mcam_dma_desc));
 630        mcam_reg_write(cam, REG_DESC_LEN_U, 0);
 631        mcam_reg_write(cam, REG_DESC_LEN_V, 0);
 632        mcam_reg_set_bit(cam, REG_CTRL1, C1_DESC_ENA);
 633        cam->vb_bufs[0] = buf;
 634}
 635
 636/*
 637 * Initial B_DMA_sg setup
 638 */
 639static void mcam_ctlr_dma_sg(struct mcam_camera *cam)
 640{
 641        /*
 642         * The list-empty condition can hit us at resume time
 643         * if the buffer list was empty when the system was suspended.
 644         */
 645        if (list_empty(&cam->buffers)) {
 646                set_bit(CF_SG_RESTART, &cam->flags);
 647                return;
 648        }
 649
 650        mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_3WORD);
 651        mcam_sg_next_buffer(cam);
 652        cam->nbufs = 3;
 653}
 654
 655
 656/*
 657 * Frame completion with S/G is trickier.  We can't muck with
 658 * a descriptor chain on the fly, since the controller buffers it
 659 * internally.  So we have to actually stop and restart; Marvell
 660 * says this is the way to do it.
 661 *
 662 * Of course, stopping is easier said than done; experience shows
 663 * that the controller can start a frame *after* C0_ENABLE has been
 664 * cleared.  So when running in S/G mode, the controller is "stopped"
 665 * on receipt of the start-of-frame interrupt.  That means we can
 666 * safely change the DMA descriptor array here and restart things
 667 * (assuming there's another buffer waiting to go).
 668 */
 669static void mcam_dma_sg_done(struct mcam_camera *cam, int frame)
 670{
 671        struct mcam_vb_buffer *buf = cam->vb_bufs[0];
 672
 673        /*
 674         * If we're no longer supposed to be streaming, don't do anything.
 675         */
 676        if (cam->state != S_STREAMING)
 677                return;
 678        /*
 679         * If we have another buffer available, put it in and
 680         * restart the engine.
 681         */
 682        if (!list_empty(&cam->buffers)) {
 683                mcam_sg_next_buffer(cam);
 684                mcam_ctlr_start(cam);
 685        /*
 686         * Otherwise set CF_SG_RESTART and the controller will
 687         * be restarted once another buffer shows up.
 688         */
 689        } else {
 690                set_bit(CF_SG_RESTART, &cam->flags);
 691                cam->frame_state.singles++;
 692                cam->vb_bufs[0] = NULL;
 693        }
 694        /*
 695         * Now we can give the completed frame back to user space.
 696         */
 697        cam->frame_state.delivered++;
 698        mcam_buffer_done(cam, frame, &buf->vb_buf);
 699}
 700
 701
 702/*
 703 * Scatter/gather mode requires stopping the controller between
 704 * frames so we can put in a new DMA descriptor array.  If no new
 705 * buffer exists at frame completion, the controller is left stopped;
 706 * this function is charged with gettig things going again.
 707 */
 708static void mcam_sg_restart(struct mcam_camera *cam)
 709{
 710        mcam_ctlr_dma_sg(cam);
 711        mcam_ctlr_start(cam);
 712        clear_bit(CF_SG_RESTART, &cam->flags);
 713}
 714
 715#else /* MCAM_MODE_DMA_SG */
 716
 717static inline void mcam_sg_restart(struct mcam_camera *cam)
 718{
 719        return;
 720}
 721
 722#endif /* MCAM_MODE_DMA_SG */
 723
 724/* ---------------------------------------------------------------------- */
 725/*
 726 * Buffer-mode-independent controller code.
 727 */
 728
 729/*
 730 * Image format setup
 731 */
 732static void mcam_ctlr_image(struct mcam_camera *cam)
 733{
 734        struct v4l2_pix_format *fmt = &cam->pix_format;
 735        u32 widthy = 0, widthuv = 0, imgsz_h, imgsz_w;
 736
 737        cam_dbg(cam, "camera: bytesperline = %d; height = %d\n",
 738                fmt->bytesperline, fmt->sizeimage / fmt->bytesperline);
 739        imgsz_h = (fmt->height << IMGSZ_V_SHIFT) & IMGSZ_V_MASK;
 740        imgsz_w = (fmt->width * 2) & IMGSZ_H_MASK;
 741
 742        switch (fmt->pixelformat) {
 743        case V4L2_PIX_FMT_YUYV:
 744        case V4L2_PIX_FMT_YVYU:
 745                widthy = fmt->width * 2;
 746                widthuv = 0;
 747                break;
 748        case V4L2_PIX_FMT_YUV420:
 749        case V4L2_PIX_FMT_YVU420:
 750                widthy = fmt->width;
 751                widthuv = fmt->width / 2;
 752                break;
 753        default:
 754                widthy = fmt->bytesperline;
 755                widthuv = 0;
 756                break;
 757        }
 758
 759        mcam_reg_write_mask(cam, REG_IMGPITCH, widthuv << 16 | widthy,
 760                        IMGP_YP_MASK | IMGP_UVP_MASK);
 761        mcam_reg_write(cam, REG_IMGSIZE, imgsz_h | imgsz_w);
 762        mcam_reg_write(cam, REG_IMGOFFSET, 0x0);
 763
 764        /*
 765         * Tell the controller about the image format we are using.
 766         */
 767        switch (fmt->pixelformat) {
 768        case V4L2_PIX_FMT_YUV420:
 769        case V4L2_PIX_FMT_YVU420:
 770                mcam_reg_write_mask(cam, REG_CTRL0,
 771                        C0_DF_YUV | C0_YUV_420PL | C0_YUVE_VYUY, C0_DF_MASK);
 772                break;
 773        case V4L2_PIX_FMT_YUYV:
 774                mcam_reg_write_mask(cam, REG_CTRL0,
 775                        C0_DF_YUV | C0_YUV_PACKED | C0_YUVE_NOSWAP, C0_DF_MASK);
 776                break;
 777        case V4L2_PIX_FMT_YVYU:
 778                mcam_reg_write_mask(cam, REG_CTRL0,
 779                        C0_DF_YUV | C0_YUV_PACKED | C0_YUVE_SWAP24, C0_DF_MASK);
 780                break;
 781        case V4L2_PIX_FMT_XRGB444:
 782                mcam_reg_write_mask(cam, REG_CTRL0,
 783                        C0_DF_RGB | C0_RGBF_444 | C0_RGB4_XBGR, C0_DF_MASK);
 784                break;
 785        case V4L2_PIX_FMT_RGB565:
 786                mcam_reg_write_mask(cam, REG_CTRL0,
 787                        C0_DF_RGB | C0_RGBF_565 | C0_RGB5_BGGR, C0_DF_MASK);
 788                break;
 789        case V4L2_PIX_FMT_SBGGR8:
 790                mcam_reg_write_mask(cam, REG_CTRL0,
 791                        C0_DF_RGB | C0_RGB5_GRBG, C0_DF_MASK);
 792                break;
 793        default:
 794                cam_err(cam, "camera: unknown format: %#x\n", fmt->pixelformat);
 795                break;
 796        }
 797
 798        /*
 799         * Make sure it knows we want to use hsync/vsync.
 800         */
 801        mcam_reg_write_mask(cam, REG_CTRL0, C0_SIF_HVSYNC, C0_SIFM_MASK);
 802        /*
 803         * This field controls the generation of EOF(DVP only)
 804         */
 805        if (cam->bus_type != V4L2_MBUS_CSI2)
 806                mcam_reg_set_bit(cam, REG_CTRL0,
 807                                C0_EOF_VSYNC | C0_VEDGE_CTRL);
 808}
 809
 810
 811/*
 812 * Configure the controller for operation; caller holds the
 813 * device mutex.
 814 */
 815static int mcam_ctlr_configure(struct mcam_camera *cam)
 816{
 817        unsigned long flags;
 818
 819        spin_lock_irqsave(&cam->dev_lock, flags);
 820        clear_bit(CF_SG_RESTART, &cam->flags);
 821        cam->dma_setup(cam);
 822        mcam_ctlr_image(cam);
 823        mcam_set_config_needed(cam, 0);
 824        spin_unlock_irqrestore(&cam->dev_lock, flags);
 825        return 0;
 826}
 827
 828static void mcam_ctlr_irq_enable(struct mcam_camera *cam)
 829{
 830        /*
 831         * Clear any pending interrupts, since we do not
 832         * expect to have I/O active prior to enabling.
 833         */
 834        mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS);
 835        mcam_reg_set_bit(cam, REG_IRQMASK, FRAMEIRQS);
 836}
 837
 838static void mcam_ctlr_irq_disable(struct mcam_camera *cam)
 839{
 840        mcam_reg_clear_bit(cam, REG_IRQMASK, FRAMEIRQS);
 841}
 842
 843
 844
 845static void mcam_ctlr_init(struct mcam_camera *cam)
 846{
 847        unsigned long flags;
 848
 849        spin_lock_irqsave(&cam->dev_lock, flags);
 850        /*
 851         * Make sure it's not powered down.
 852         */
 853        mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
 854        /*
 855         * Turn off the enable bit.  It sure should be off anyway,
 856         * but it's good to be sure.
 857         */
 858        mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
 859        /*
 860         * Clock the sensor appropriately.  Controller clock should
 861         * be 48MHz, sensor "typical" value is half that.
 862         */
 863        mcam_reg_write_mask(cam, REG_CLKCTRL, 2, CLK_DIV_MASK);
 864        spin_unlock_irqrestore(&cam->dev_lock, flags);
 865}
 866
 867
 868/*
 869 * Stop the controller, and don't return until we're really sure that no
 870 * further DMA is going on.
 871 */
 872static void mcam_ctlr_stop_dma(struct mcam_camera *cam)
 873{
 874        unsigned long flags;
 875
 876        /*
 877         * Theory: stop the camera controller (whether it is operating
 878         * or not).  Delay briefly just in case we race with the SOF
 879         * interrupt, then wait until no DMA is active.
 880         */
 881        spin_lock_irqsave(&cam->dev_lock, flags);
 882        clear_bit(CF_SG_RESTART, &cam->flags);
 883        mcam_ctlr_stop(cam);
 884        cam->state = S_IDLE;
 885        spin_unlock_irqrestore(&cam->dev_lock, flags);
 886        /*
 887         * This is a brutally long sleep, but experience shows that
 888         * it can take the controller a while to get the message that
 889         * it needs to stop grabbing frames.  In particular, we can
 890         * sometimes (on mmp) get a frame at the end WITHOUT the
 891         * start-of-frame indication.
 892         */
 893        msleep(150);
 894        if (test_bit(CF_DMA_ACTIVE, &cam->flags))
 895                cam_err(cam, "Timeout waiting for DMA to end\n");
 896                /* This would be bad news - what now? */
 897        spin_lock_irqsave(&cam->dev_lock, flags);
 898        mcam_ctlr_irq_disable(cam);
 899        spin_unlock_irqrestore(&cam->dev_lock, flags);
 900}
 901
 902/*
 903 * Power up and down.
 904 */
 905static int mcam_ctlr_power_up(struct mcam_camera *cam)
 906{
 907        unsigned long flags;
 908        int ret;
 909
 910        spin_lock_irqsave(&cam->dev_lock, flags);
 911        ret = cam->plat_power_up(cam);
 912        if (ret) {
 913                spin_unlock_irqrestore(&cam->dev_lock, flags);
 914                return ret;
 915        }
 916        mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
 917        spin_unlock_irqrestore(&cam->dev_lock, flags);
 918        msleep(5); /* Just to be sure */
 919        return 0;
 920}
 921
 922static void mcam_ctlr_power_down(struct mcam_camera *cam)
 923{
 924        unsigned long flags;
 925
 926        spin_lock_irqsave(&cam->dev_lock, flags);
 927        /*
 928         * School of hard knocks department: be sure we do any register
 929         * twiddling on the controller *before* calling the platform
 930         * power down routine.
 931         */
 932        mcam_reg_set_bit(cam, REG_CTRL1, C1_PWRDWN);
 933        cam->plat_power_down(cam);
 934        spin_unlock_irqrestore(&cam->dev_lock, flags);
 935}
 936
 937/* -------------------------------------------------------------------- */
 938/*
 939 * Communications with the sensor.
 940 */
 941
 942static int __mcam_cam_reset(struct mcam_camera *cam)
 943{
 944        return sensor_call(cam, core, reset, 0);
 945}
 946
 947/*
 948 * We have found the sensor on the i2c.  Let's try to have a
 949 * conversation.
 950 */
 951static int mcam_cam_init(struct mcam_camera *cam)
 952{
 953        int ret;
 954
 955        if (cam->state != S_NOTREADY)
 956                cam_warn(cam, "Cam init with device in funky state %d",
 957                                cam->state);
 958        ret = __mcam_cam_reset(cam);
 959        /* Get/set parameters? */
 960        cam->state = S_IDLE;
 961        mcam_ctlr_power_down(cam);
 962        return ret;
 963}
 964
 965/*
 966 * Configure the sensor to match the parameters we have.  Caller should
 967 * hold s_mutex
 968 */
 969static int mcam_cam_set_flip(struct mcam_camera *cam)
 970{
 971        struct v4l2_control ctrl;
 972
 973        memset(&ctrl, 0, sizeof(ctrl));
 974        ctrl.id = V4L2_CID_VFLIP;
 975        ctrl.value = flip;
 976        return v4l2_s_ctrl(NULL, cam->sensor->ctrl_handler, &ctrl);
 977}
 978
 979
 980static int mcam_cam_configure(struct mcam_camera *cam)
 981{
 982        struct v4l2_subdev_format format = {
 983                .which = V4L2_SUBDEV_FORMAT_ACTIVE,
 984        };
 985        int ret;
 986
 987        v4l2_fill_mbus_format(&format.format, &cam->pix_format, cam->mbus_code);
 988        ret = sensor_call(cam, core, init, 0);
 989        if (ret == 0)
 990                ret = sensor_call(cam, pad, set_fmt, NULL, &format);
 991        /*
 992         * OV7670 does weird things if flip is set *before* format...
 993         */
 994        ret += mcam_cam_set_flip(cam);
 995        return ret;
 996}
 997
 998/*
 999 * Get everything ready, and start grabbing frames.
1000 */
1001static int mcam_read_setup(struct mcam_camera *cam)
1002{
1003        int ret;
1004        unsigned long flags;
1005
1006        /*
1007         * Configuration.  If we still don't have DMA buffers,
1008         * make one last, desperate attempt.
1009         */
1010        if (cam->buffer_mode == B_vmalloc && cam->nbufs == 0 &&
1011                        mcam_alloc_dma_bufs(cam, 0))
1012                return -ENOMEM;
1013
1014        if (mcam_needs_config(cam)) {
1015                mcam_cam_configure(cam);
1016                ret = mcam_ctlr_configure(cam);
1017                if (ret)
1018                        return ret;
1019        }
1020
1021        /*
1022         * Turn it loose.
1023         */
1024        spin_lock_irqsave(&cam->dev_lock, flags);
1025        clear_bit(CF_DMA_ACTIVE, &cam->flags);
1026        mcam_reset_buffers(cam);
1027        /*
1028         * Update CSI2_DPHY value
1029         */
1030        if (cam->calc_dphy)
1031                cam->calc_dphy(cam);
1032        cam_dbg(cam, "camera: DPHY sets: dphy3=0x%x, dphy5=0x%x, dphy6=0x%x\n",
1033                        cam->dphy[0], cam->dphy[1], cam->dphy[2]);
1034        if (cam->bus_type == V4L2_MBUS_CSI2)
1035                mcam_enable_mipi(cam);
1036        else
1037                mcam_disable_mipi(cam);
1038        mcam_ctlr_irq_enable(cam);
1039        cam->state = S_STREAMING;
1040        if (!test_bit(CF_SG_RESTART, &cam->flags))
1041                mcam_ctlr_start(cam);
1042        spin_unlock_irqrestore(&cam->dev_lock, flags);
1043        return 0;
1044}
1045
1046/* ----------------------------------------------------------------------- */
1047/*
1048 * Videobuf2 interface code.
1049 */
1050
1051static int mcam_vb_queue_setup(struct vb2_queue *vq,
1052                unsigned int *nbufs,
1053                unsigned int *num_planes, unsigned int sizes[],
1054                struct device *alloc_devs[])
1055{
1056        struct mcam_camera *cam = vb2_get_drv_priv(vq);
1057        int minbufs = (cam->buffer_mode == B_DMA_contig) ? 3 : 2;
1058        unsigned size = cam->pix_format.sizeimage;
1059
1060        if (*nbufs < minbufs)
1061                *nbufs = minbufs;
1062
1063        if (*num_planes)
1064                return sizes[0] < size ? -EINVAL : 0;
1065        sizes[0] = size;
1066        *num_planes = 1; /* Someday we have to support planar formats... */
1067        return 0;
1068}
1069
1070
1071static void mcam_vb_buf_queue(struct vb2_buffer *vb)
1072{
1073        struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1074        struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf);
1075        struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1076        unsigned long flags;
1077        int start;
1078
1079        spin_lock_irqsave(&cam->dev_lock, flags);
1080        start = (cam->state == S_BUFWAIT) && !list_empty(&cam->buffers);
1081        list_add(&mvb->queue, &cam->buffers);
1082        if (cam->state == S_STREAMING && test_bit(CF_SG_RESTART, &cam->flags))
1083                mcam_sg_restart(cam);
1084        spin_unlock_irqrestore(&cam->dev_lock, flags);
1085        if (start)
1086                mcam_read_setup(cam);
1087}
1088
1089static void mcam_vb_requeue_bufs(struct vb2_queue *vq,
1090                                 enum vb2_buffer_state state)
1091{
1092        struct mcam_camera *cam = vb2_get_drv_priv(vq);
1093        struct mcam_vb_buffer *buf, *node;
1094        unsigned long flags;
1095        unsigned i;
1096
1097        spin_lock_irqsave(&cam->dev_lock, flags);
1098        list_for_each_entry_safe(buf, node, &cam->buffers, queue) {
1099                vb2_buffer_done(&buf->vb_buf.vb2_buf, state);
1100                list_del(&buf->queue);
1101        }
1102        for (i = 0; i < MAX_DMA_BUFS; i++) {
1103                buf = cam->vb_bufs[i];
1104
1105                if (buf) {
1106                        vb2_buffer_done(&buf->vb_buf.vb2_buf, state);
1107                        cam->vb_bufs[i] = NULL;
1108                }
1109        }
1110        spin_unlock_irqrestore(&cam->dev_lock, flags);
1111}
1112
1113/*
1114 * These need to be called with the mutex held from vb2
1115 */
1116static int mcam_vb_start_streaming(struct vb2_queue *vq, unsigned int count)
1117{
1118        struct mcam_camera *cam = vb2_get_drv_priv(vq);
1119        unsigned int frame;
1120        int ret;
1121
1122        if (cam->state != S_IDLE) {
1123                mcam_vb_requeue_bufs(vq, VB2_BUF_STATE_QUEUED);
1124                return -EINVAL;
1125        }
1126        cam->frame_state.frames = 0;
1127        cam->frame_state.singles = 0;
1128        cam->frame_state.delivered = 0;
1129        cam->sequence = 0;
1130        /*
1131         * Videobuf2 sneakily hoards all the buffers and won't
1132         * give them to us until *after* streaming starts.  But
1133         * we can't actually start streaming until we have a
1134         * destination.  So go into a wait state and hope they
1135         * give us buffers soon.
1136         */
1137        if (cam->buffer_mode != B_vmalloc && list_empty(&cam->buffers)) {
1138                cam->state = S_BUFWAIT;
1139                return 0;
1140        }
1141
1142        /*
1143         * Ensure clear the left over frame flags
1144         * before every really start streaming
1145         */
1146        for (frame = 0; frame < cam->nbufs; frame++)
1147                clear_bit(CF_FRAME_SOF0 + frame, &cam->flags);
1148
1149        ret = mcam_read_setup(cam);
1150        if (ret)
1151                mcam_vb_requeue_bufs(vq, VB2_BUF_STATE_QUEUED);
1152        return ret;
1153}
1154
1155static void mcam_vb_stop_streaming(struct vb2_queue *vq)
1156{
1157        struct mcam_camera *cam = vb2_get_drv_priv(vq);
1158
1159        cam_dbg(cam, "stop_streaming: %d frames, %d singles, %d delivered\n",
1160                        cam->frame_state.frames, cam->frame_state.singles,
1161                        cam->frame_state.delivered);
1162        if (cam->state == S_BUFWAIT) {
1163                /* They never gave us buffers */
1164                cam->state = S_IDLE;
1165                return;
1166        }
1167        if (cam->state != S_STREAMING)
1168                return;
1169        mcam_ctlr_stop_dma(cam);
1170        /*
1171         * Reset the CCIC PHY after stopping streaming,
1172         * otherwise, the CCIC may be unstable.
1173         */
1174        if (cam->ctlr_reset)
1175                cam->ctlr_reset(cam);
1176        /*
1177         * VB2 reclaims the buffers, so we need to forget
1178         * about them.
1179         */
1180        mcam_vb_requeue_bufs(vq, VB2_BUF_STATE_ERROR);
1181}
1182
1183
1184static const struct vb2_ops mcam_vb2_ops = {
1185        .queue_setup            = mcam_vb_queue_setup,
1186        .buf_queue              = mcam_vb_buf_queue,
1187        .start_streaming        = mcam_vb_start_streaming,
1188        .stop_streaming         = mcam_vb_stop_streaming,
1189        .wait_prepare           = vb2_ops_wait_prepare,
1190        .wait_finish            = vb2_ops_wait_finish,
1191};
1192
1193
1194#ifdef MCAM_MODE_DMA_SG
1195/*
1196 * Scatter/gather mode uses all of the above functions plus a
1197 * few extras to deal with DMA mapping.
1198 */
1199static int mcam_vb_sg_buf_init(struct vb2_buffer *vb)
1200{
1201        struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1202        struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf);
1203        struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1204        int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1205
1206        mvb->dma_desc = dma_alloc_coherent(cam->dev,
1207                        ndesc * sizeof(struct mcam_dma_desc),
1208                        &mvb->dma_desc_pa, GFP_KERNEL);
1209        if (mvb->dma_desc == NULL) {
1210                cam_err(cam, "Unable to get DMA descriptor array\n");
1211                return -ENOMEM;
1212        }
1213        return 0;
1214}
1215
1216static int mcam_vb_sg_buf_prepare(struct vb2_buffer *vb)
1217{
1218        struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1219        struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf);
1220        struct sg_table *sg_table = vb2_dma_sg_plane_desc(vb, 0);
1221        struct mcam_dma_desc *desc = mvb->dma_desc;
1222        struct scatterlist *sg;
1223        int i;
1224
1225        for_each_sg(sg_table->sgl, sg, sg_table->nents, i) {
1226                desc->dma_addr = sg_dma_address(sg);
1227                desc->segment_len = sg_dma_len(sg);
1228                desc++;
1229        }
1230        return 0;
1231}
1232
1233static void mcam_vb_sg_buf_cleanup(struct vb2_buffer *vb)
1234{
1235        struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1236        struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1237        struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf);
1238        int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1239
1240        dma_free_coherent(cam->dev, ndesc * sizeof(struct mcam_dma_desc),
1241                        mvb->dma_desc, mvb->dma_desc_pa);
1242}
1243
1244
1245static const struct vb2_ops mcam_vb2_sg_ops = {
1246        .queue_setup            = mcam_vb_queue_setup,
1247        .buf_init               = mcam_vb_sg_buf_init,
1248        .buf_prepare            = mcam_vb_sg_buf_prepare,
1249        .buf_queue              = mcam_vb_buf_queue,
1250        .buf_cleanup            = mcam_vb_sg_buf_cleanup,
1251        .start_streaming        = mcam_vb_start_streaming,
1252        .stop_streaming         = mcam_vb_stop_streaming,
1253        .wait_prepare           = vb2_ops_wait_prepare,
1254        .wait_finish            = vb2_ops_wait_finish,
1255};
1256
1257#endif /* MCAM_MODE_DMA_SG */
1258
1259static int mcam_setup_vb2(struct mcam_camera *cam)
1260{
1261        struct vb2_queue *vq = &cam->vb_queue;
1262
1263        memset(vq, 0, sizeof(*vq));
1264        vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1265        vq->drv_priv = cam;
1266        vq->lock = &cam->s_mutex;
1267        vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1268        vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
1269        vq->buf_struct_size = sizeof(struct mcam_vb_buffer);
1270        vq->dev = cam->dev;
1271        INIT_LIST_HEAD(&cam->buffers);
1272        switch (cam->buffer_mode) {
1273        case B_DMA_contig:
1274#ifdef MCAM_MODE_DMA_CONTIG
1275                vq->ops = &mcam_vb2_ops;
1276                vq->mem_ops = &vb2_dma_contig_memops;
1277                cam->dma_setup = mcam_ctlr_dma_contig;
1278                cam->frame_complete = mcam_dma_contig_done;
1279#endif
1280                break;
1281        case B_DMA_sg:
1282#ifdef MCAM_MODE_DMA_SG
1283                vq->ops = &mcam_vb2_sg_ops;
1284                vq->mem_ops = &vb2_dma_sg_memops;
1285                cam->dma_setup = mcam_ctlr_dma_sg;
1286                cam->frame_complete = mcam_dma_sg_done;
1287#endif
1288                break;
1289        case B_vmalloc:
1290#ifdef MCAM_MODE_VMALLOC
1291                tasklet_init(&cam->s_tasklet, mcam_frame_tasklet,
1292                                (unsigned long) cam);
1293                vq->ops = &mcam_vb2_ops;
1294                vq->mem_ops = &vb2_vmalloc_memops;
1295                cam->dma_setup = mcam_ctlr_dma_vmalloc;
1296                cam->frame_complete = mcam_vmalloc_done;
1297#endif
1298                break;
1299        }
1300        return vb2_queue_init(vq);
1301}
1302
1303
1304/* ---------------------------------------------------------------------- */
1305/*
1306 * The long list of V4L2 ioctl() operations.
1307 */
1308
1309static int mcam_vidioc_querycap(struct file *file, void *priv,
1310                struct v4l2_capability *cap)
1311{
1312        struct mcam_camera *cam = video_drvdata(file);
1313
1314        strcpy(cap->driver, "marvell_ccic");
1315        strcpy(cap->card, "marvell_ccic");
1316        strlcpy(cap->bus_info, cam->bus_info, sizeof(cap->bus_info));
1317        cap->device_caps = V4L2_CAP_VIDEO_CAPTURE |
1318                V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
1319        cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1320        return 0;
1321}
1322
1323
1324static int mcam_vidioc_enum_fmt_vid_cap(struct file *filp,
1325                void *priv, struct v4l2_fmtdesc *fmt)
1326{
1327        if (fmt->index >= N_MCAM_FMTS)
1328                return -EINVAL;
1329        strlcpy(fmt->description, mcam_formats[fmt->index].desc,
1330                        sizeof(fmt->description));
1331        fmt->pixelformat = mcam_formats[fmt->index].pixelformat;
1332        return 0;
1333}
1334
1335static int mcam_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1336                struct v4l2_format *fmt)
1337{
1338        struct mcam_camera *cam = video_drvdata(filp);
1339        struct mcam_format_struct *f;
1340        struct v4l2_pix_format *pix = &fmt->fmt.pix;
1341        struct v4l2_subdev_pad_config pad_cfg;
1342        struct v4l2_subdev_format format = {
1343                .which = V4L2_SUBDEV_FORMAT_TRY,
1344        };
1345        int ret;
1346
1347        f = mcam_find_format(pix->pixelformat);
1348        pix->pixelformat = f->pixelformat;
1349        v4l2_fill_mbus_format(&format.format, pix, f->mbus_code);
1350        ret = sensor_call(cam, pad, set_fmt, &pad_cfg, &format);
1351        v4l2_fill_pix_format(pix, &format.format);
1352        pix->bytesperline = pix->width * f->bpp;
1353        switch (f->pixelformat) {
1354        case V4L2_PIX_FMT_YUV420:
1355        case V4L2_PIX_FMT_YVU420:
1356                pix->sizeimage = pix->height * pix->bytesperline * 3 / 2;
1357                break;
1358        default:
1359                pix->sizeimage = pix->height * pix->bytesperline;
1360                break;
1361        }
1362        pix->colorspace = V4L2_COLORSPACE_SRGB;
1363        return ret;
1364}
1365
1366static int mcam_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1367                struct v4l2_format *fmt)
1368{
1369        struct mcam_camera *cam = video_drvdata(filp);
1370        struct mcam_format_struct *f;
1371        int ret;
1372
1373        /*
1374         * Can't do anything if the device is not idle
1375         * Also can't if there are streaming buffers in place.
1376         */
1377        if (cam->state != S_IDLE || vb2_is_busy(&cam->vb_queue))
1378                return -EBUSY;
1379
1380        f = mcam_find_format(fmt->fmt.pix.pixelformat);
1381
1382        /*
1383         * See if the formatting works in principle.
1384         */
1385        ret = mcam_vidioc_try_fmt_vid_cap(filp, priv, fmt);
1386        if (ret)
1387                return ret;
1388        /*
1389         * Now we start to change things for real, so let's do it
1390         * under lock.
1391         */
1392        cam->pix_format = fmt->fmt.pix;
1393        cam->mbus_code = f->mbus_code;
1394
1395        /*
1396         * Make sure we have appropriate DMA buffers.
1397         */
1398        if (cam->buffer_mode == B_vmalloc) {
1399                ret = mcam_check_dma_buffers(cam);
1400                if (ret)
1401                        goto out;
1402        }
1403        mcam_set_config_needed(cam, 1);
1404out:
1405        return ret;
1406}
1407
1408/*
1409 * Return our stored notion of how the camera is/should be configured.
1410 * The V4l2 spec wants us to be smarter, and actually get this from
1411 * the camera (and not mess with it at open time).  Someday.
1412 */
1413static int mcam_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1414                struct v4l2_format *f)
1415{
1416        struct mcam_camera *cam = video_drvdata(filp);
1417
1418        f->fmt.pix = cam->pix_format;
1419        return 0;
1420}
1421
1422/*
1423 * We only have one input - the sensor - so minimize the nonsense here.
1424 */
1425static int mcam_vidioc_enum_input(struct file *filp, void *priv,
1426                struct v4l2_input *input)
1427{
1428        if (input->index != 0)
1429                return -EINVAL;
1430
1431        input->type = V4L2_INPUT_TYPE_CAMERA;
1432        strcpy(input->name, "Camera");
1433        return 0;
1434}
1435
1436static int mcam_vidioc_g_input(struct file *filp, void *priv, unsigned int *i)
1437{
1438        *i = 0;
1439        return 0;
1440}
1441
1442static int mcam_vidioc_s_input(struct file *filp, void *priv, unsigned int i)
1443{
1444        if (i != 0)
1445                return -EINVAL;
1446        return 0;
1447}
1448
1449/*
1450 * G/S_PARM.  Most of this is done by the sensor, but we are
1451 * the level which controls the number of read buffers.
1452 */
1453static int mcam_vidioc_g_parm(struct file *filp, void *priv,
1454                struct v4l2_streamparm *parms)
1455{
1456        struct mcam_camera *cam = video_drvdata(filp);
1457        int ret;
1458
1459        ret = sensor_call(cam, video, g_parm, parms);
1460        parms->parm.capture.readbuffers = n_dma_bufs;
1461        return ret;
1462}
1463
1464static int mcam_vidioc_s_parm(struct file *filp, void *priv,
1465                struct v4l2_streamparm *parms)
1466{
1467        struct mcam_camera *cam = video_drvdata(filp);
1468        int ret;
1469
1470        ret = sensor_call(cam, video, s_parm, parms);
1471        parms->parm.capture.readbuffers = n_dma_bufs;
1472        return ret;
1473}
1474
1475static int mcam_vidioc_enum_framesizes(struct file *filp, void *priv,
1476                struct v4l2_frmsizeenum *sizes)
1477{
1478        struct mcam_camera *cam = video_drvdata(filp);
1479        struct mcam_format_struct *f;
1480        struct v4l2_subdev_frame_size_enum fse = {
1481                .index = sizes->index,
1482                .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1483        };
1484        int ret;
1485
1486        f = mcam_find_format(sizes->pixel_format);
1487        if (f->pixelformat != sizes->pixel_format)
1488                return -EINVAL;
1489        fse.code = f->mbus_code;
1490        ret = sensor_call(cam, pad, enum_frame_size, NULL, &fse);
1491        if (ret)
1492                return ret;
1493        if (fse.min_width == fse.max_width &&
1494            fse.min_height == fse.max_height) {
1495                sizes->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1496                sizes->discrete.width = fse.min_width;
1497                sizes->discrete.height = fse.min_height;
1498                return 0;
1499        }
1500        sizes->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
1501        sizes->stepwise.min_width = fse.min_width;
1502        sizes->stepwise.max_width = fse.max_width;
1503        sizes->stepwise.min_height = fse.min_height;
1504        sizes->stepwise.max_height = fse.max_height;
1505        sizes->stepwise.step_width = 1;
1506        sizes->stepwise.step_height = 1;
1507        return 0;
1508}
1509
1510static int mcam_vidioc_enum_frameintervals(struct file *filp, void *priv,
1511                struct v4l2_frmivalenum *interval)
1512{
1513        struct mcam_camera *cam = video_drvdata(filp);
1514        struct mcam_format_struct *f;
1515        struct v4l2_subdev_frame_interval_enum fie = {
1516                .index = interval->index,
1517                .width = interval->width,
1518                .height = interval->height,
1519                .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1520        };
1521        int ret;
1522
1523        f = mcam_find_format(interval->pixel_format);
1524        if (f->pixelformat != interval->pixel_format)
1525                return -EINVAL;
1526        fie.code = f->mbus_code;
1527        ret = sensor_call(cam, pad, enum_frame_interval, NULL, &fie);
1528        if (ret)
1529                return ret;
1530        interval->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1531        interval->discrete = fie.interval;
1532        return 0;
1533}
1534
1535#ifdef CONFIG_VIDEO_ADV_DEBUG
1536static int mcam_vidioc_g_register(struct file *file, void *priv,
1537                struct v4l2_dbg_register *reg)
1538{
1539        struct mcam_camera *cam = video_drvdata(file);
1540
1541        if (reg->reg > cam->regs_size - 4)
1542                return -EINVAL;
1543        reg->val = mcam_reg_read(cam, reg->reg);
1544        reg->size = 4;
1545        return 0;
1546}
1547
1548static int mcam_vidioc_s_register(struct file *file, void *priv,
1549                const struct v4l2_dbg_register *reg)
1550{
1551        struct mcam_camera *cam = video_drvdata(file);
1552
1553        if (reg->reg > cam->regs_size - 4)
1554                return -EINVAL;
1555        mcam_reg_write(cam, reg->reg, reg->val);
1556        return 0;
1557}
1558#endif
1559
1560static const struct v4l2_ioctl_ops mcam_v4l_ioctl_ops = {
1561        .vidioc_querycap        = mcam_vidioc_querycap,
1562        .vidioc_enum_fmt_vid_cap = mcam_vidioc_enum_fmt_vid_cap,
1563        .vidioc_try_fmt_vid_cap = mcam_vidioc_try_fmt_vid_cap,
1564        .vidioc_s_fmt_vid_cap   = mcam_vidioc_s_fmt_vid_cap,
1565        .vidioc_g_fmt_vid_cap   = mcam_vidioc_g_fmt_vid_cap,
1566        .vidioc_enum_input      = mcam_vidioc_enum_input,
1567        .vidioc_g_input         = mcam_vidioc_g_input,
1568        .vidioc_s_input         = mcam_vidioc_s_input,
1569        .vidioc_reqbufs         = vb2_ioctl_reqbufs,
1570        .vidioc_create_bufs     = vb2_ioctl_create_bufs,
1571        .vidioc_querybuf        = vb2_ioctl_querybuf,
1572        .vidioc_qbuf            = vb2_ioctl_qbuf,
1573        .vidioc_dqbuf           = vb2_ioctl_dqbuf,
1574        .vidioc_expbuf          = vb2_ioctl_expbuf,
1575        .vidioc_streamon        = vb2_ioctl_streamon,
1576        .vidioc_streamoff       = vb2_ioctl_streamoff,
1577        .vidioc_g_parm          = mcam_vidioc_g_parm,
1578        .vidioc_s_parm          = mcam_vidioc_s_parm,
1579        .vidioc_enum_framesizes = mcam_vidioc_enum_framesizes,
1580        .vidioc_enum_frameintervals = mcam_vidioc_enum_frameintervals,
1581        .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1582        .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1583#ifdef CONFIG_VIDEO_ADV_DEBUG
1584        .vidioc_g_register      = mcam_vidioc_g_register,
1585        .vidioc_s_register      = mcam_vidioc_s_register,
1586#endif
1587};
1588
1589/* ---------------------------------------------------------------------- */
1590/*
1591 * Our various file operations.
1592 */
1593static int mcam_v4l_open(struct file *filp)
1594{
1595        struct mcam_camera *cam = video_drvdata(filp);
1596        int ret;
1597
1598        mutex_lock(&cam->s_mutex);
1599        ret = v4l2_fh_open(filp);
1600        if (ret)
1601                goto out;
1602        if (v4l2_fh_is_singular_file(filp)) {
1603                ret = mcam_ctlr_power_up(cam);
1604                if (ret)
1605                        goto out;
1606                __mcam_cam_reset(cam);
1607                mcam_set_config_needed(cam, 1);
1608        }
1609out:
1610        mutex_unlock(&cam->s_mutex);
1611        if (ret)
1612                v4l2_fh_release(filp);
1613        return ret;
1614}
1615
1616
1617static int mcam_v4l_release(struct file *filp)
1618{
1619        struct mcam_camera *cam = video_drvdata(filp);
1620        bool last_open;
1621
1622        mutex_lock(&cam->s_mutex);
1623        last_open = v4l2_fh_is_singular_file(filp);
1624        _vb2_fop_release(filp, NULL);
1625        if (last_open) {
1626                mcam_disable_mipi(cam);
1627                mcam_ctlr_power_down(cam);
1628                if (cam->buffer_mode == B_vmalloc && alloc_bufs_at_read)
1629                        mcam_free_dma_bufs(cam);
1630        }
1631
1632        mutex_unlock(&cam->s_mutex);
1633        return 0;
1634}
1635
1636static const struct v4l2_file_operations mcam_v4l_fops = {
1637        .owner = THIS_MODULE,
1638        .open = mcam_v4l_open,
1639        .release = mcam_v4l_release,
1640        .read = vb2_fop_read,
1641        .poll = vb2_fop_poll,
1642        .mmap = vb2_fop_mmap,
1643        .unlocked_ioctl = video_ioctl2,
1644};
1645
1646
1647/*
1648 * This template device holds all of those v4l2 methods; we
1649 * clone it for specific real devices.
1650 */
1651static struct video_device mcam_v4l_template = {
1652        .name = "mcam",
1653        .fops = &mcam_v4l_fops,
1654        .ioctl_ops = &mcam_v4l_ioctl_ops,
1655        .release = video_device_release_empty,
1656};
1657
1658/* ---------------------------------------------------------------------- */
1659/*
1660 * Interrupt handler stuff
1661 */
1662static void mcam_frame_complete(struct mcam_camera *cam, int frame)
1663{
1664        /*
1665         * Basic frame housekeeping.
1666         */
1667        set_bit(frame, &cam->flags);
1668        clear_bit(CF_DMA_ACTIVE, &cam->flags);
1669        cam->next_buf = frame;
1670        cam->buf_seq[frame] = cam->sequence++;
1671        cam->frame_state.frames++;
1672        /*
1673         * "This should never happen"
1674         */
1675        if (cam->state != S_STREAMING)
1676                return;
1677        /*
1678         * Process the frame and set up the next one.
1679         */
1680        cam->frame_complete(cam, frame);
1681}
1682
1683
1684/*
1685 * The interrupt handler; this needs to be called from the
1686 * platform irq handler with the lock held.
1687 */
1688int mccic_irq(struct mcam_camera *cam, unsigned int irqs)
1689{
1690        unsigned int frame, handled = 0;
1691
1692        mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS); /* Clear'em all */
1693        /*
1694         * Handle any frame completions.  There really should
1695         * not be more than one of these, or we have fallen
1696         * far behind.
1697         *
1698         * When running in S/G mode, the frame number lacks any
1699         * real meaning - there's only one descriptor array - but
1700         * the controller still picks a different one to signal
1701         * each time.
1702         */
1703        for (frame = 0; frame < cam->nbufs; frame++)
1704                if (irqs & (IRQ_EOF0 << frame) &&
1705                        test_bit(CF_FRAME_SOF0 + frame, &cam->flags)) {
1706                        mcam_frame_complete(cam, frame);
1707                        handled = 1;
1708                        clear_bit(CF_FRAME_SOF0 + frame, &cam->flags);
1709                        if (cam->buffer_mode == B_DMA_sg)
1710                                break;
1711                }
1712        /*
1713         * If a frame starts, note that we have DMA active.  This
1714         * code assumes that we won't get multiple frame interrupts
1715         * at once; may want to rethink that.
1716         */
1717        for (frame = 0; frame < cam->nbufs; frame++) {
1718                if (irqs & (IRQ_SOF0 << frame)) {
1719                        set_bit(CF_FRAME_SOF0 + frame, &cam->flags);
1720                        handled = IRQ_HANDLED;
1721                }
1722        }
1723
1724        if (handled == IRQ_HANDLED) {
1725                set_bit(CF_DMA_ACTIVE, &cam->flags);
1726                if (cam->buffer_mode == B_DMA_sg)
1727                        mcam_ctlr_stop(cam);
1728        }
1729        return handled;
1730}
1731
1732/* ---------------------------------------------------------------------- */
1733/*
1734 * Registration and such.
1735 */
1736static struct ov7670_config sensor_cfg = {
1737        /*
1738         * Exclude QCIF mode, because it only captures a tiny portion
1739         * of the sensor FOV
1740         */
1741        .min_width = 320,
1742        .min_height = 240,
1743};
1744
1745
1746int mccic_register(struct mcam_camera *cam)
1747{
1748        struct i2c_board_info ov7670_info = {
1749                .type = "ov7670",
1750                .addr = 0x42 >> 1,
1751                .platform_data = &sensor_cfg,
1752        };
1753        int ret;
1754
1755        /*
1756         * Validate the requested buffer mode.
1757         */
1758        if (buffer_mode >= 0)
1759                cam->buffer_mode = buffer_mode;
1760        if (cam->buffer_mode == B_DMA_sg &&
1761                        cam->chip_id == MCAM_CAFE) {
1762                printk(KERN_ERR "marvell-cam: Cafe can't do S/G I/O, "
1763                        "attempting vmalloc mode instead\n");
1764                cam->buffer_mode = B_vmalloc;
1765        }
1766        if (!mcam_buffer_mode_supported(cam->buffer_mode)) {
1767                printk(KERN_ERR "marvell-cam: buffer mode %d unsupported\n",
1768                                cam->buffer_mode);
1769                return -EINVAL;
1770        }
1771        /*
1772         * Register with V4L
1773         */
1774        ret = v4l2_device_register(cam->dev, &cam->v4l2_dev);
1775        if (ret)
1776                return ret;
1777
1778        mutex_init(&cam->s_mutex);
1779        cam->state = S_NOTREADY;
1780        mcam_set_config_needed(cam, 1);
1781        cam->pix_format = mcam_def_pix_format;
1782        cam->mbus_code = mcam_def_mbus_code;
1783        mcam_ctlr_init(cam);
1784
1785        /*
1786         * Get the v4l2 setup done.
1787         */
1788        ret = v4l2_ctrl_handler_init(&cam->ctrl_handler, 10);
1789        if (ret)
1790                goto out_unregister;
1791        cam->v4l2_dev.ctrl_handler = &cam->ctrl_handler;
1792
1793        /*
1794         * Try to find the sensor.
1795         */
1796        sensor_cfg.clock_speed = cam->clock_speed;
1797        sensor_cfg.use_smbus = cam->use_smbus;
1798        cam->sensor_addr = ov7670_info.addr;
1799        cam->sensor = v4l2_i2c_new_subdev_board(&cam->v4l2_dev,
1800                        cam->i2c_adapter, &ov7670_info, NULL);
1801        if (cam->sensor == NULL) {
1802                ret = -ENODEV;
1803                goto out_unregister;
1804        }
1805
1806        ret = mcam_cam_init(cam);
1807        if (ret)
1808                goto out_unregister;
1809
1810        ret = mcam_setup_vb2(cam);
1811        if (ret)
1812                goto out_unregister;
1813
1814        mutex_lock(&cam->s_mutex);
1815        cam->vdev = mcam_v4l_template;
1816        cam->vdev.v4l2_dev = &cam->v4l2_dev;
1817        cam->vdev.lock = &cam->s_mutex;
1818        cam->vdev.queue = &cam->vb_queue;
1819        video_set_drvdata(&cam->vdev, cam);
1820        ret = video_register_device(&cam->vdev, VFL_TYPE_GRABBER, -1);
1821        if (ret) {
1822                mutex_unlock(&cam->s_mutex);
1823                goto out_unregister;
1824        }
1825
1826        /*
1827         * If so requested, try to get our DMA buffers now.
1828         */
1829        if (cam->buffer_mode == B_vmalloc && !alloc_bufs_at_read) {
1830                if (mcam_alloc_dma_bufs(cam, 1))
1831                        cam_warn(cam, "Unable to alloc DMA buffers at load"
1832                                        " will try again later.");
1833        }
1834
1835        mutex_unlock(&cam->s_mutex);
1836        return 0;
1837
1838out_unregister:
1839        v4l2_ctrl_handler_free(&cam->ctrl_handler);
1840        v4l2_device_unregister(&cam->v4l2_dev);
1841        return ret;
1842}
1843
1844
1845void mccic_shutdown(struct mcam_camera *cam)
1846{
1847        /*
1848         * If we have no users (and we really, really should have no
1849         * users) the device will already be powered down.  Trying to
1850         * take it down again will wedge the machine, which is frowned
1851         * upon.
1852         */
1853        if (!list_empty(&cam->vdev.fh_list)) {
1854                cam_warn(cam, "Removing a device with users!\n");
1855                mcam_ctlr_power_down(cam);
1856        }
1857        if (cam->buffer_mode == B_vmalloc)
1858                mcam_free_dma_bufs(cam);
1859        video_unregister_device(&cam->vdev);
1860        v4l2_ctrl_handler_free(&cam->ctrl_handler);
1861        v4l2_device_unregister(&cam->v4l2_dev);
1862}
1863
1864/*
1865 * Power management
1866 */
1867#ifdef CONFIG_PM
1868
1869void mccic_suspend(struct mcam_camera *cam)
1870{
1871        mutex_lock(&cam->s_mutex);
1872        if (!list_empty(&cam->vdev.fh_list)) {
1873                enum mcam_state cstate = cam->state;
1874
1875                mcam_ctlr_stop_dma(cam);
1876                mcam_ctlr_power_down(cam);
1877                cam->state = cstate;
1878        }
1879        mutex_unlock(&cam->s_mutex);
1880}
1881
1882int mccic_resume(struct mcam_camera *cam)
1883{
1884        int ret = 0;
1885
1886        mutex_lock(&cam->s_mutex);
1887        if (!list_empty(&cam->vdev.fh_list)) {
1888                ret = mcam_ctlr_power_up(cam);
1889                if (ret) {
1890                        mutex_unlock(&cam->s_mutex);
1891                        return ret;
1892                }
1893                __mcam_cam_reset(cam);
1894        } else {
1895                mcam_ctlr_power_down(cam);
1896        }
1897        mutex_unlock(&cam->s_mutex);
1898
1899        set_bit(CF_CONFIG_NEEDED, &cam->flags);
1900        if (cam->state == S_STREAMING) {
1901                /*
1902                 * If there was a buffer in the DMA engine at suspend
1903                 * time, put it back on the queue or we'll forget about it.
1904                 */
1905                if (cam->buffer_mode == B_DMA_sg && cam->vb_bufs[0])
1906                        list_add(&cam->vb_bufs[0]->queue, &cam->buffers);
1907                ret = mcam_read_setup(cam);
1908        }
1909        return ret;
1910}
1911#endif /* CONFIG_PM */
1912