LXR linux/drivers/memory/pl35x-smc.c

   1/*
   2 * ARM PL35X SMC Driver
   3 *
   4 * Copyright (C) 2012 - 2014 Xilinx, Inc.
   5 *
   6 * This program is free software: you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation, either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * Currently only a single SMC instance is supported.
  17 */
  18
  19#include <linux/clk.h>
  20#include <linux/io.h>
  21#include <linux/kernel.h>
  22#include <linux/memory/pl35x-smc.h>
  23#include <linux/module.h>
  24#include <linux/of_platform.h>
  25#include <linux/platform_device.h>
  26#include <linux/slab.h>
  27
  28/* Register definitions */
  29#define PL35X_SMC_MEMC_STATUS_OFFS      0       /* Controller status reg, RO */
  30#define PL35X_SMC_CFG_CLR_OFFS          0xC     /* Clear config reg, WO */
  31#define PL35X_SMC_DIRECT_CMD_OFFS       0x10    /* Direct command reg, WO */
  32#define PL35X_SMC_SET_CYCLES_OFFS       0x14    /* Set cycles register, WO */
  33#define PL35X_SMC_SET_OPMODE_OFFS       0x18    /* Set opmode register, WO */
  34#define PL35X_SMC_ECC_STATUS_OFFS       0x400   /* ECC status register */
  35#define PL35X_SMC_ECC_MEMCFG_OFFS       0x404   /* ECC mem config reg */
  36#define PL35X_SMC_ECC_MEMCMD1_OFFS      0x408   /* ECC mem cmd1 reg */
  37#define PL35X_SMC_ECC_MEMCMD2_OFFS      0x40C   /* ECC mem cmd2 reg */
  38#define PL35X_SMC_ECC_VALUE0_OFFS       0x418   /* ECC value 0 reg */
  39
  40/* Controller status register specifc constants */
  41#define PL35X_SMC_MEMC_STATUS_RAW_INT_1_SHIFT   6
  42
  43/* Clear configuration register specific constants */
  44#define PL35X_SMC_CFG_CLR_INT_CLR_1     0x10
  45#define PL35X_SMC_CFG_CLR_ECC_INT_DIS_1 0x40
  46#define PL35X_SMC_CFG_CLR_INT_DIS_1     0x2
  47#define PL35X_SMC_CFG_CLR_DEFAULT_MASK  (PL35X_SMC_CFG_CLR_INT_CLR_1 | \
  48                                         PL35X_SMC_CFG_CLR_ECC_INT_DIS_1 | \
  49                                         PL35X_SMC_CFG_CLR_INT_DIS_1)
  50
  51/* Set cycles register specific constants */
  52#define PL35X_SMC_SET_CYCLES_T0_MASK    0xF
  53#define PL35X_SMC_SET_CYCLES_T0_SHIFT   0
  54#define PL35X_SMC_SET_CYCLES_T1_MASK    0xF
  55#define PL35X_SMC_SET_CYCLES_T1_SHIFT   4
  56#define PL35X_SMC_SET_CYCLES_T2_MASK    0x7
  57#define PL35X_SMC_SET_CYCLES_T2_SHIFT   8
  58#define PL35X_SMC_SET_CYCLES_T3_MASK    0x7
  59#define PL35X_SMC_SET_CYCLES_T3_SHIFT   11
  60#define PL35X_SMC_SET_CYCLES_T4_MASK    0x7
  61#define PL35X_SMC_SET_CYCLES_T4_SHIFT   14
  62#define PL35X_SMC_SET_CYCLES_T5_MASK    0x7
  63#define PL35X_SMC_SET_CYCLES_T5_SHIFT   17
  64#define PL35X_SMC_SET_CYCLES_T6_MASK    0xF
  65#define PL35X_SMC_SET_CYCLES_T6_SHIFT   20
  66
  67/* ECC status register specific constants */
  68#define PL35X_SMC_ECC_STATUS_BUSY       (1 << 6)
  69
  70/* ECC memory config register specific constants */
  71#define PL35X_SMC_ECC_MEMCFG_MODE_MASK  0xC
  72#define PL35X_SMC_ECC_MEMCFG_MODE_SHIFT 2
  73#define PL35X_SMC_ECC_MEMCFG_PGSIZE_MASK        0xC
  74
  75#define PL35X_SMC_DC_UPT_NAND_REGS      ((4 << 23) |    /* CS: NAND chip */ \
  76                                 (2 << 21))     /* UpdateRegs operation */
  77
  78#define PL35X_NAND_ECC_CMD1     ((0x80)       | /* Write command */ \
  79                                 (0 << 8)     | /* Read command */ \
  80                                 (0x30 << 16) | /* Read End command */ \
  81                                 (1 << 24))     /* Read End command calid */
  82
  83#define PL35X_NAND_ECC_CMD2     ((0x85)       | /* Write col change cmd */ \
  84                                 (5 << 8)     | /* Read col change cmd */ \
  85                                 (0xE0 << 16) | /* Read col change end cmd */ \
  86                                 (1 << 24)) /* Read col change end cmd valid */
  87#define PL35X_NAND_ECC_BUSY_TIMEOUT     (1 * HZ)
  88/**
  89 * struct pl35x_smc_data - Private smc driver structure
  90 * @devclk:             Pointer to the peripheral clock
  91 * @aperclk:            Pointer to the APER clock
  92 */
  93struct pl35x_smc_data {
  94        struct clk              *memclk;
  95        struct clk              *aclk;
  96};
  97
  98/* SMC virtual register base */
  99static void __iomem *pl35x_smc_base;
 100
 101/**
 102 * pl35x_smc_set_buswidth - Set memory buswidth
 103 * @bw: Memory buswidth (8 | 16)
 104 * Return: 0 on success or negative errno.
 105 */
 106int pl35x_smc_set_buswidth(unsigned int bw)
 107{
 108
 109        if (bw != PL35X_SMC_MEM_WIDTH_8  && bw != PL35X_SMC_MEM_WIDTH_16)
 110                return -EINVAL;
 111
 112        writel(bw, pl35x_smc_base + PL35X_SMC_SET_OPMODE_OFFS);
 113        writel(PL35X_SMC_DC_UPT_NAND_REGS, pl35x_smc_base +
 114               PL35X_SMC_DIRECT_CMD_OFFS);
 115
 116        return 0;
 117}
 118EXPORT_SYMBOL_GPL(pl35x_smc_set_buswidth);
 119
 120/**
 121 * pl35x_smc_set_cycles - Set memory timing parameters
 122 * @t0: t_rc            read cycle time
 123 * @t1: t_wc            write cycle time
 124 * @t2: t_rea/t_ceoe    output enable assertion delay
 125 * @t3: t_wp            write enable deassertion delay
 126 * @t4: t_clr/t_pc      page cycle time
 127 * @t5: t_ar/t_ta       ID read time/turnaround time
 128 * @t6: t_rr            busy to RE timing
 129 *
 130 * Sets NAND chip specific timing parameters.
 131 */
 132static void pl35x_smc_set_cycles(u32 t0, u32 t1, u32 t2, u32 t3, u32
 133                              t4, u32 t5, u32 t6)
 134{
 135        t0 &= PL35X_SMC_SET_CYCLES_T0_MASK;
 136        t1 = (t1 & PL35X_SMC_SET_CYCLES_T1_MASK) <<
 137                        PL35X_SMC_SET_CYCLES_T1_SHIFT;
 138        t2 = (t2 & PL35X_SMC_SET_CYCLES_T2_MASK) <<
 139                        PL35X_SMC_SET_CYCLES_T2_SHIFT;
 140        t3 = (t3 & PL35X_SMC_SET_CYCLES_T3_MASK) <<
 141                        PL35X_SMC_SET_CYCLES_T3_SHIFT;
 142        t4 = (t4 & PL35X_SMC_SET_CYCLES_T4_MASK) <<
 143                        PL35X_SMC_SET_CYCLES_T4_SHIFT;
 144        t5 = (t5 & PL35X_SMC_SET_CYCLES_T5_MASK) <<
 145                        PL35X_SMC_SET_CYCLES_T5_SHIFT;
 146        t6 = (t6 & PL35X_SMC_SET_CYCLES_T6_MASK) <<
 147                        PL35X_SMC_SET_CYCLES_T6_SHIFT;
 148
 149        t0 |= t1 | t2 | t3 | t4 | t5 | t6;
 150
 151        writel(t0, pl35x_smc_base + PL35X_SMC_SET_CYCLES_OFFS);
 152        writel(PL35X_SMC_DC_UPT_NAND_REGS, pl35x_smc_base +
 153               PL35X_SMC_DIRECT_CMD_OFFS);
 154}
 155
 156/**
 157 * pl35x_smc_ecc_is_busy_noirq - Read ecc busy flag
 158 * Return: the ecc_status bit from the ecc_status register. 1 = busy, 0 = idle
 159 */
 160static int pl35x_smc_ecc_is_busy_noirq(void)
 161{
 162        return !!(readl(pl35x_smc_base + PL35X_SMC_ECC_STATUS_OFFS) &
 163                  PL35X_SMC_ECC_STATUS_BUSY);
 164}
 165
 166/**
 167 * pl35x_smc_ecc_is_busy - Read ecc busy flag
 168 * Return: the ecc_status bit from the ecc_status register. 1 = busy, 0 = idle
 169 */
 170int pl35x_smc_ecc_is_busy(void)
 171{
 172        int ret;
 173
 174        ret = pl35x_smc_ecc_is_busy_noirq();
 175
 176        return ret;
 177}
 178EXPORT_SYMBOL_GPL(pl35x_smc_ecc_is_busy);
 179
 180/**
 181 * pl35x_smc_get_ecc_val - Read ecc_valueN registers
 182 * @ecc_reg:    Index of the ecc_value reg (0..3)
 183 * Return: the content of the requested ecc_value register.
 184 *
 185 * There are four valid ecc_value registers. The argument is truncated to stay
 186 * within this valid boundary.
 187 */
 188u32 pl35x_smc_get_ecc_val(int ecc_reg)
 189{
 190        u32 addr, reg;
 191
 192        ecc_reg &= 3;
 193        addr = PL35X_SMC_ECC_VALUE0_OFFS + (ecc_reg << 2);
 194        reg = readl(pl35x_smc_base + addr);
 195
 196        return reg;
 197}
 198EXPORT_SYMBOL_GPL(pl35x_smc_get_ecc_val);
 199
 200/**
 201 * pl35x_smc_get_nand_int_status_raw - Get NAND interrupt status bit
 202 * Return: the raw_int_status1 bit from the memc_status register
 203 */
 204int pl35x_smc_get_nand_int_status_raw(void)
 205{
 206        u32 reg;
 207
 208        reg = readl(pl35x_smc_base + PL35X_SMC_MEMC_STATUS_OFFS);
 209        reg >>= PL35X_SMC_MEMC_STATUS_RAW_INT_1_SHIFT;
 210        reg &= 1;
 211
 212        return reg;
 213}
 214EXPORT_SYMBOL_GPL(pl35x_smc_get_nand_int_status_raw);
 215
 216/**
 217 * pl35x_smc_clr_nand_int - Clear NAND interrupt
 218 */
 219void pl35x_smc_clr_nand_int(void)
 220{
 221        writel(PL35X_SMC_CFG_CLR_INT_CLR_1,
 222                pl35x_smc_base + PL35X_SMC_CFG_CLR_OFFS);
 223}
 224EXPORT_SYMBOL_GPL(pl35x_smc_clr_nand_int);
 225
 226/**
 227 * pl35x_smc_set_ecc_mode - Set SMC ECC mode
 228 * @mode:       ECC mode (BYPASS, APB, MEM)
 229 * Return: 0 on success or negative errno.
 230 */
 231int pl35x_smc_set_ecc_mode(enum pl35x_smc_ecc_mode mode)
 232{
 233        u32 reg;
 234        int ret = 0;
 235
 236        switch (mode) {
 237        case PL35X_SMC_ECCMODE_BYPASS:
 238        case PL35X_SMC_ECCMODE_APB:
 239        case PL35X_SMC_ECCMODE_MEM:
 240
 241                reg = readl(pl35x_smc_base + PL35X_SMC_ECC_MEMCFG_OFFS);
 242                reg &= ~PL35X_SMC_ECC_MEMCFG_MODE_MASK;
 243                reg |= mode << PL35X_SMC_ECC_MEMCFG_MODE_SHIFT;
 244                writel(reg, pl35x_smc_base + PL35X_SMC_ECC_MEMCFG_OFFS);
 245
 246                break;
 247        default:
 248                ret = -EINVAL;
 249        }
 250
 251        return ret;
 252}
 253EXPORT_SYMBOL_GPL(pl35x_smc_set_ecc_mode);
 254
 255/**
 256 * pl35x_smc_set_ecc_pg_size - Set SMC ECC page size
 257 * @pg_sz:      ECC page size
 258 * Return: 0 on success or negative errno.
 259 */
 260int pl35x_smc_set_ecc_pg_size(unsigned int pg_sz)
 261{
 262        u32 reg, sz;
 263
 264        switch (pg_sz) {
 265        case 0:
 266                sz = 0;
 267                break;
 268        case 512:
 269                sz = 1;
 270                break;
 271        case 1024:
 272                sz = 2;
 273                break;
 274        case 2048:
 275                sz = 3;
 276                break;
 277        default:
 278                return -EINVAL;
 279        }
 280
 281        reg = readl(pl35x_smc_base + PL35X_SMC_ECC_MEMCFG_OFFS);
 282        reg &= ~PL35X_SMC_ECC_MEMCFG_PGSIZE_MASK;
 283        reg |= sz;
 284        writel(reg, pl35x_smc_base + PL35X_SMC_ECC_MEMCFG_OFFS);
 285
 286        return 0;
 287}
 288EXPORT_SYMBOL_GPL(pl35x_smc_set_ecc_pg_size);
 289
 290static int __maybe_unused pl35x_smc_suspend(struct device *dev)
 291{
 292        struct pl35x_smc_data *pl35x_smc = dev_get_drvdata(dev);
 293
 294        clk_disable(pl35x_smc->memclk);
 295        clk_disable(pl35x_smc->aclk);
 296
 297        return 0;
 298}
 299
 300static int __maybe_unused pl35x_smc_resume(struct device *dev)
 301{
 302        int ret;
 303        struct pl35x_smc_data *pl35x_smc = dev_get_drvdata(dev);
 304
 305        ret = clk_enable(pl35x_smc->aclk);
 306        if (ret) {
 307                dev_err(dev, "Cannot enable axi domain clock.\n");
 308                return ret;
 309        }
 310
 311        ret = clk_enable(pl35x_smc->memclk);
 312        if (ret) {
 313                dev_err(dev, "Cannot enable memory clock.\n");
 314                clk_disable(pl35x_smc->aclk);
 315                return ret;
 316        }
 317        return ret;
 318}
 319
 320static SIMPLE_DEV_PM_OPS(pl35x_smc_dev_pm_ops, pl35x_smc_suspend,
 321                         pl35x_smc_resume);
 322
 323/**
 324 * pl35x_smc_init_nand_interface - Initialize the NAND interface
 325 * @pdev:       Pointer to the platform_device struct
 326 * @nand_node:  Pointer to the pl35x_nand device_node struct
 327 */
 328static void pl35x_smc_init_nand_interface(struct platform_device *pdev,
 329                                       struct device_node *nand_node)
 330{
 331        u32 t_rc, t_wc, t_rea, t_wp, t_clr, t_ar, t_rr;
 332        int err;
 333        unsigned long timeout = jiffies + PL35X_NAND_ECC_BUSY_TIMEOUT;
 334
 335        /* nand-cycle-<X> property is refer to the NAND flash timing
 336         * mapping between dts and the NAND flash AC timing
 337         *  X  : AC timing name
 338         *  t0 : t_rc
 339         *  t1 : t_wc
 340         *  t2 : t_rea
 341         *  t3 : t_wp
 342         *  t4 : t_clr
 343         *  t5 : t_ar
 344         *  t6 : t_rr
 345         */
 346        err = of_property_read_u32(nand_node, "arm,nand-cycle-t0", &t_rc);
 347        if (err) {
 348                dev_warn(&pdev->dev, "arm,nand-cycle-t0 not in device tree");
 349                goto default_nand_timing;
 350        }
 351        err = of_property_read_u32(nand_node, "arm,nand-cycle-t1", &t_wc);
 352        if (err) {
 353                dev_warn(&pdev->dev, "arm,nand-cycle-t1 not in device tree");
 354                goto default_nand_timing;
 355        }
 356        err = of_property_read_u32(nand_node, "arm,nand-cycle-t2", &t_rea);
 357        if (err) {
 358                dev_warn(&pdev->dev, "arm,nand-cycle-t2 not in device tree");
 359                goto default_nand_timing;
 360        }
 361        err = of_property_read_u32(nand_node, "arm,nand-cycle-t3", &t_wp);
 362        if (err) {
 363                dev_warn(&pdev->dev, "arm,nand-cycle-t3 not in device tree");
 364                goto default_nand_timing;
 365        }
 366        err = of_property_read_u32(nand_node, "arm,nand-cycle-t4", &t_clr);
 367        if (err) {
 368                dev_warn(&pdev->dev, "arm,nand-cycle-t4 not in device tree");
 369                goto default_nand_timing;
 370        }
 371        err = of_property_read_u32(nand_node, "arm,nand-cycle-t5", &t_ar);
 372        if (err) {
 373                dev_warn(&pdev->dev, "arm,nand-cycle-t5 not in device tree");
 374                goto default_nand_timing;
 375        }
 376        err = of_property_read_u32(nand_node, "arm,nand-cycle-t6", &t_rr);
 377        if (err) {
 378                dev_warn(&pdev->dev, "arm,nand-cycle-t6 not in device tree");
 379                goto default_nand_timing;
 380        }
 381
 382default_nand_timing:
 383        if (err) {
 384                /* set default NAND flash timing property */
 385                dev_warn(&pdev->dev, "Using default timing for");
 386                dev_warn(&pdev->dev, "2Gb Numonyx MT29F2G08ABAEAWP NAND flash");
 387                dev_warn(&pdev->dev, "t_wp, t_clr, t_ar are set to 2");
 388                dev_warn(&pdev->dev, "t_rc, t_wc, t_rr are set to 4");
 389                dev_warn(&pdev->dev, "t_rea is set to 1");
 390                t_rc = t_wc = t_rr = 4;
 391                t_rea = 1;
 392                t_wp = t_clr = t_ar = 2;
 393        }
 394
 395        pl35x_smc_set_buswidth(PL35X_SMC_MEM_WIDTH_8);
 396
 397        /*
 398         * Default assume 50MHz clock (20ns cycle time) and 3V operation
 399         * The SET_CYCLES_REG register value depends on the flash device.
 400         * Look in to the device datasheet and change its value, This value
 401         * is for 2Gb Numonyx flash.
 402         */
 403        pl35x_smc_set_cycles(t_rc, t_wc, t_rea, t_wp, t_clr, t_ar, t_rr);
 404        writel(PL35X_SMC_CFG_CLR_INT_CLR_1,
 405                pl35x_smc_base + PL35X_SMC_CFG_CLR_OFFS);
 406        writel(PL35X_SMC_DC_UPT_NAND_REGS, pl35x_smc_base +
 407               PL35X_SMC_DIRECT_CMD_OFFS);
 408        /* Wait till the ECC operation is complete */
 409        do {
 410                if (pl35x_smc_ecc_is_busy_noirq())
 411                        cpu_relax();
 412                else
 413                        break;
 414        } while (!time_after_eq(jiffies, timeout));
 415
 416        if (time_after_eq(jiffies, timeout))
 417                dev_err(&pdev->dev, "nand ecc busy status timed out");
 418        /* Set the command1 and command2 register */
 419        writel(PL35X_NAND_ECC_CMD1,
 420                        pl35x_smc_base + PL35X_SMC_ECC_MEMCMD1_OFFS);
 421        writel(PL35X_NAND_ECC_CMD2,
 422                        pl35x_smc_base + PL35X_SMC_ECC_MEMCMD2_OFFS);
 423}
 424
 425static const struct of_device_id matches_nor[] = {
 426        { .compatible = "cfi-flash" },
 427        {}
 428};
 429
 430static const struct of_device_id matches_nand[] = {
 431        { .compatible = "arm,pl353-nand-r2p1" },
 432        {}
 433};
 434
 435static int pl35x_smc_probe(struct platform_device *pdev)
 436{
 437        struct pl35x_smc_data *pl35x_smc;
 438        struct device_node *child;
 439        struct resource *res;
 440        int err;
 441        struct device_node *of_node = pdev->dev.of_node;
 442        const struct of_device_id *matches = NULL;
 443
 444        pl35x_smc = devm_kzalloc(&pdev->dev, sizeof(*pl35x_smc), GFP_KERNEL);
 445        if (!pl35x_smc)
 446                return -ENOMEM;
 447
 448        /* Get the NAND controller virtual address */
 449        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 450        pl35x_smc_base = devm_ioremap_resource(&pdev->dev, res);
 451        if (IS_ERR(pl35x_smc_base))
 452                return PTR_ERR(pl35x_smc_base);
 453
 454        pl35x_smc->aclk = devm_clk_get(&pdev->dev, "aclk");
 455        if (IS_ERR(pl35x_smc->aclk)) {
 456                dev_err(&pdev->dev, "aclk clock not found.\n");
 457                return PTR_ERR(pl35x_smc->aclk);
 458        }
 459
 460        pl35x_smc->memclk = devm_clk_get(&pdev->dev, "memclk");
 461        if (IS_ERR(pl35x_smc->memclk)) {
 462                dev_err(&pdev->dev, "memclk clock not found.\n");
 463                return PTR_ERR(pl35x_smc->memclk);
 464        }
 465
 466        err = clk_prepare_enable(pl35x_smc->aclk);
 467        if (err) {
 468                dev_err(&pdev->dev, "Unable to enable AXI clock.\n");
 469                return err;
 470        }
 471
 472        err = clk_prepare_enable(pl35x_smc->memclk);
 473        if (err) {
 474                dev_err(&pdev->dev, "Unable to enable memory clock.\n");
 475                goto out_clk_dis_aper;
 476        }
 477
 478        platform_set_drvdata(pdev, pl35x_smc);
 479
 480        /* clear interrupts */
 481        writel(PL35X_SMC_CFG_CLR_DEFAULT_MASK,
 482                pl35x_smc_base + PL35X_SMC_CFG_CLR_OFFS);
 483
 484        /* Find compatible children. Only a single child is supported */
 485        for_each_available_child_of_node(of_node, child) {
 486                if (of_match_node(matches_nand, child)) {
 487                        pl35x_smc_init_nand_interface(pdev, child);
 488                        if (!matches) {
 489                                matches = matches_nand;
 490                        } else {
 491                                dev_err(&pdev->dev,
 492                                        "incompatible configuration\n");
 493                                goto out_clk_disable;
 494                        }
 495                }
 496
 497                if (of_match_node(matches_nor, child)) {
 498                        static int counts;
 499                        if (!matches) {
 500                                matches = matches_nor;
 501                        } else {
 502                                if (matches != matches_nor || counts > 1) {
 503                                        dev_err(&pdev->dev,
 504                                                "incompatible configuration\n");
 505                                        goto out_clk_disable;
 506                                }
 507                        }
 508                        counts++;
 509                }
 510        }
 511
 512        if (matches)
 513                of_platform_populate(of_node, matches, NULL, &pdev->dev);
 514
 515        return 0;
 516
 517out_clk_disable:
 518        clk_disable_unprepare(pl35x_smc->memclk);
 519out_clk_dis_aper:
 520        clk_disable_unprepare(pl35x_smc->aclk);
 521
 522        return err;
 523}
 524
 525static int pl35x_smc_remove(struct platform_device *pdev)
 526{
 527        struct pl35x_smc_data *pl35x_smc = platform_get_drvdata(pdev);
 528
 529        clk_disable_unprepare(pl35x_smc->memclk);
 530        clk_disable_unprepare(pl35x_smc->aclk);
 531
 532        return 0;
 533}
 534
 535/* Match table for device tree binding */
 536static const struct of_device_id pl35x_smc_of_match[] = {
 537        { .compatible = "arm,pl353-smc-r2p1" },
 538        { },
 539};
 540MODULE_DEVICE_TABLE(of, pl35x_smc_of_match);
 541
 542static struct platform_driver pl35x_smc_driver = {
 543        .probe          = pl35x_smc_probe,
 544        .remove         = pl35x_smc_remove,
 545        .driver         = {
 546                .name   = "pl35x-smc",
 547                .pm     = &pl35x_smc_dev_pm_ops,
 548                .of_match_table = pl35x_smc_of_match,
 549        },
 550};
 551
 552module_platform_driver(pl35x_smc_driver);
 553
 554MODULE_AUTHOR("Xilinx, Inc.");
 555MODULE_DESCRIPTION("ARM PL35X SMC Driver");
 556MODULE_LICENSE("GPL");
 557