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10#include <linux/pci.h>
11#include <misc/cxl.h>
12#include <asm/pnv-pci.h>
13#include "cxl.h"
14
15static int cxl_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
16{
17 if (dma_mask < DMA_BIT_MASK(64)) {
18 pr_info("%s only 64bit DMA supported on CXL", __func__);
19 return -EIO;
20 }
21
22 *(pdev->dev.dma_mask) = dma_mask;
23 return 0;
24}
25
26static int cxl_pci_probe_mode(struct pci_bus *bus)
27{
28 return PCI_PROBE_NORMAL;
29}
30
31static int cxl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
32{
33 return -ENODEV;
34}
35
36static void cxl_teardown_msi_irqs(struct pci_dev *pdev)
37{
38
39
40
41
42}
43
44static bool cxl_pci_enable_device_hook(struct pci_dev *dev)
45{
46 struct pci_controller *phb;
47 struct cxl_afu *afu;
48
49 phb = pci_bus_to_host(dev->bus);
50 afu = (struct cxl_afu *)phb->private_data;
51
52 if (!cxl_ops->link_ok(afu->adapter, afu)) {
53 dev_warn(&dev->dev, "%s: Device link is down, refusing to enable AFU\n", __func__);
54 return false;
55 }
56
57 set_dma_ops(&dev->dev, &dma_direct_ops);
58 set_dma_offset(&dev->dev, PAGE_OFFSET);
59
60 return _cxl_pci_associate_default_context(dev, afu);
61}
62
63static resource_size_t cxl_pci_window_alignment(struct pci_bus *bus,
64 unsigned long type)
65{
66 return 1;
67}
68
69static void cxl_pci_reset_secondary_bus(struct pci_dev *dev)
70{
71
72}
73
74static int cxl_pcie_cfg_record(u8 bus, u8 devfn)
75{
76 return (bus << 8) + devfn;
77}
78
79static int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn,
80 struct cxl_afu **_afu, int *_record)
81{
82 struct pci_controller *phb;
83 struct cxl_afu *afu;
84 int record;
85
86 phb = pci_bus_to_host(bus);
87 if (phb == NULL)
88 return PCIBIOS_DEVICE_NOT_FOUND;
89
90 afu = (struct cxl_afu *)phb->private_data;
91 record = cxl_pcie_cfg_record(bus->number, devfn);
92 if (record > afu->crs_num)
93 return PCIBIOS_DEVICE_NOT_FOUND;
94
95 *_afu = afu;
96 *_record = record;
97 return 0;
98}
99
100static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
101 int offset, int len, u32 *val)
102{
103 int rc, record;
104 struct cxl_afu *afu;
105 u8 val8;
106 u16 val16;
107 u32 val32;
108
109 rc = cxl_pcie_config_info(bus, devfn, &afu, &record);
110 if (rc)
111 return rc;
112
113 switch (len) {
114 case 1:
115 rc = cxl_ops->afu_cr_read8(afu, record, offset, &val8);
116 *val = val8;
117 break;
118 case 2:
119 rc = cxl_ops->afu_cr_read16(afu, record, offset, &val16);
120 *val = val16;
121 break;
122 case 4:
123 rc = cxl_ops->afu_cr_read32(afu, record, offset, &val32);
124 *val = val32;
125 break;
126 default:
127 WARN_ON(1);
128 }
129
130 if (rc)
131 return PCIBIOS_DEVICE_NOT_FOUND;
132
133 return PCIBIOS_SUCCESSFUL;
134}
135
136static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
137 int offset, int len, u32 val)
138{
139 int rc, record;
140 struct cxl_afu *afu;
141
142 rc = cxl_pcie_config_info(bus, devfn, &afu, &record);
143 if (rc)
144 return rc;
145
146 switch (len) {
147 case 1:
148 rc = cxl_ops->afu_cr_write8(afu, record, offset, val & 0xff);
149 break;
150 case 2:
151 rc = cxl_ops->afu_cr_write16(afu, record, offset, val & 0xffff);
152 break;
153 case 4:
154 rc = cxl_ops->afu_cr_write32(afu, record, offset, val);
155 break;
156 default:
157 WARN_ON(1);
158 }
159
160 if (rc)
161 return PCIBIOS_SET_FAILED;
162
163 return PCIBIOS_SUCCESSFUL;
164}
165
166static struct pci_ops cxl_pcie_pci_ops =
167{
168 .read = cxl_pcie_read_config,
169 .write = cxl_pcie_write_config,
170};
171
172
173static struct pci_controller_ops cxl_pci_controller_ops =
174{
175 .probe_mode = cxl_pci_probe_mode,
176 .enable_device_hook = cxl_pci_enable_device_hook,
177 .disable_device = _cxl_pci_disable_device,
178 .release_device = _cxl_pci_disable_device,
179 .window_alignment = cxl_pci_window_alignment,
180 .reset_secondary_bus = cxl_pci_reset_secondary_bus,
181 .setup_msi_irqs = cxl_setup_msi_irqs,
182 .teardown_msi_irqs = cxl_teardown_msi_irqs,
183 .dma_set_mask = cxl_dma_set_mask,
184};
185
186int cxl_pci_vphb_add(struct cxl_afu *afu)
187{
188 struct pci_controller *phb;
189 struct device_node *vphb_dn;
190 struct device *parent;
191
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198
199
200 if (!afu->crs_num)
201 return 0;
202
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207
208
209
210 parent = afu->adapter->dev.parent;
211 vphb_dn = parent->of_node;
212
213
214 phb = pcibios_alloc_controller(vphb_dn);
215 if (!phb)
216 return -ENODEV;
217
218
219 phb->parent = parent;
220
221
222 phb->ops = &cxl_pcie_pci_ops;
223 phb->cfg_addr = NULL;
224 phb->cfg_data = NULL;
225 phb->private_data = afu;
226 phb->controller_ops = cxl_pci_controller_ops;
227
228
229 pcibios_scan_phb(phb);
230 if (phb->bus == NULL)
231 return -ENXIO;
232
233
234 pci_set_host_bridge_release(to_pci_host_bridge(phb->bus->bridge),
235 pcibios_free_controller_deferred,
236 (void *) phb);
237
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240
241
242 pcibios_claim_one_bus(phb->bus);
243
244
245 pci_bus_add_devices(phb->bus);
246
247 afu->phb = phb;
248
249 return 0;
250}
251
252void cxl_pci_vphb_remove(struct cxl_afu *afu)
253{
254 struct pci_controller *phb;
255
256
257 if (!afu || !afu->phb)
258 return;
259
260 phb = afu->phb;
261 afu->phb = NULL;
262
263 pci_remove_root_bus(phb->bus);
264
265
266
267
268}
269
270static bool _cxl_pci_is_vphb_device(struct pci_controller *phb)
271{
272 return (phb->ops == &cxl_pcie_pci_ops);
273}
274
275bool cxl_pci_is_vphb_device(struct pci_dev *dev)
276{
277 struct pci_controller *phb;
278
279 phb = pci_bus_to_host(dev->bus);
280
281 return _cxl_pci_is_vphb_device(phb);
282}
283
284struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev)
285{
286 struct pci_controller *phb;
287
288 phb = pci_bus_to_host(dev->bus);
289
290 if (_cxl_pci_is_vphb_device(phb))
291 return (struct cxl_afu *)phb->private_data;
292
293 if (pnv_pci_on_cxl_phb(dev))
294 return pnv_cxl_phb_to_afu(phb);
295
296 return ERR_PTR(-ENODEV);
297}
298EXPORT_SYMBOL_GPL(cxl_pci_to_afu);
299
300unsigned int cxl_pci_to_cfg_record(struct pci_dev *dev)
301{
302 return cxl_pcie_cfg_record(dev->bus->number, dev->devfn);
303}
304EXPORT_SYMBOL_GPL(cxl_pci_to_cfg_record);
305