linux/drivers/mtd/nand/fsl_ifc_nand.c
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   1/*
   2 * Freescale Integrated Flash Controller NAND driver
   3 *
   4 * Copyright 2011-2012 Freescale Semiconductor, Inc
   5 *
   6 * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; either version 2 of the License, or
  11 * (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23#include <linux/module.h>
  24#include <linux/types.h>
  25#include <linux/kernel.h>
  26#include <linux/of_address.h>
  27#include <linux/slab.h>
  28#include <linux/mtd/mtd.h>
  29#include <linux/mtd/nand.h>
  30#include <linux/mtd/partitions.h>
  31#include <linux/mtd/nand_ecc.h>
  32#include <linux/fsl_ifc.h>
  33
  34#define ERR_BYTE                0xFF /* Value returned for read
  35                                        bytes when read failed  */
  36#define IFC_TIMEOUT_MSECS       500  /* Maximum number of mSecs to wait
  37                                        for IFC NAND Machine    */
  38
  39struct fsl_ifc_ctrl;
  40
  41/* mtd information per set */
  42struct fsl_ifc_mtd {
  43        struct nand_chip chip;
  44        struct fsl_ifc_ctrl *ctrl;
  45
  46        struct device *dev;
  47        int bank;               /* Chip select bank number              */
  48        unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  49        u8 __iomem *vbase;      /* Chip select base virtual address     */
  50};
  51
  52/* overview of the fsl ifc controller */
  53struct fsl_ifc_nand_ctrl {
  54        struct nand_hw_control controller;
  55        struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
  56
  57        void __iomem *addr;     /* Address of assigned IFC buffer       */
  58        unsigned int page;      /* Last page written to / read from     */
  59        unsigned int read_bytes;/* Number of bytes read during command  */
  60        unsigned int column;    /* Saved column from SEQIN              */
  61        unsigned int index;     /* Pointer to next byte to 'read'       */
  62        unsigned int oob;       /* Non zero if operating on OOB data    */
  63        unsigned int eccread;   /* Non zero for a full-page ECC read    */
  64        unsigned int counter;   /* counter for the initializations      */
  65        unsigned int max_bitflips;  /* Saved during READ0 cmd           */
  66};
  67
  68static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
  69
  70/*
  71 * Generic flash bbt descriptors
  72 */
  73static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  74static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  75
  76static struct nand_bbt_descr bbt_main_descr = {
  77        .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  78                   NAND_BBT_2BIT | NAND_BBT_VERSION,
  79        .offs = 2, /* 0 on 8-bit small page */
  80        .len = 4,
  81        .veroffs = 6,
  82        .maxblocks = 4,
  83        .pattern = bbt_pattern,
  84};
  85
  86static struct nand_bbt_descr bbt_mirror_descr = {
  87        .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  88                   NAND_BBT_2BIT | NAND_BBT_VERSION,
  89        .offs = 2, /* 0 on 8-bit small page */
  90        .len = 4,
  91        .veroffs = 6,
  92        .maxblocks = 4,
  93        .pattern = mirror_pattern,
  94};
  95
  96static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section,
  97                                 struct mtd_oob_region *oobregion)
  98{
  99        struct nand_chip *chip = mtd_to_nand(mtd);
 100
 101        if (section)
 102                return -ERANGE;
 103
 104        oobregion->offset = 8;
 105        oobregion->length = chip->ecc.total;
 106
 107        return 0;
 108}
 109
 110static int fsl_ifc_ooblayout_free(struct mtd_info *mtd, int section,
 111                                  struct mtd_oob_region *oobregion)
 112{
 113        struct nand_chip *chip = mtd_to_nand(mtd);
 114
 115        if (section > 1)
 116                return -ERANGE;
 117
 118        if (mtd->writesize == 512 &&
 119            !(chip->options & NAND_BUSWIDTH_16)) {
 120                if (!section) {
 121                        oobregion->offset = 0;
 122                        oobregion->length = 5;
 123                } else {
 124                        oobregion->offset = 6;
 125                        oobregion->length = 2;
 126                }
 127
 128                return 0;
 129        }
 130
 131        if (!section) {
 132                oobregion->offset = 2;
 133                oobregion->length = 6;
 134        } else {
 135                oobregion->offset = chip->ecc.total + 8;
 136                oobregion->length = mtd->oobsize - oobregion->offset;
 137        }
 138
 139        return 0;
 140}
 141
 142static const struct mtd_ooblayout_ops fsl_ifc_ooblayout_ops = {
 143        .ecc = fsl_ifc_ooblayout_ecc,
 144        .free = fsl_ifc_ooblayout_free,
 145};
 146
 147/*
 148 * Set up the IFC hardware block and page address fields, and the ifc nand
 149 * structure addr field to point to the correct IFC buffer in memory
 150 */
 151static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 152{
 153        struct nand_chip *chip = mtd_to_nand(mtd);
 154        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 155        struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 156        struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 157        int buf_num;
 158
 159        ifc_nand_ctrl->page = page_addr;
 160        /* Program ROW0/COL0 */
 161        ifc_out32(page_addr, &ifc->ifc_nand.row0);
 162        ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
 163
 164        buf_num = page_addr & priv->bufnum_mask;
 165
 166        ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
 167        ifc_nand_ctrl->index = column;
 168
 169        /* for OOB data point to the second half of the buffer */
 170        if (oob)
 171                ifc_nand_ctrl->index += mtd->writesize;
 172}
 173
 174static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
 175{
 176        struct nand_chip *chip = mtd_to_nand(mtd);
 177        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 178        u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
 179        u32 __iomem *mainarea = (u32 __iomem *)addr;
 180        u8 __iomem *oob = addr + mtd->writesize;
 181        struct mtd_oob_region oobregion = { };
 182        int i, section = 0;
 183
 184        for (i = 0; i < mtd->writesize / 4; i++) {
 185                if (__raw_readl(&mainarea[i]) != 0xffffffff)
 186                        return 0;
 187        }
 188
 189        mtd_ooblayout_ecc(mtd, section++, &oobregion);
 190        while (oobregion.length) {
 191                for (i = 0; i < oobregion.length; i++) {
 192                        if (__raw_readb(&oob[oobregion.offset + i]) != 0xff)
 193                                return 0;
 194                }
 195
 196                mtd_ooblayout_ecc(mtd, section++, &oobregion);
 197        }
 198
 199        return 1;
 200}
 201
 202/* returns nonzero if entire page is blank */
 203static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
 204                          u32 *eccstat, unsigned int bufnum)
 205{
 206        u32 reg = eccstat[bufnum / 4];
 207        int errors;
 208
 209        errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
 210
 211        return errors;
 212}
 213
 214/*
 215 * execute IFC NAND command and wait for it to complete
 216 */
 217static void fsl_ifc_run_command(struct mtd_info *mtd)
 218{
 219        struct nand_chip *chip = mtd_to_nand(mtd);
 220        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 221        struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 222        struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
 223        struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 224        u32 eccstat[4];
 225        int i;
 226
 227        /* set the chip select for NAND Transaction */
 228        ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,
 229                  &ifc->ifc_nand.nand_csel);
 230
 231        dev_vdbg(priv->dev,
 232                        "%s: fir0=%08x fcr0=%08x\n",
 233                        __func__,
 234                        ifc_in32(&ifc->ifc_nand.nand_fir0),
 235                        ifc_in32(&ifc->ifc_nand.nand_fcr0));
 236
 237        ctrl->nand_stat = 0;
 238
 239        /* start read/write seq */
 240        ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
 241
 242        /* wait for command complete flag or timeout */
 243        wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
 244                           msecs_to_jiffies(IFC_TIMEOUT_MSECS));
 245
 246        /* ctrl->nand_stat will be updated from IRQ context */
 247        if (!ctrl->nand_stat)
 248                dev_err(priv->dev, "Controller is not responding\n");
 249        if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
 250                dev_err(priv->dev, "NAND Flash Timeout Error\n");
 251        if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
 252                dev_err(priv->dev, "NAND Flash Write Protect Error\n");
 253
 254        nctrl->max_bitflips = 0;
 255
 256        if (nctrl->eccread) {
 257                int errors;
 258                int bufnum = nctrl->page & priv->bufnum_mask;
 259                int sector = bufnum * chip->ecc.steps;
 260                int sector_end = sector + chip->ecc.steps - 1;
 261
 262                for (i = sector / 4; i <= sector_end / 4; i++)
 263                        eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
 264
 265                for (i = sector; i <= sector_end; i++) {
 266                        errors = check_read_ecc(mtd, ctrl, eccstat, i);
 267
 268                        if (errors == 15) {
 269                                /*
 270                                 * Uncorrectable error.
 271                                 * OK only if the whole page is blank.
 272                                 *
 273                                 * We disable ECCER reporting due to...
 274                                 * erratum IFC-A002770 -- so report it now if we
 275                                 * see an uncorrectable error in ECCSTAT.
 276                                 */
 277                                if (!is_blank(mtd, bufnum))
 278                                        ctrl->nand_stat |=
 279                                                IFC_NAND_EVTER_STAT_ECCER;
 280                                break;
 281                        }
 282
 283                        mtd->ecc_stats.corrected += errors;
 284                        nctrl->max_bitflips = max_t(unsigned int,
 285                                                    nctrl->max_bitflips,
 286                                                    errors);
 287                }
 288
 289                nctrl->eccread = 0;
 290        }
 291}
 292
 293static void fsl_ifc_do_read(struct nand_chip *chip,
 294                            int oob,
 295                            struct mtd_info *mtd)
 296{
 297        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 298        struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 299        struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 300
 301        /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
 302        if (mtd->writesize > 512) {
 303                ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 304                          (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 305                          (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 306                          (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
 307                          (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
 308                          &ifc->ifc_nand.nand_fir0);
 309                ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
 310
 311                ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
 312                          (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
 313                          &ifc->ifc_nand.nand_fcr0);
 314        } else {
 315                ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 316                          (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 317                          (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
 318                          (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
 319                          &ifc->ifc_nand.nand_fir0);
 320                ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
 321
 322                if (oob)
 323                        ifc_out32(NAND_CMD_READOOB <<
 324                                  IFC_NAND_FCR0_CMD0_SHIFT,
 325                                  &ifc->ifc_nand.nand_fcr0);
 326                else
 327                        ifc_out32(NAND_CMD_READ0 <<
 328                                  IFC_NAND_FCR0_CMD0_SHIFT,
 329                                  &ifc->ifc_nand.nand_fcr0);
 330        }
 331}
 332
 333/* cmdfunc send commands to the IFC NAND Machine */
 334static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 335                             int column, int page_addr) {
 336        struct nand_chip *chip = mtd_to_nand(mtd);
 337        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 338        struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 339        struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 340
 341        /* clear the read buffer */
 342        ifc_nand_ctrl->read_bytes = 0;
 343        if (command != NAND_CMD_PAGEPROG)
 344                ifc_nand_ctrl->index = 0;
 345
 346        switch (command) {
 347        /* READ0 read the entire buffer to use hardware ECC. */
 348        case NAND_CMD_READ0:
 349                ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
 350                set_addr(mtd, 0, page_addr, 0);
 351
 352                ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 353                ifc_nand_ctrl->index += column;
 354
 355                if (chip->ecc.mode == NAND_ECC_HW)
 356                        ifc_nand_ctrl->eccread = 1;
 357
 358                fsl_ifc_do_read(chip, 0, mtd);
 359                fsl_ifc_run_command(mtd);
 360                return;
 361
 362        /* READOOB reads only the OOB because no ECC is performed. */
 363        case NAND_CMD_READOOB:
 364                ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
 365                set_addr(mtd, column, page_addr, 1);
 366
 367                ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 368
 369                fsl_ifc_do_read(chip, 1, mtd);
 370                fsl_ifc_run_command(mtd);
 371
 372                return;
 373
 374        case NAND_CMD_READID:
 375        case NAND_CMD_PARAM: {
 376                int timing = IFC_FIR_OP_RB;
 377                if (command == NAND_CMD_PARAM)
 378                        timing = IFC_FIR_OP_RBCD;
 379
 380                ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 381                          (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 382                          (timing << IFC_NAND_FIR0_OP2_SHIFT),
 383                          &ifc->ifc_nand.nand_fir0);
 384                ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT,
 385                          &ifc->ifc_nand.nand_fcr0);
 386                ifc_out32(column, &ifc->ifc_nand.row3);
 387
 388                /*
 389                 * although currently it's 8 bytes for READID, we always read
 390                 * the maximum 256 bytes(for PARAM)
 391                 */
 392                ifc_out32(256, &ifc->ifc_nand.nand_fbcr);
 393                ifc_nand_ctrl->read_bytes = 256;
 394
 395                set_addr(mtd, 0, 0, 0);
 396                fsl_ifc_run_command(mtd);
 397                return;
 398        }
 399
 400        /* ERASE1 stores the block and page address */
 401        case NAND_CMD_ERASE1:
 402                set_addr(mtd, 0, page_addr, 0);
 403                return;
 404
 405        /* ERASE2 uses the block and page address from ERASE1 */
 406        case NAND_CMD_ERASE2:
 407                ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 408                          (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 409                          (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
 410                          &ifc->ifc_nand.nand_fir0);
 411
 412                ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
 413                          (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
 414                          &ifc->ifc_nand.nand_fcr0);
 415
 416                ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
 417                ifc_nand_ctrl->read_bytes = 0;
 418                fsl_ifc_run_command(mtd);
 419                return;
 420
 421        /* SEQIN sets up the addr buffer and all registers except the length */
 422        case NAND_CMD_SEQIN: {
 423                u32 nand_fcr0;
 424                ifc_nand_ctrl->column = column;
 425                ifc_nand_ctrl->oob = 0;
 426
 427                if (mtd->writesize > 512) {
 428                        nand_fcr0 =
 429                                (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
 430                                (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
 431                                (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
 432
 433                        ifc_out32(
 434                                (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 435                                (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 436                                (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 437                                (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
 438                                (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
 439                                &ifc->ifc_nand.nand_fir0);
 440                        ifc_out32(
 441                                (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
 442                                (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) |
 443                                (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
 444                                &ifc->ifc_nand.nand_fir1);
 445                } else {
 446                        nand_fcr0 = ((NAND_CMD_PAGEPROG <<
 447                                        IFC_NAND_FCR0_CMD1_SHIFT) |
 448                                    (NAND_CMD_SEQIN <<
 449                                        IFC_NAND_FCR0_CMD2_SHIFT) |
 450                                    (NAND_CMD_STATUS <<
 451                                        IFC_NAND_FCR0_CMD3_SHIFT));
 452
 453                        ifc_out32(
 454                                (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 455                                (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
 456                                (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 457                                (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
 458                                (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
 459                                &ifc->ifc_nand.nand_fir0);
 460                        ifc_out32(
 461                                (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
 462                                (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
 463                                (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) |
 464                                (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
 465                                &ifc->ifc_nand.nand_fir1);
 466
 467                        if (column >= mtd->writesize)
 468                                nand_fcr0 |=
 469                                NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
 470                        else
 471                                nand_fcr0 |=
 472                                NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
 473                }
 474
 475                if (column >= mtd->writesize) {
 476                        /* OOB area --> READOOB */
 477                        column -= mtd->writesize;
 478                        ifc_nand_ctrl->oob = 1;
 479                }
 480                ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
 481                set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
 482                return;
 483        }
 484
 485        /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 486        case NAND_CMD_PAGEPROG: {
 487                if (ifc_nand_ctrl->oob) {
 488                        ifc_out32(ifc_nand_ctrl->index -
 489                                  ifc_nand_ctrl->column,
 490                                  &ifc->ifc_nand.nand_fbcr);
 491                } else {
 492                        ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
 493                }
 494
 495                fsl_ifc_run_command(mtd);
 496                return;
 497        }
 498
 499        case NAND_CMD_STATUS: {
 500                void __iomem *addr;
 501
 502                ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 503                          (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
 504                          &ifc->ifc_nand.nand_fir0);
 505                ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
 506                          &ifc->ifc_nand.nand_fcr0);
 507                ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
 508                set_addr(mtd, 0, 0, 0);
 509                ifc_nand_ctrl->read_bytes = 1;
 510
 511                fsl_ifc_run_command(mtd);
 512
 513                /*
 514                 * The chip always seems to report that it is
 515                 * write-protected, even when it is not.
 516                 */
 517                addr = ifc_nand_ctrl->addr;
 518                if (chip->options & NAND_BUSWIDTH_16)
 519                        ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr);
 520                else
 521                        ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr);
 522                return;
 523        }
 524
 525        case NAND_CMD_RESET:
 526                ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
 527                          &ifc->ifc_nand.nand_fir0);
 528                ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
 529                          &ifc->ifc_nand.nand_fcr0);
 530                fsl_ifc_run_command(mtd);
 531                return;
 532
 533        default:
 534                dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
 535                                        __func__, command);
 536        }
 537}
 538
 539static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
 540{
 541        /* The hardware does not seem to support multiple
 542         * chips per bank.
 543         */
 544}
 545
 546/*
 547 * Write buf to the IFC NAND Controller Data Buffer
 548 */
 549static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 550{
 551        struct nand_chip *chip = mtd_to_nand(mtd);
 552        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 553        unsigned int bufsize = mtd->writesize + mtd->oobsize;
 554
 555        if (len <= 0) {
 556                dev_err(priv->dev, "%s: len %d bytes", __func__, len);
 557                return;
 558        }
 559
 560        if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
 561                dev_err(priv->dev,
 562                        "%s: beyond end of buffer (%d requested, %u available)\n",
 563                        __func__, len, bufsize - ifc_nand_ctrl->index);
 564                len = bufsize - ifc_nand_ctrl->index;
 565        }
 566
 567        memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len);
 568        ifc_nand_ctrl->index += len;
 569}
 570
 571/*
 572 * Read a byte from either the IFC hardware buffer
 573 * read function for 8-bit buswidth
 574 */
 575static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
 576{
 577        struct nand_chip *chip = mtd_to_nand(mtd);
 578        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 579        unsigned int offset;
 580
 581        /*
 582         * If there are still bytes in the IFC buffer, then use the
 583         * next byte.
 584         */
 585        if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
 586                offset = ifc_nand_ctrl->index++;
 587                return ifc_in8(ifc_nand_ctrl->addr + offset);
 588        }
 589
 590        dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
 591        return ERR_BYTE;
 592}
 593
 594/*
 595 * Read two bytes from the IFC hardware buffer
 596 * read function for 16-bit buswith
 597 */
 598static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
 599{
 600        struct nand_chip *chip = mtd_to_nand(mtd);
 601        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 602        uint16_t data;
 603
 604        /*
 605         * If there are still bytes in the IFC buffer, then use the
 606         * next byte.
 607         */
 608        if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
 609                data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
 610                ifc_nand_ctrl->index += 2;
 611                return (uint8_t) data;
 612        }
 613
 614        dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
 615        return ERR_BYTE;
 616}
 617
 618/*
 619 * Read from the IFC Controller Data Buffer
 620 */
 621static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 622{
 623        struct nand_chip *chip = mtd_to_nand(mtd);
 624        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 625        int avail;
 626
 627        if (len < 0) {
 628                dev_err(priv->dev, "%s: len %d bytes", __func__, len);
 629                return;
 630        }
 631
 632        avail = min((unsigned int)len,
 633                        ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
 634        memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail);
 635        ifc_nand_ctrl->index += avail;
 636
 637        if (len > avail)
 638                dev_err(priv->dev,
 639                        "%s: beyond end of buffer (%d requested, %d available)\n",
 640                        __func__, len, avail);
 641}
 642
 643/*
 644 * This function is called after Program and Erase Operations to
 645 * check for success or failure.
 646 */
 647static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 648{
 649        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 650        struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 651        struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
 652        u32 nand_fsr;
 653
 654        /* Use READ_STATUS command, but wait for the device to be ready */
 655        ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 656                  (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
 657                  &ifc->ifc_nand.nand_fir0);
 658        ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
 659                  &ifc->ifc_nand.nand_fcr0);
 660        ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
 661        set_addr(mtd, 0, 0, 0);
 662        ifc_nand_ctrl->read_bytes = 1;
 663
 664        fsl_ifc_run_command(mtd);
 665
 666        nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
 667
 668        /*
 669         * The chip always seems to report that it is
 670         * write-protected, even when it is not.
 671         */
 672        return nand_fsr | NAND_STATUS_WP;
 673}
 674
 675static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 676                             uint8_t *buf, int oob_required, int page)
 677{
 678        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 679        struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 680        struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
 681
 682        fsl_ifc_read_buf(mtd, buf, mtd->writesize);
 683        if (oob_required)
 684                fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 685
 686        if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER)
 687                dev_err(priv->dev, "NAND Flash ECC Uncorrectable Error\n");
 688
 689        if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
 690                mtd->ecc_stats.failed++;
 691
 692        return nctrl->max_bitflips;
 693}
 694
 695/* ECC will be calculated automatically, and errors will be detected in
 696 * waitfunc.
 697 */
 698static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 699                               const uint8_t *buf, int oob_required, int page)
 700{
 701        fsl_ifc_write_buf(mtd, buf, mtd->writesize);
 702        fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 703
 704        return 0;
 705}
 706
 707static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
 708{
 709        struct nand_chip *chip = mtd_to_nand(mtd);
 710        struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 711
 712        dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
 713                                                        chip->numchips);
 714        dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
 715                                                        chip->chipsize);
 716        dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
 717                                                        chip->pagemask);
 718        dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
 719                                                        chip->chip_delay);
 720        dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
 721                                                        chip->badblockpos);
 722        dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
 723                                                        chip->chip_shift);
 724        dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
 725                                                        chip->page_shift);
 726        dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
 727                                                        chip->phys_erase_shift);
 728        dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
 729                                                        chip->ecc.mode);
 730        dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
 731                                                        chip->ecc.steps);
 732        dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
 733                                                        chip->ecc.bytes);
 734        dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
 735                                                        chip->ecc.total);
 736        dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__,
 737                                                        mtd->ooblayout);
 738        dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
 739        dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
 740        dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
 741                                                        mtd->erasesize);
 742        dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
 743                                                        mtd->writesize);
 744        dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
 745                                                        mtd->oobsize);
 746
 747        return 0;
 748}
 749
 750static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
 751{
 752        struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 753        struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
 754        struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
 755        uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
 756        uint32_t cs = priv->bank;
 757
 758        /* Save CSOR and CSOR_ext */
 759        csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
 760        csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
 761
 762        /* chage PageSize 8K and SpareSize 1K*/
 763        csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
 764        ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor);
 765        ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext);
 766
 767        /* READID */
 768        ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 769                    (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 770                    (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
 771                    &ifc_runtime->ifc_nand.nand_fir0);
 772        ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
 773                    &ifc_runtime->ifc_nand.nand_fcr0);
 774        ifc_out32(0x0, &ifc_runtime->ifc_nand.row3);
 775
 776        ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr);
 777
 778        /* Program ROW0/COL0 */
 779        ifc_out32(0x0, &ifc_runtime->ifc_nand.row0);
 780        ifc_out32(0x0, &ifc_runtime->ifc_nand.col0);
 781
 782        /* set the chip select for NAND Transaction */
 783        ifc_out32(cs << IFC_NAND_CSEL_SHIFT,
 784                &ifc_runtime->ifc_nand.nand_csel);
 785
 786        /* start read seq */
 787        ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT,
 788                &ifc_runtime->ifc_nand.nandseq_strt);
 789
 790        /* wait for command complete flag or timeout */
 791        wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
 792                           msecs_to_jiffies(IFC_TIMEOUT_MSECS));
 793
 794        if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
 795                printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
 796
 797        /* Restore CSOR and CSOR_ext */
 798        ifc_out32(csor, &ifc_global->csor_cs[cs].csor);
 799        ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext);
 800}
 801
 802static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 803{
 804        struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 805        struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
 806        struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
 807        struct nand_chip *chip = &priv->chip;
 808        struct mtd_info *mtd = nand_to_mtd(&priv->chip);
 809        u32 csor;
 810
 811        /* Fill in fsl_ifc_mtd structure */
 812        mtd->dev.parent = priv->dev;
 813        nand_set_flash_node(chip, priv->dev->of_node);
 814
 815        /* fill in nand_chip structure */
 816        /* set up function call table */
 817        if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
 818                & CSPR_PORT_SIZE_16)
 819                chip->read_byte = fsl_ifc_read_byte16;
 820        else
 821                chip->read_byte = fsl_ifc_read_byte;
 822
 823        chip->write_buf = fsl_ifc_write_buf;
 824        chip->read_buf = fsl_ifc_read_buf;
 825        chip->select_chip = fsl_ifc_select_chip;
 826        chip->cmdfunc = fsl_ifc_cmdfunc;
 827        chip->waitfunc = fsl_ifc_wait;
 828
 829        chip->bbt_td = &bbt_main_descr;
 830        chip->bbt_md = &bbt_mirror_descr;
 831
 832        ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr);
 833
 834        /* set up nand options */
 835        chip->bbt_options = NAND_BBT_USE_FLASH;
 836        chip->options = NAND_NO_SUBPAGE_WRITE;
 837
 838        if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
 839                & CSPR_PORT_SIZE_16) {
 840                chip->read_byte = fsl_ifc_read_byte16;
 841                chip->options |= NAND_BUSWIDTH_16;
 842        } else {
 843                chip->read_byte = fsl_ifc_read_byte;
 844        }
 845
 846        chip->controller = &ifc_nand_ctrl->controller;
 847        nand_set_controller_data(chip, priv);
 848
 849        chip->ecc.read_page = fsl_ifc_read_page;
 850        chip->ecc.write_page = fsl_ifc_write_page;
 851
 852        csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
 853
 854        switch (csor & CSOR_NAND_PGS_MASK) {
 855        case CSOR_NAND_PGS_512:
 856                if (!(chip->options & NAND_BUSWIDTH_16)) {
 857                        /* Avoid conflict with bad block marker */
 858                        bbt_main_descr.offs = 0;
 859                        bbt_mirror_descr.offs = 0;
 860                }
 861
 862                priv->bufnum_mask = 15;
 863                break;
 864
 865        case CSOR_NAND_PGS_2K:
 866                priv->bufnum_mask = 3;
 867                break;
 868
 869        case CSOR_NAND_PGS_4K:
 870                priv->bufnum_mask = 1;
 871                break;
 872
 873        case CSOR_NAND_PGS_8K:
 874                priv->bufnum_mask = 0;
 875                break;
 876
 877        default:
 878                dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
 879                return -ENODEV;
 880        }
 881
 882        /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
 883        if (csor & CSOR_NAND_ECC_DEC_EN) {
 884                chip->ecc.mode = NAND_ECC_HW;
 885                mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
 886
 887                /* Hardware generates ECC per 512 Bytes */
 888                chip->ecc.size = 512;
 889                if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
 890                        chip->ecc.bytes = 8;
 891                        chip->ecc.strength = 4;
 892                } else {
 893                        chip->ecc.bytes = 16;
 894                        chip->ecc.strength = 8;
 895                }
 896        } else {
 897                chip->ecc.mode = NAND_ECC_SOFT;
 898                chip->ecc.algo = NAND_ECC_HAMMING;
 899        }
 900
 901        if (ctrl->version == FSL_IFC_VERSION_1_1_0)
 902                fsl_ifc_sram_init(priv);
 903
 904        return 0;
 905}
 906
 907static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
 908{
 909        struct mtd_info *mtd = nand_to_mtd(&priv->chip);
 910
 911        nand_release(mtd);
 912
 913        kfree(mtd->name);
 914
 915        if (priv->vbase)
 916                iounmap(priv->vbase);
 917
 918        ifc_nand_ctrl->chips[priv->bank] = NULL;
 919
 920        return 0;
 921}
 922
 923static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank,
 924                      phys_addr_t addr)
 925{
 926        u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr);
 927
 928        if (!(cspr & CSPR_V))
 929                return 0;
 930        if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
 931                return 0;
 932
 933        return (cspr & CSPR_BA) == convert_ifc_address(addr);
 934}
 935
 936static DEFINE_MUTEX(fsl_ifc_nand_mutex);
 937
 938static int fsl_ifc_nand_probe(struct platform_device *dev)
 939{
 940        struct fsl_ifc_runtime __iomem *ifc;
 941        struct fsl_ifc_mtd *priv;
 942        struct resource res;
 943        static const char *part_probe_types[]
 944                = { "cmdlinepart", "RedBoot", "ofpart", NULL };
 945        int ret;
 946        int bank;
 947        struct device_node *node = dev->dev.of_node;
 948        struct mtd_info *mtd;
 949
 950        if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs)
 951                return -ENODEV;
 952        ifc = fsl_ifc_ctrl_dev->rregs;
 953
 954        /* get, allocate and map the memory resource */
 955        ret = of_address_to_resource(node, 0, &res);
 956        if (ret) {
 957                dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
 958                return ret;
 959        }
 960
 961        /* find which chip select it is connected to */
 962        for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
 963                if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start))
 964                        break;
 965        }
 966
 967        if (bank >= fsl_ifc_ctrl_dev->banks) {
 968                dev_err(&dev->dev, "%s: address did not match any chip selects\n",
 969                        __func__);
 970                return -ENODEV;
 971        }
 972
 973        priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
 974        if (!priv)
 975                return -ENOMEM;
 976
 977        mutex_lock(&fsl_ifc_nand_mutex);
 978        if (!fsl_ifc_ctrl_dev->nand) {
 979                ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
 980                if (!ifc_nand_ctrl) {
 981                        mutex_unlock(&fsl_ifc_nand_mutex);
 982                        return -ENOMEM;
 983                }
 984
 985                ifc_nand_ctrl->read_bytes = 0;
 986                ifc_nand_ctrl->index = 0;
 987                ifc_nand_ctrl->addr = NULL;
 988                fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
 989
 990                nand_hw_control_init(&ifc_nand_ctrl->controller);
 991        } else {
 992                ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
 993        }
 994        mutex_unlock(&fsl_ifc_nand_mutex);
 995
 996        ifc_nand_ctrl->chips[bank] = priv;
 997        priv->bank = bank;
 998        priv->ctrl = fsl_ifc_ctrl_dev;
 999        priv->dev = &dev->dev;
1000
1001        priv->vbase = ioremap(res.start, resource_size(&res));
1002        if (!priv->vbase) {
1003                dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1004                ret = -ENOMEM;
1005                goto err;
1006        }
1007
1008        dev_set_drvdata(priv->dev, priv);
1009
1010        ifc_out32(IFC_NAND_EVTER_EN_OPC_EN |
1011                  IFC_NAND_EVTER_EN_FTOER_EN |
1012                  IFC_NAND_EVTER_EN_WPER_EN,
1013                  &ifc->ifc_nand.nand_evter_en);
1014
1015        /* enable NAND Machine Interrupts */
1016        ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN |
1017                  IFC_NAND_EVTER_INTR_FTOERIR_EN |
1018                  IFC_NAND_EVTER_INTR_WPERIR_EN,
1019                  &ifc->ifc_nand.nand_evter_intr_en);
1020
1021        mtd = nand_to_mtd(&priv->chip);
1022        mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
1023        if (!mtd->name) {
1024                ret = -ENOMEM;
1025                goto err;
1026        }
1027
1028        ret = fsl_ifc_chip_init(priv);
1029        if (ret)
1030                goto err;
1031
1032        ret = nand_scan_ident(mtd, 1, NULL);
1033        if (ret)
1034                goto err;
1035
1036        ret = fsl_ifc_chip_init_tail(mtd);
1037        if (ret)
1038                goto err;
1039
1040        ret = nand_scan_tail(mtd);
1041        if (ret)
1042                goto err;
1043
1044        /* First look for RedBoot table or partitions on the command
1045         * line, these take precedence over device tree information */
1046        mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
1047
1048        dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1049                 (unsigned long long)res.start, priv->bank);
1050        return 0;
1051
1052err:
1053        fsl_ifc_chip_remove(priv);
1054        return ret;
1055}
1056
1057static int fsl_ifc_nand_remove(struct platform_device *dev)
1058{
1059        struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1060
1061        fsl_ifc_chip_remove(priv);
1062
1063        mutex_lock(&fsl_ifc_nand_mutex);
1064        ifc_nand_ctrl->counter--;
1065        if (!ifc_nand_ctrl->counter) {
1066                fsl_ifc_ctrl_dev->nand = NULL;
1067                kfree(ifc_nand_ctrl);
1068        }
1069        mutex_unlock(&fsl_ifc_nand_mutex);
1070
1071        return 0;
1072}
1073
1074static const struct of_device_id fsl_ifc_nand_match[] = {
1075        {
1076                .compatible = "fsl,ifc-nand",
1077        },
1078        {}
1079};
1080MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match);
1081
1082static struct platform_driver fsl_ifc_nand_driver = {
1083        .driver = {
1084                .name   = "fsl,ifc-nand",
1085                .of_match_table = fsl_ifc_nand_match,
1086        },
1087        .probe       = fsl_ifc_nand_probe,
1088        .remove      = fsl_ifc_nand_remove,
1089};
1090
1091module_platform_driver(fsl_ifc_nand_driver);
1092
1093MODULE_LICENSE("GPL");
1094MODULE_AUTHOR("Freescale");
1095MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");
1096