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36#include <linux/pci.h>
37
38#include "t4vf_common.h"
39#include "t4vf_defs.h"
40
41#include "../cxgb4/t4_regs.h"
42#include "../cxgb4/t4_values.h"
43#include "../cxgb4/t4fw_api.h"
44
45
46
47
48
49
50int t4vf_wait_dev_ready(struct adapter *adapter)
51{
52 const u32 whoami = T4VF_PL_BASE_ADDR + PL_VF_WHOAMI;
53 const u32 notready1 = 0xffffffff;
54 const u32 notready2 = 0xeeeeeeee;
55 u32 val;
56
57 val = t4_read_reg(adapter, whoami);
58 if (val != notready1 && val != notready2)
59 return 0;
60 msleep(500);
61 val = t4_read_reg(adapter, whoami);
62 if (val != notready1 && val != notready2)
63 return 0;
64 else
65 return -EIO;
66}
67
68
69
70
71
72static void get_mbox_rpl(struct adapter *adapter, __be64 *rpl, int size,
73 u32 mbox_data)
74{
75 for ( ; size; size -= 8, mbox_data += 8)
76 *rpl++ = cpu_to_be64(t4_read_reg64(adapter, mbox_data));
77}
78
79
80
81
82
83
84
85
86
87static void t4vf_record_mbox(struct adapter *adapter, const __be64 *cmd,
88 int size, int access, int execute)
89{
90 struct mbox_cmd_log *log = adapter->mbox_log;
91 struct mbox_cmd *entry;
92 int i;
93
94 entry = mbox_cmd_log_entry(log, log->cursor++);
95 if (log->cursor == log->size)
96 log->cursor = 0;
97
98 for (i = 0; i < size / 8; i++)
99 entry->cmd[i] = be64_to_cpu(cmd[i]);
100 while (i < MBOX_LEN / 8)
101 entry->cmd[i++] = 0;
102 entry->timestamp = jiffies;
103 entry->seqno = log->seqno++;
104 entry->access = access;
105 entry->execute = execute;
106}
107
108
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127
128int t4vf_wr_mbox_core(struct adapter *adapter, const void *cmd, int size,
129 void *rpl, bool sleep_ok)
130{
131 static const int delay[] = {
132 1, 1, 3, 5, 10, 10, 20, 50, 100
133 };
134
135 u16 access = 0, execute = 0;
136 u32 v, mbox_data;
137 int i, ms, delay_idx, ret;
138 const __be64 *p;
139 u32 mbox_ctl = T4VF_CIM_BASE_ADDR + CIM_VF_EXT_MAILBOX_CTRL;
140 u32 cmd_op = FW_CMD_OP_G(be32_to_cpu(((struct fw_cmd_hdr *)cmd)->hi));
141 __be64 cmd_rpl[MBOX_LEN / 8];
142 struct mbox_list entry;
143
144
145
146
147 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
148 mbox_data = T4VF_MBDATA_BASE_ADDR;
149 else
150 mbox_data = T6VF_MBDATA_BASE_ADDR;
151
152
153
154
155
156 if ((size % 16) != 0 ||
157 size > NUM_CIM_VF_MAILBOX_DATA_INSTANCES * 4)
158 return -EINVAL;
159
160
161
162
163
164
165 spin_lock(&adapter->mbox_lock);
166 list_add_tail(&entry.list, &adapter->mlist.list);
167 spin_unlock(&adapter->mbox_lock);
168
169 delay_idx = 0;
170 ms = delay[0];
171
172 for (i = 0; ; i += ms) {
173
174
175
176
177
178 if (i > FW_CMD_MAX_TIMEOUT) {
179 spin_lock(&adapter->mbox_lock);
180 list_del(&entry.list);
181 spin_unlock(&adapter->mbox_lock);
182 ret = -EBUSY;
183 t4vf_record_mbox(adapter, cmd, size, access, ret);
184 return ret;
185 }
186
187
188
189
190 if (list_first_entry(&adapter->mlist.list, struct mbox_list,
191 list) == &entry)
192 break;
193
194
195 if (sleep_ok) {
196 ms = delay[delay_idx];
197 if (delay_idx < ARRAY_SIZE(delay) - 1)
198 delay_idx++;
199 msleep(ms);
200 } else {
201 mdelay(ms);
202 }
203 }
204
205
206
207
208
209 v = MBOWNER_G(t4_read_reg(adapter, mbox_ctl));
210 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
211 v = MBOWNER_G(t4_read_reg(adapter, mbox_ctl));
212 if (v != MBOX_OWNER_DRV) {
213 spin_lock(&adapter->mbox_lock);
214 list_del(&entry.list);
215 spin_unlock(&adapter->mbox_lock);
216 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
217 t4vf_record_mbox(adapter, cmd, size, access, ret);
218 return ret;
219 }
220
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231
232
233
234 if (cmd_op != FW_VI_STATS_CMD)
235 t4vf_record_mbox(adapter, cmd, size, access, 0);
236 for (i = 0, p = cmd; i < size; i += 8)
237 t4_write_reg64(adapter, mbox_data + i, be64_to_cpu(*p++));
238 t4_read_reg(adapter, mbox_data);
239
240 t4_write_reg(adapter, mbox_ctl,
241 MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
242 t4_read_reg(adapter, mbox_ctl);
243
244
245
246
247 delay_idx = 0;
248 ms = delay[0];
249
250 for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) {
251 if (sleep_ok) {
252 ms = delay[delay_idx];
253 if (delay_idx < ARRAY_SIZE(delay) - 1)
254 delay_idx++;
255 msleep(ms);
256 } else
257 mdelay(ms);
258
259
260
261
262 v = t4_read_reg(adapter, mbox_ctl);
263 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
264
265
266
267
268 if ((v & MBMSGVALID_F) == 0) {
269 t4_write_reg(adapter, mbox_ctl,
270 MBOWNER_V(MBOX_OWNER_NONE));
271 continue;
272 }
273
274
275
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277
278
279
280
281 get_mbox_rpl(adapter, cmd_rpl, size, mbox_data);
282
283
284 v = be64_to_cpu(cmd_rpl[0]);
285
286 if (rpl) {
287
288 WARN_ON((be32_to_cpu(*(const __be32 *)cmd)
289 & FW_CMD_REQUEST_F) == 0);
290 memcpy(rpl, cmd_rpl, size);
291 WARN_ON((be32_to_cpu(*(__be32 *)rpl)
292 & FW_CMD_REQUEST_F) != 0);
293 }
294 t4_write_reg(adapter, mbox_ctl,
295 MBOWNER_V(MBOX_OWNER_NONE));
296 execute = i + ms;
297 if (cmd_op != FW_VI_STATS_CMD)
298 t4vf_record_mbox(adapter, cmd_rpl, size, access,
299 execute);
300 spin_lock(&adapter->mbox_lock);
301 list_del(&entry.list);
302 spin_unlock(&adapter->mbox_lock);
303 return -FW_CMD_RETVAL_G(v);
304 }
305 }
306
307
308 ret = -ETIMEDOUT;
309 t4vf_record_mbox(adapter, cmd, size, access, ret);
310 spin_lock(&adapter->mbox_lock);
311 list_del(&entry.list);
312 spin_unlock(&adapter->mbox_lock);
313 return ret;
314}
315
316#define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
317 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_25G | \
318 FW_PORT_CAP_SPEED_40G | FW_PORT_CAP_SPEED_100G | \
319 FW_PORT_CAP_ANEG)
320
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327
328
329static void init_link_config(struct link_config *lc, unsigned int caps)
330{
331 lc->supported = caps;
332 lc->lp_advertising = 0;
333 lc->requested_speed = 0;
334 lc->speed = 0;
335 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
336 if (lc->supported & FW_PORT_CAP_ANEG) {
337 lc->advertising = lc->supported & ADVERT_MASK;
338 lc->autoneg = AUTONEG_ENABLE;
339 lc->requested_fc |= PAUSE_AUTONEG;
340 } else {
341 lc->advertising = 0;
342 lc->autoneg = AUTONEG_DISABLE;
343 }
344}
345
346
347
348
349
350
351int t4vf_port_init(struct adapter *adapter, int pidx)
352{
353 struct port_info *pi = adap2pinfo(adapter, pidx);
354 struct fw_vi_cmd vi_cmd, vi_rpl;
355 struct fw_port_cmd port_cmd, port_rpl;
356 int v;
357
358
359
360
361
362 memset(&vi_cmd, 0, sizeof(vi_cmd));
363 vi_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
364 FW_CMD_REQUEST_F |
365 FW_CMD_READ_F);
366 vi_cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(vi_cmd));
367 vi_cmd.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(pi->viid));
368 v = t4vf_wr_mbox(adapter, &vi_cmd, sizeof(vi_cmd), &vi_rpl);
369 if (v)
370 return v;
371
372 BUG_ON(pi->port_id != FW_VI_CMD_PORTID_G(vi_rpl.portid_pkd));
373 pi->rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(vi_rpl.rsssize_pkd));
374 t4_os_set_hw_addr(adapter, pidx, vi_rpl.mac);
375
376
377
378
379
380 if (!(adapter->params.vfres.r_caps & FW_CMD_CAP_PORT))
381 return 0;
382
383 memset(&port_cmd, 0, sizeof(port_cmd));
384 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
385 FW_CMD_REQUEST_F |
386 FW_CMD_READ_F |
387 FW_PORT_CMD_PORTID_V(pi->port_id));
388 port_cmd.action_to_len16 =
389 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
390 FW_LEN16(port_cmd));
391 v = t4vf_wr_mbox(adapter, &port_cmd, sizeof(port_cmd), &port_rpl);
392 if (v)
393 return v;
394
395 v = be32_to_cpu(port_rpl.u.info.lstatus_to_modtype);
396 pi->mdio_addr = (v & FW_PORT_CMD_MDIOCAP_F) ?
397 FW_PORT_CMD_MDIOADDR_G(v) : -1;
398 pi->port_type = FW_PORT_CMD_PTYPE_G(v);
399 pi->mod_type = FW_PORT_MOD_TYPE_NA;
400
401 init_link_config(&pi->link_cfg, be16_to_cpu(port_rpl.u.info.pcap));
402
403 return 0;
404}
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413
414int t4vf_fw_reset(struct adapter *adapter)
415{
416 struct fw_reset_cmd cmd;
417
418 memset(&cmd, 0, sizeof(cmd));
419 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RESET_CMD) |
420 FW_CMD_WRITE_F);
421 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
422 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
423}
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434
435static int t4vf_query_params(struct adapter *adapter, unsigned int nparams,
436 const u32 *params, u32 *vals)
437{
438 int i, ret;
439 struct fw_params_cmd cmd, rpl;
440 struct fw_params_param *p;
441 size_t len16;
442
443 if (nparams > 7)
444 return -EINVAL;
445
446 memset(&cmd, 0, sizeof(cmd));
447 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
448 FW_CMD_REQUEST_F |
449 FW_CMD_READ_F);
450 len16 = DIV_ROUND_UP(offsetof(struct fw_params_cmd,
451 param[nparams].mnem), 16);
452 cmd.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(len16));
453 for (i = 0, p = &cmd.param[0]; i < nparams; i++, p++)
454 p->mnem = htonl(*params++);
455
456 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
457 if (ret == 0)
458 for (i = 0, p = &rpl.param[0]; i < nparams; i++, p++)
459 *vals++ = be32_to_cpu(p->val);
460 return ret;
461}
462
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471
472
473int t4vf_set_params(struct adapter *adapter, unsigned int nparams,
474 const u32 *params, const u32 *vals)
475{
476 int i;
477 struct fw_params_cmd cmd;
478 struct fw_params_param *p;
479 size_t len16;
480
481 if (nparams > 7)
482 return -EINVAL;
483
484 memset(&cmd, 0, sizeof(cmd));
485 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
486 FW_CMD_REQUEST_F |
487 FW_CMD_WRITE_F);
488 len16 = DIV_ROUND_UP(offsetof(struct fw_params_cmd,
489 param[nparams]), 16);
490 cmd.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(len16));
491 for (i = 0, p = &cmd.param[0]; i < nparams; i++, p++) {
492 p->mnem = cpu_to_be32(*params++);
493 p->val = cpu_to_be32(*vals++);
494 }
495
496 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
497}
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509
510int t4vf_fl_pkt_align(struct adapter *adapter)
511{
512 u32 sge_control, sge_control2;
513 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
514
515 sge_control = adapter->params.sge.sge_control;
516
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527
528
529 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
530 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
531 else
532 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
533
534 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
535
536 fl_align = ingpadboundary;
537 if (!is_t4(adapter->params.chip)) {
538
539
540
541 sge_control2 = adapter->params.sge.sge_control2;
542 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
543 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
544 ingpackboundary = 16;
545 else
546 ingpackboundary = 1 << (ingpackboundary +
547 INGPACKBOUNDARY_SHIFT_X);
548
549 fl_align = max(ingpadboundary, ingpackboundary);
550 }
551 return fl_align;
552}
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579int t4vf_bar2_sge_qregs(struct adapter *adapter,
580 unsigned int qid,
581 enum t4_bar2_qtype qtype,
582 u64 *pbar2_qoffset,
583 unsigned int *pbar2_qid)
584{
585 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
586 u64 bar2_page_offset, bar2_qoffset;
587 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
588
589
590
591 if (is_t4(adapter->params.chip))
592 return -EINVAL;
593
594
595
596 page_shift = adapter->params.sge.sge_vf_hps + 10;
597 page_size = 1 << page_shift;
598
599
600
601 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
602 ? adapter->params.sge.sge_vf_eq_qpp
603 : adapter->params.sge.sge_vf_iq_qpp);
604 qpp_mask = (1 << qpp_shift) - 1;
605
606
607
608
609
610
611 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
612 bar2_qid = qid & qpp_mask;
613 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
614
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629
630
631 bar2_qoffset = bar2_page_offset;
632 bar2_qinferred = (bar2_qid_offset < page_size);
633 if (bar2_qinferred) {
634 bar2_qoffset += bar2_qid_offset;
635 bar2_qid = 0;
636 }
637
638 *pbar2_qoffset = bar2_qoffset;
639 *pbar2_qid = bar2_qid;
640 return 0;
641}
642
643unsigned int t4vf_get_pf_from_vf(struct adapter *adapter)
644{
645 u32 whoami;
646
647 whoami = t4_read_reg(adapter, T4VF_PL_BASE_ADDR + PL_VF_WHOAMI_A);
648 return (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
649 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami));
650}
651
652
653
654
655
656
657
658
659
660int t4vf_get_sge_params(struct adapter *adapter)
661{
662 struct sge_params *sge_params = &adapter->params.sge;
663 u32 params[7], vals[7];
664 int v;
665
666 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
667 FW_PARAMS_PARAM_XYZ_V(SGE_CONTROL_A));
668 params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
669 FW_PARAMS_PARAM_XYZ_V(SGE_HOST_PAGE_SIZE_A));
670 params[2] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
671 FW_PARAMS_PARAM_XYZ_V(SGE_FL_BUFFER_SIZE0_A));
672 params[3] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
673 FW_PARAMS_PARAM_XYZ_V(SGE_FL_BUFFER_SIZE1_A));
674 params[4] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
675 FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_0_AND_1_A));
676 params[5] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
677 FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_2_AND_3_A));
678 params[6] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
679 FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_4_AND_5_A));
680 v = t4vf_query_params(adapter, 7, params, vals);
681 if (v)
682 return v;
683 sge_params->sge_control = vals[0];
684 sge_params->sge_host_page_size = vals[1];
685 sge_params->sge_fl_buffer_size[0] = vals[2];
686 sge_params->sge_fl_buffer_size[1] = vals[3];
687 sge_params->sge_timer_value_0_and_1 = vals[4];
688 sge_params->sge_timer_value_2_and_3 = vals[5];
689 sge_params->sge_timer_value_4_and_5 = vals[6];
690
691
692
693
694
695
696
697
698
699
700
701 if (!is_t4(adapter->params.chip)) {
702 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
703 FW_PARAMS_PARAM_XYZ_V(SGE_CONTROL2_A));
704 v = t4vf_query_params(adapter, 1, params, vals);
705 if (v != FW_SUCCESS) {
706 dev_err(adapter->pdev_dev,
707 "Unable to get SGE Control2; "
708 "probably old firmware.\n");
709 return v;
710 }
711 sge_params->sge_control2 = vals[0];
712 }
713
714 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
715 FW_PARAMS_PARAM_XYZ_V(SGE_INGRESS_RX_THRESHOLD_A));
716 params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
717 FW_PARAMS_PARAM_XYZ_V(SGE_CONM_CTRL_A));
718 v = t4vf_query_params(adapter, 2, params, vals);
719 if (v)
720 return v;
721 sge_params->sge_ingress_rx_threshold = vals[0];
722 sge_params->sge_congestion_control = vals[1];
723
724
725
726
727
728 if (!is_t4(adapter->params.chip)) {
729 unsigned int pf, s_hps, s_qpp;
730
731 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
732 FW_PARAMS_PARAM_XYZ_V(
733 SGE_EGRESS_QUEUES_PER_PAGE_VF_A));
734 params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
735 FW_PARAMS_PARAM_XYZ_V(
736 SGE_INGRESS_QUEUES_PER_PAGE_VF_A));
737 v = t4vf_query_params(adapter, 2, params, vals);
738 if (v != FW_SUCCESS) {
739 dev_warn(adapter->pdev_dev,
740 "Unable to get VF SGE Queues/Page; "
741 "probably old firmware.\n");
742 return v;
743 }
744 sge_params->sge_egress_queues_per_page = vals[0];
745 sge_params->sge_ingress_queues_per_page = vals[1];
746
747
748
749
750
751
752 pf = t4vf_get_pf_from_vf(adapter);
753 s_hps = (HOSTPAGESIZEPF0_S +
754 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * pf);
755 sge_params->sge_vf_hps =
756 ((sge_params->sge_host_page_size >> s_hps)
757 & HOSTPAGESIZEPF0_M);
758
759 s_qpp = (QUEUESPERPAGEPF0_S +
760 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * pf);
761 sge_params->sge_vf_eq_qpp =
762 ((sge_params->sge_egress_queues_per_page >> s_qpp)
763 & QUEUESPERPAGEPF0_M);
764 sge_params->sge_vf_iq_qpp =
765 ((sge_params->sge_ingress_queues_per_page >> s_qpp)
766 & QUEUESPERPAGEPF0_M);
767 }
768
769 return 0;
770}
771
772
773
774
775
776
777
778
779int t4vf_get_vpd_params(struct adapter *adapter)
780{
781 struct vpd_params *vpd_params = &adapter->params.vpd;
782 u32 params[7], vals[7];
783 int v;
784
785 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
786 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
787 v = t4vf_query_params(adapter, 1, params, vals);
788 if (v)
789 return v;
790 vpd_params->cclk = vals[0];
791
792 return 0;
793}
794
795
796
797
798
799
800
801
802int t4vf_get_dev_params(struct adapter *adapter)
803{
804 struct dev_params *dev_params = &adapter->params.dev;
805 u32 params[7], vals[7];
806 int v;
807
808 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
809 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWREV));
810 params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
811 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPREV));
812 v = t4vf_query_params(adapter, 2, params, vals);
813 if (v)
814 return v;
815 dev_params->fwrev = vals[0];
816 dev_params->tprev = vals[1];
817
818 return 0;
819}
820
821
822
823
824
825
826
827
828int t4vf_get_rss_glb_config(struct adapter *adapter)
829{
830 struct rss_params *rss = &adapter->params.rss;
831 struct fw_rss_glb_config_cmd cmd, rpl;
832 int v;
833
834
835
836
837
838 memset(&cmd, 0, sizeof(cmd));
839 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
840 FW_CMD_REQUEST_F |
841 FW_CMD_READ_F);
842 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
843 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
844 if (v)
845 return v;
846
847
848
849
850
851
852
853 rss->mode = FW_RSS_GLB_CONFIG_CMD_MODE_G(
854 be32_to_cpu(rpl.u.manual.mode_pkd));
855 switch (rss->mode) {
856 case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL: {
857 u32 word = be32_to_cpu(
858 rpl.u.basicvirtual.synmapen_to_hashtoeplitz);
859
860 rss->u.basicvirtual.synmapen =
861 ((word & FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F) != 0);
862 rss->u.basicvirtual.syn4tupenipv6 =
863 ((word & FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F) != 0);
864 rss->u.basicvirtual.syn2tupenipv6 =
865 ((word & FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F) != 0);
866 rss->u.basicvirtual.syn4tupenipv4 =
867 ((word & FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F) != 0);
868 rss->u.basicvirtual.syn2tupenipv4 =
869 ((word & FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F) != 0);
870
871 rss->u.basicvirtual.ofdmapen =
872 ((word & FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F) != 0);
873
874 rss->u.basicvirtual.tnlmapen =
875 ((word & FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F) != 0);
876 rss->u.basicvirtual.tnlalllookup =
877 ((word & FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F) != 0);
878
879 rss->u.basicvirtual.hashtoeplitz =
880 ((word & FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F) != 0);
881
882
883 if (!rss->u.basicvirtual.tnlmapen)
884 return -EINVAL;
885 break;
886 }
887
888 default:
889
890 return -EINVAL;
891 }
892
893 return 0;
894}
895
896
897
898
899
900
901
902
903int t4vf_get_vfres(struct adapter *adapter)
904{
905 struct vf_resources *vfres = &adapter->params.vfres;
906 struct fw_pfvf_cmd cmd, rpl;
907 int v;
908 u32 word;
909
910
911
912
913
914 memset(&cmd, 0, sizeof(cmd));
915 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
916 FW_CMD_REQUEST_F |
917 FW_CMD_READ_F);
918 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
919 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
920 if (v)
921 return v;
922
923
924
925
926 word = be32_to_cpu(rpl.niqflint_niq);
927 vfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word);
928 vfres->niq = FW_PFVF_CMD_NIQ_G(word);
929
930 word = be32_to_cpu(rpl.type_to_neq);
931 vfres->neq = FW_PFVF_CMD_NEQ_G(word);
932 vfres->pmask = FW_PFVF_CMD_PMASK_G(word);
933
934 word = be32_to_cpu(rpl.tc_to_nexactf);
935 vfres->tc = FW_PFVF_CMD_TC_G(word);
936 vfres->nvi = FW_PFVF_CMD_NVI_G(word);
937 vfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word);
938
939 word = be32_to_cpu(rpl.r_caps_to_nethctrl);
940 vfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word);
941 vfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word);
942 vfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word);
943
944 return 0;
945}
946
947
948
949
950
951
952
953
954
955
956int t4vf_read_rss_vi_config(struct adapter *adapter, unsigned int viid,
957 union rss_vi_config *config)
958{
959 struct fw_rss_vi_config_cmd cmd, rpl;
960 int v;
961
962 memset(&cmd, 0, sizeof(cmd));
963 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
964 FW_CMD_REQUEST_F |
965 FW_CMD_READ_F |
966 FW_RSS_VI_CONFIG_CMD_VIID(viid));
967 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
968 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
969 if (v)
970 return v;
971
972 switch (adapter->params.rss.mode) {
973 case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL: {
974 u32 word = be32_to_cpu(rpl.u.basicvirtual.defaultq_to_udpen);
975
976 config->basicvirtual.ip6fourtupen =
977 ((word & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F) != 0);
978 config->basicvirtual.ip6twotupen =
979 ((word & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F) != 0);
980 config->basicvirtual.ip4fourtupen =
981 ((word & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F) != 0);
982 config->basicvirtual.ip4twotupen =
983 ((word & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F) != 0);
984 config->basicvirtual.udpen =
985 ((word & FW_RSS_VI_CONFIG_CMD_UDPEN_F) != 0);
986 config->basicvirtual.defaultq =
987 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(word);
988 break;
989 }
990
991 default:
992 return -EINVAL;
993 }
994
995 return 0;
996}
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007int t4vf_write_rss_vi_config(struct adapter *adapter, unsigned int viid,
1008 union rss_vi_config *config)
1009{
1010 struct fw_rss_vi_config_cmd cmd, rpl;
1011
1012 memset(&cmd, 0, sizeof(cmd));
1013 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
1014 FW_CMD_REQUEST_F |
1015 FW_CMD_WRITE_F |
1016 FW_RSS_VI_CONFIG_CMD_VIID(viid));
1017 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1018 switch (adapter->params.rss.mode) {
1019 case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL: {
1020 u32 word = 0;
1021
1022 if (config->basicvirtual.ip6fourtupen)
1023 word |= FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F;
1024 if (config->basicvirtual.ip6twotupen)
1025 word |= FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F;
1026 if (config->basicvirtual.ip4fourtupen)
1027 word |= FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F;
1028 if (config->basicvirtual.ip4twotupen)
1029 word |= FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F;
1030 if (config->basicvirtual.udpen)
1031 word |= FW_RSS_VI_CONFIG_CMD_UDPEN_F;
1032 word |= FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(
1033 config->basicvirtual.defaultq);
1034 cmd.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(word);
1035 break;
1036 }
1037
1038 default:
1039 return -EINVAL;
1040 }
1041
1042 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
1043}
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060int t4vf_config_rss_range(struct adapter *adapter, unsigned int viid,
1061 int start, int n, const u16 *rspq, int nrspq)
1062{
1063 const u16 *rsp = rspq;
1064 const u16 *rsp_end = rspq+nrspq;
1065 struct fw_rss_ind_tbl_cmd cmd;
1066
1067
1068
1069
1070 memset(&cmd, 0, sizeof(cmd));
1071 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
1072 FW_CMD_REQUEST_F |
1073 FW_CMD_WRITE_F |
1074 FW_RSS_IND_TBL_CMD_VIID_V(viid));
1075 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1076
1077
1078
1079
1080
1081
1082
1083 while (n > 0) {
1084 __be32 *qp = &cmd.iq0_to_iq2;
1085 int nq = min(n, 32);
1086 int ret;
1087
1088
1089
1090
1091
1092 cmd.niqid = cpu_to_be16(nq);
1093 cmd.startidx = cpu_to_be16(start);
1094
1095
1096
1097
1098 start += nq;
1099 n -= nq;
1100
1101
1102
1103
1104
1105
1106 while (nq > 0) {
1107
1108
1109
1110
1111
1112
1113 u16 qbuf[3];
1114 u16 *qbp = qbuf;
1115 int nqbuf = min(3, nq);
1116
1117 nq -= nqbuf;
1118 qbuf[0] = qbuf[1] = qbuf[2] = 0;
1119 while (nqbuf) {
1120 nqbuf--;
1121 *qbp++ = *rsp++;
1122 if (rsp >= rsp_end)
1123 rsp = rspq;
1124 }
1125 *qp++ = cpu_to_be32(FW_RSS_IND_TBL_CMD_IQ0_V(qbuf[0]) |
1126 FW_RSS_IND_TBL_CMD_IQ1_V(qbuf[1]) |
1127 FW_RSS_IND_TBL_CMD_IQ2_V(qbuf[2]));
1128 }
1129
1130
1131
1132
1133
1134 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1135 if (ret)
1136 return ret;
1137 }
1138 return 0;
1139}
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150int t4vf_alloc_vi(struct adapter *adapter, int port_id)
1151{
1152 struct fw_vi_cmd cmd, rpl;
1153 int v;
1154
1155
1156
1157
1158
1159 memset(&cmd, 0, sizeof(cmd));
1160 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
1161 FW_CMD_REQUEST_F |
1162 FW_CMD_WRITE_F |
1163 FW_CMD_EXEC_F);
1164 cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(cmd) |
1165 FW_VI_CMD_ALLOC_F);
1166 cmd.portid_pkd = FW_VI_CMD_PORTID_V(port_id);
1167 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
1168 if (v)
1169 return v;
1170
1171 return FW_VI_CMD_VIID_G(be16_to_cpu(rpl.type_viid));
1172}
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182int t4vf_free_vi(struct adapter *adapter, int viid)
1183{
1184 struct fw_vi_cmd cmd;
1185
1186
1187
1188
1189 memset(&cmd, 0, sizeof(cmd));
1190 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
1191 FW_CMD_REQUEST_F |
1192 FW_CMD_EXEC_F);
1193 cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(cmd) |
1194 FW_VI_CMD_FREE_F);
1195 cmd.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
1196 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1197}
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208int t4vf_enable_vi(struct adapter *adapter, unsigned int viid,
1209 bool rx_en, bool tx_en)
1210{
1211 struct fw_vi_enable_cmd cmd;
1212
1213 memset(&cmd, 0, sizeof(cmd));
1214 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
1215 FW_CMD_REQUEST_F |
1216 FW_CMD_EXEC_F |
1217 FW_VI_ENABLE_CMD_VIID_V(viid));
1218 cmd.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
1219 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
1220 FW_LEN16(cmd));
1221 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1222}
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232int t4vf_identify_port(struct adapter *adapter, unsigned int viid,
1233 unsigned int nblinks)
1234{
1235 struct fw_vi_enable_cmd cmd;
1236
1237 memset(&cmd, 0, sizeof(cmd));
1238 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
1239 FW_CMD_REQUEST_F |
1240 FW_CMD_EXEC_F |
1241 FW_VI_ENABLE_CMD_VIID_V(viid));
1242 cmd.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F |
1243 FW_LEN16(cmd));
1244 cmd.blinkdur = cpu_to_be16(nblinks);
1245 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1246}
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261int t4vf_set_rxmode(struct adapter *adapter, unsigned int viid,
1262 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1263 bool sleep_ok)
1264{
1265 struct fw_vi_rxmode_cmd cmd;
1266
1267
1268 if (mtu < 0)
1269 mtu = FW_VI_RXMODE_CMD_MTU_M;
1270 if (promisc < 0)
1271 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
1272 if (all_multi < 0)
1273 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
1274 if (bcast < 0)
1275 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
1276 if (vlanex < 0)
1277 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
1278
1279 memset(&cmd, 0, sizeof(cmd));
1280 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
1281 FW_CMD_REQUEST_F |
1282 FW_CMD_WRITE_F |
1283 FW_VI_RXMODE_CMD_VIID_V(viid));
1284 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1285 cmd.mtu_to_vlanexen =
1286 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
1287 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
1288 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
1289 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
1290 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
1291 return t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), NULL, sleep_ok);
1292}
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315int t4vf_alloc_mac_filt(struct adapter *adapter, unsigned int viid, bool free,
1316 unsigned int naddr, const u8 **addr, u16 *idx,
1317 u64 *hash, bool sleep_ok)
1318{
1319 int offset, ret = 0;
1320 unsigned nfilters = 0;
1321 unsigned int rem = naddr;
1322 struct fw_vi_mac_cmd cmd, rpl;
1323 unsigned int max_naddr = adapter->params.arch.mps_tcam_size;
1324
1325 if (naddr > max_naddr)
1326 return -EINVAL;
1327
1328 for (offset = 0; offset < naddr; ) {
1329 unsigned int fw_naddr = (rem < ARRAY_SIZE(cmd.u.exact)
1330 ? rem
1331 : ARRAY_SIZE(cmd.u.exact));
1332 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1333 u.exact[fw_naddr]), 16);
1334 struct fw_vi_mac_exact *p;
1335 int i;
1336
1337 memset(&cmd, 0, sizeof(cmd));
1338 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
1339 FW_CMD_REQUEST_F |
1340 FW_CMD_WRITE_F |
1341 (free ? FW_CMD_EXEC_F : 0) |
1342 FW_VI_MAC_CMD_VIID_V(viid));
1343 cmd.freemacs_to_len16 =
1344 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
1345 FW_CMD_LEN16_V(len16));
1346
1347 for (i = 0, p = cmd.u.exact; i < fw_naddr; i++, p++) {
1348 p->valid_to_idx = cpu_to_be16(
1349 FW_VI_MAC_CMD_VALID_F |
1350 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
1351 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
1352 }
1353
1354
1355 ret = t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), &rpl,
1356 sleep_ok);
1357 if (ret && ret != -ENOMEM)
1358 break;
1359
1360 for (i = 0, p = rpl.u.exact; i < fw_naddr; i++, p++) {
1361 u16 index = FW_VI_MAC_CMD_IDX_G(
1362 be16_to_cpu(p->valid_to_idx));
1363
1364 if (idx)
1365 idx[offset+i] =
1366 (index >= max_naddr
1367 ? 0xffff
1368 : index);
1369 if (index < max_naddr)
1370 nfilters++;
1371 else if (hash)
1372 *hash |= (1ULL << hash_mac_addr(addr[offset+i]));
1373 }
1374
1375 free = false;
1376 offset += fw_naddr;
1377 rem -= fw_naddr;
1378 }
1379
1380
1381
1382
1383
1384 if (ret == 0 || ret == -ENOMEM)
1385 ret = nfilters;
1386 return ret;
1387}
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401int t4vf_free_mac_filt(struct adapter *adapter, unsigned int viid,
1402 unsigned int naddr, const u8 **addr, bool sleep_ok)
1403{
1404 int offset, ret = 0;
1405 struct fw_vi_mac_cmd cmd;
1406 unsigned int nfilters = 0;
1407 unsigned int max_naddr = adapter->params.arch.mps_tcam_size;
1408 unsigned int rem = naddr;
1409
1410 if (naddr > max_naddr)
1411 return -EINVAL;
1412
1413 for (offset = 0; offset < (int)naddr ; ) {
1414 unsigned int fw_naddr = (rem < ARRAY_SIZE(cmd.u.exact) ?
1415 rem : ARRAY_SIZE(cmd.u.exact));
1416 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1417 u.exact[fw_naddr]), 16);
1418 struct fw_vi_mac_exact *p;
1419 int i;
1420
1421 memset(&cmd, 0, sizeof(cmd));
1422 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
1423 FW_CMD_REQUEST_F |
1424 FW_CMD_WRITE_F |
1425 FW_CMD_EXEC_V(0) |
1426 FW_VI_MAC_CMD_VIID_V(viid));
1427 cmd.freemacs_to_len16 =
1428 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
1429 FW_CMD_LEN16_V(len16));
1430
1431 for (i = 0, p = cmd.u.exact; i < (int)fw_naddr; i++, p++) {
1432 p->valid_to_idx = cpu_to_be16(
1433 FW_VI_MAC_CMD_VALID_F |
1434 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
1435 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
1436 }
1437
1438 ret = t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), &cmd,
1439 sleep_ok);
1440 if (ret)
1441 break;
1442
1443 for (i = 0, p = cmd.u.exact; i < fw_naddr; i++, p++) {
1444 u16 index = FW_VI_MAC_CMD_IDX_G(
1445 be16_to_cpu(p->valid_to_idx));
1446
1447 if (index < max_naddr)
1448 nfilters++;
1449 }
1450
1451 offset += fw_naddr;
1452 rem -= fw_naddr;
1453 }
1454
1455 if (ret == 0)
1456 ret = nfilters;
1457 return ret;
1458}
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478int t4vf_change_mac(struct adapter *adapter, unsigned int viid,
1479 int idx, const u8 *addr, bool persist)
1480{
1481 int ret;
1482 struct fw_vi_mac_cmd cmd, rpl;
1483 struct fw_vi_mac_exact *p = &cmd.u.exact[0];
1484 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1485 u.exact[1]), 16);
1486 unsigned int max_mac_addr = adapter->params.arch.mps_tcam_size;
1487
1488
1489
1490
1491
1492 if (idx < 0)
1493 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
1494
1495 memset(&cmd, 0, sizeof(cmd));
1496 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
1497 FW_CMD_REQUEST_F |
1498 FW_CMD_WRITE_F |
1499 FW_VI_MAC_CMD_VIID_V(viid));
1500 cmd.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(len16));
1501 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
1502 FW_VI_MAC_CMD_IDX_V(idx));
1503 memcpy(p->macaddr, addr, sizeof(p->macaddr));
1504
1505 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
1506 if (ret == 0) {
1507 p = &rpl.u.exact[0];
1508 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
1509 if (ret >= max_mac_addr)
1510 ret = -ENOMEM;
1511 }
1512 return ret;
1513}
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525int t4vf_set_addr_hash(struct adapter *adapter, unsigned int viid,
1526 bool ucast, u64 vec, bool sleep_ok)
1527{
1528 struct fw_vi_mac_cmd cmd;
1529 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1530 u.exact[0]), 16);
1531
1532 memset(&cmd, 0, sizeof(cmd));
1533 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
1534 FW_CMD_REQUEST_F |
1535 FW_CMD_WRITE_F |
1536 FW_VI_ENABLE_CMD_VIID_V(viid));
1537 cmd.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
1538 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
1539 FW_CMD_LEN16_V(len16));
1540 cmd.u.hash.hashvec = cpu_to_be64(vec);
1541 return t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), NULL, sleep_ok);
1542}
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552int t4vf_get_port_stats(struct adapter *adapter, int pidx,
1553 struct t4vf_port_stats *s)
1554{
1555 struct port_info *pi = adap2pinfo(adapter, pidx);
1556 struct fw_vi_stats_vf fwstats;
1557 unsigned int rem = VI_VF_NUM_STATS;
1558 __be64 *fwsp = (__be64 *)&fwstats;
1559
1560
1561
1562
1563
1564
1565 while (rem) {
1566 unsigned int ix = VI_VF_NUM_STATS - rem;
1567 unsigned int nstats = min(6U, rem);
1568 struct fw_vi_stats_cmd cmd, rpl;
1569 size_t len = (offsetof(struct fw_vi_stats_cmd, u) +
1570 sizeof(struct fw_vi_stats_ctl));
1571 size_t len16 = DIV_ROUND_UP(len, 16);
1572 int ret;
1573
1574 memset(&cmd, 0, sizeof(cmd));
1575 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_STATS_CMD) |
1576 FW_VI_STATS_CMD_VIID_V(pi->viid) |
1577 FW_CMD_REQUEST_F |
1578 FW_CMD_READ_F);
1579 cmd.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(len16));
1580 cmd.u.ctl.nstats_ix =
1581 cpu_to_be16(FW_VI_STATS_CMD_IX_V(ix) |
1582 FW_VI_STATS_CMD_NSTATS_V(nstats));
1583 ret = t4vf_wr_mbox_ns(adapter, &cmd, len, &rpl);
1584 if (ret)
1585 return ret;
1586
1587 memcpy(fwsp, &rpl.u.ctl.stat0, sizeof(__be64) * nstats);
1588
1589 rem -= nstats;
1590 fwsp += nstats;
1591 }
1592
1593
1594
1595
1596 s->tx_bcast_bytes = be64_to_cpu(fwstats.tx_bcast_bytes);
1597 s->tx_bcast_frames = be64_to_cpu(fwstats.tx_bcast_frames);
1598 s->tx_mcast_bytes = be64_to_cpu(fwstats.tx_mcast_bytes);
1599 s->tx_mcast_frames = be64_to_cpu(fwstats.tx_mcast_frames);
1600 s->tx_ucast_bytes = be64_to_cpu(fwstats.tx_ucast_bytes);
1601 s->tx_ucast_frames = be64_to_cpu(fwstats.tx_ucast_frames);
1602 s->tx_drop_frames = be64_to_cpu(fwstats.tx_drop_frames);
1603 s->tx_offload_bytes = be64_to_cpu(fwstats.tx_offload_bytes);
1604 s->tx_offload_frames = be64_to_cpu(fwstats.tx_offload_frames);
1605
1606 s->rx_bcast_bytes = be64_to_cpu(fwstats.rx_bcast_bytes);
1607 s->rx_bcast_frames = be64_to_cpu(fwstats.rx_bcast_frames);
1608 s->rx_mcast_bytes = be64_to_cpu(fwstats.rx_mcast_bytes);
1609 s->rx_mcast_frames = be64_to_cpu(fwstats.rx_mcast_frames);
1610 s->rx_ucast_bytes = be64_to_cpu(fwstats.rx_ucast_bytes);
1611 s->rx_ucast_frames = be64_to_cpu(fwstats.rx_ucast_frames);
1612
1613 s->rx_err_frames = be64_to_cpu(fwstats.rx_err_frames);
1614
1615 return 0;
1616}
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628int t4vf_iq_free(struct adapter *adapter, unsigned int iqtype,
1629 unsigned int iqid, unsigned int fl0id, unsigned int fl1id)
1630{
1631 struct fw_iq_cmd cmd;
1632
1633 memset(&cmd, 0, sizeof(cmd));
1634 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) |
1635 FW_CMD_REQUEST_F |
1636 FW_CMD_EXEC_F);
1637 cmd.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F |
1638 FW_LEN16(cmd));
1639 cmd.type_to_iqandstindex =
1640 cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
1641
1642 cmd.iqid = cpu_to_be16(iqid);
1643 cmd.fl0id = cpu_to_be16(fl0id);
1644 cmd.fl1id = cpu_to_be16(fl1id);
1645 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1646}
1647
1648
1649
1650
1651
1652
1653
1654
1655int t4vf_eth_eq_free(struct adapter *adapter, unsigned int eqid)
1656{
1657 struct fw_eq_eth_cmd cmd;
1658
1659 memset(&cmd, 0, sizeof(cmd));
1660 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
1661 FW_CMD_REQUEST_F |
1662 FW_CMD_EXEC_F);
1663 cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F |
1664 FW_LEN16(cmd));
1665 cmd.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
1666 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1667}
1668
1669
1670
1671
1672
1673
1674
1675
1676int t4vf_handle_fw_rpl(struct adapter *adapter, const __be64 *rpl)
1677{
1678 const struct fw_cmd_hdr *cmd_hdr = (const struct fw_cmd_hdr *)rpl;
1679 u8 opcode = FW_CMD_OP_G(be32_to_cpu(cmd_hdr->hi));
1680
1681 switch (opcode) {
1682 case FW_PORT_CMD: {
1683
1684
1685
1686 const struct fw_port_cmd *port_cmd =
1687 (const struct fw_port_cmd *)rpl;
1688 u32 stat, mod;
1689 int action, port_id, link_ok, speed, fc, pidx;
1690
1691
1692
1693
1694 action = FW_PORT_CMD_ACTION_G(
1695 be32_to_cpu(port_cmd->action_to_len16));
1696 if (action != FW_PORT_ACTION_GET_PORT_INFO) {
1697 dev_err(adapter->pdev_dev,
1698 "Unknown firmware PORT reply action %x\n",
1699 action);
1700 break;
1701 }
1702
1703 port_id = FW_PORT_CMD_PORTID_G(
1704 be32_to_cpu(port_cmd->op_to_portid));
1705
1706 stat = be32_to_cpu(port_cmd->u.info.lstatus_to_modtype);
1707 link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
1708 speed = 0;
1709 fc = 0;
1710 if (stat & FW_PORT_CMD_RXPAUSE_F)
1711 fc |= PAUSE_RX;
1712 if (stat & FW_PORT_CMD_TXPAUSE_F)
1713 fc |= PAUSE_TX;
1714 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
1715 speed = 100;
1716 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
1717 speed = 1000;
1718 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
1719 speed = 10000;
1720 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
1721 speed = 25000;
1722 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
1723 speed = 40000;
1724 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
1725 speed = 100000;
1726
1727
1728
1729
1730
1731
1732
1733 for_each_port(adapter, pidx) {
1734 struct port_info *pi = adap2pinfo(adapter, pidx);
1735 struct link_config *lc;
1736
1737 if (pi->port_id != port_id)
1738 continue;
1739
1740 lc = &pi->link_cfg;
1741
1742 mod = FW_PORT_CMD_MODTYPE_G(stat);
1743 if (mod != pi->mod_type) {
1744 pi->mod_type = mod;
1745 t4vf_os_portmod_changed(adapter, pidx);
1746 }
1747
1748 if (link_ok != lc->link_ok || speed != lc->speed ||
1749 fc != lc->fc) {
1750
1751 lc->link_ok = link_ok;
1752 lc->speed = speed;
1753 lc->fc = fc;
1754 lc->supported =
1755 be16_to_cpu(port_cmd->u.info.pcap);
1756 lc->lp_advertising =
1757 be16_to_cpu(port_cmd->u.info.lpacap);
1758 t4vf_os_link_changed(adapter, pidx, link_ok);
1759 }
1760 }
1761 break;
1762 }
1763
1764 default:
1765 dev_err(adapter->pdev_dev, "Unknown firmware reply %X\n",
1766 opcode);
1767 }
1768 return 0;
1769}
1770
1771
1772
1773int t4vf_prep_adapter(struct adapter *adapter)
1774{
1775 int err;
1776 unsigned int chipid;
1777
1778
1779
1780 err = t4vf_wait_dev_ready(adapter);
1781 if (err)
1782 return err;
1783
1784
1785
1786
1787 adapter->params.nports = 1;
1788 adapter->params.vfres.pmask = 1;
1789 adapter->params.vpd.cclk = 50000;
1790
1791 adapter->params.chip = 0;
1792 switch (CHELSIO_PCI_ID_VER(adapter->pdev->device)) {
1793 case CHELSIO_T4:
1794 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, 0);
1795 adapter->params.arch.sge_fl_db = DBPRIO_F;
1796 adapter->params.arch.mps_tcam_size =
1797 NUM_MPS_CLS_SRAM_L_INSTANCES;
1798 break;
1799
1800 case CHELSIO_T5:
1801 chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A));
1802 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, chipid);
1803 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
1804 adapter->params.arch.mps_tcam_size =
1805 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
1806 break;
1807
1808 case CHELSIO_T6:
1809 chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A));
1810 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, chipid);
1811 adapter->params.arch.sge_fl_db = 0;
1812 adapter->params.arch.mps_tcam_size =
1813 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
1814 break;
1815 }
1816
1817 return 0;
1818}
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831int t4vf_get_vf_mac_acl(struct adapter *adapter, unsigned int pf,
1832 unsigned int *naddr, u8 *addr)
1833{
1834 struct fw_acl_mac_cmd cmd;
1835 int ret;
1836
1837 memset(&cmd, 0, sizeof(cmd));
1838 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
1839 FW_CMD_REQUEST_F |
1840 FW_CMD_READ_F);
1841 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
1842 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &cmd);
1843 if (ret)
1844 return ret;
1845
1846 if (cmd.nmac < *naddr)
1847 *naddr = cmd.nmac;
1848
1849 switch (pf) {
1850 case 3:
1851 memcpy(addr, cmd.macaddr3, sizeof(cmd.macaddr3));
1852 break;
1853 case 2:
1854 memcpy(addr, cmd.macaddr2, sizeof(cmd.macaddr2));
1855 break;
1856 case 1:
1857 memcpy(addr, cmd.macaddr1, sizeof(cmd.macaddr1));
1858 break;
1859 case 0:
1860 memcpy(addr, cmd.macaddr0, sizeof(cmd.macaddr0));
1861 break;
1862 }
1863
1864 return ret;
1865}
1866