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22#ifndef _E1000_DEFINES_H_
23#define _E1000_DEFINES_H_
24
25
26#define REQ_TX_DESCRIPTOR_MULTIPLE 8
27#define REQ_RX_DESCRIPTOR_MULTIPLE 8
28
29
30
31#define E1000_WUC_APME 0x00000001
32#define E1000_WUC_PME_EN 0x00000002
33#define E1000_WUC_PME_STATUS 0x00000004
34#define E1000_WUC_APMPME 0x00000008
35#define E1000_WUC_PHY_WAKE 0x00000100
36
37
38#define E1000_WUFC_LNKC 0x00000001
39#define E1000_WUFC_MAG 0x00000002
40#define E1000_WUFC_EX 0x00000004
41#define E1000_WUFC_MC 0x00000008
42#define E1000_WUFC_BC 0x00000010
43#define E1000_WUFC_ARP 0x00000020
44
45
46#define E1000_WUS_LNKC E1000_WUFC_LNKC
47#define E1000_WUS_MAG E1000_WUFC_MAG
48#define E1000_WUS_EX E1000_WUFC_EX
49#define E1000_WUS_MC E1000_WUFC_MC
50#define E1000_WUS_BC E1000_WUFC_BC
51
52
53#define E1000_CTRL_EXT_LPCD 0x00000004
54#define E1000_CTRL_EXT_SDP3_DATA 0x00000080
55#define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800
56#define E1000_CTRL_EXT_EE_RST 0x00002000
57#define E1000_CTRL_EXT_SPD_BYPS 0x00008000
58#define E1000_CTRL_EXT_RO_DIS 0x00020000
59#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000
60#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
61#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
62#define E1000_CTRL_EXT_EIAME 0x01000000
63#define E1000_CTRL_EXT_DRV_LOAD 0x10000000
64#define E1000_CTRL_EXT_IAME 0x08000000
65#define E1000_CTRL_EXT_PBA_CLR 0x80000000
66#define E1000_CTRL_EXT_LSECCK 0x00001000
67#define E1000_CTRL_EXT_PHYPDEN 0x00100000
68
69
70#define E1000_RXD_STAT_DD 0x01
71#define E1000_RXD_STAT_EOP 0x02
72#define E1000_RXD_STAT_IXSM 0x04
73#define E1000_RXD_STAT_VP 0x08
74#define E1000_RXD_STAT_UDPCS 0x10
75#define E1000_RXD_STAT_TCPCS 0x20
76#define E1000_RXD_ERR_CE 0x01
77#define E1000_RXD_ERR_SE 0x02
78#define E1000_RXD_ERR_SEQ 0x04
79#define E1000_RXD_ERR_CXE 0x10
80#define E1000_RXD_ERR_TCPE 0x20
81#define E1000_RXD_ERR_IPE 0x40
82#define E1000_RXD_ERR_RXE 0x80
83#define E1000_RXD_SPC_VLAN_MASK 0x0FFF
84
85#define E1000_RXDEXT_STATERR_TST 0x00000100
86#define E1000_RXDEXT_STATERR_CE 0x01000000
87#define E1000_RXDEXT_STATERR_SE 0x02000000
88#define E1000_RXDEXT_STATERR_SEQ 0x04000000
89#define E1000_RXDEXT_STATERR_CXE 0x10000000
90#define E1000_RXDEXT_STATERR_RXE 0x80000000
91
92
93#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
94 E1000_RXD_ERR_CE | \
95 E1000_RXD_ERR_SE | \
96 E1000_RXD_ERR_SEQ | \
97 E1000_RXD_ERR_CXE | \
98 E1000_RXD_ERR_RXE)
99
100
101#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
102 E1000_RXDEXT_STATERR_CE | \
103 E1000_RXDEXT_STATERR_SE | \
104 E1000_RXDEXT_STATERR_SEQ | \
105 E1000_RXDEXT_STATERR_CXE | \
106 E1000_RXDEXT_STATERR_RXE)
107
108#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
109#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
110#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
111#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
112#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
113#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
114
115#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
116
117
118#define E1000_MANC_SMBUS_EN 0x00000001
119#define E1000_MANC_ASF_EN 0x00000002
120#define E1000_MANC_ARP_EN 0x00002000
121#define E1000_MANC_RCV_TCO_EN 0x00020000
122#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000
123
124#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
125
126#define E1000_MANC_EN_MNG2HOST 0x00200000
127
128#define E1000_MANC2H_PORT_623 0x00000020
129#define E1000_MANC2H_PORT_664 0x00000040
130#define E1000_MDEF_PORT_623 0x00000800
131#define E1000_MDEF_PORT_664 0x00000400
132
133
134#define E1000_RCTL_EN 0x00000002
135#define E1000_RCTL_SBP 0x00000004
136#define E1000_RCTL_UPE 0x00000008
137#define E1000_RCTL_MPE 0x00000010
138#define E1000_RCTL_LPE 0x00000020
139#define E1000_RCTL_LBM_NO 0x00000000
140#define E1000_RCTL_LBM_MAC 0x00000040
141#define E1000_RCTL_LBM_TCVR 0x000000C0
142#define E1000_RCTL_DTYP_PS 0x00000400
143#define E1000_RCTL_RDMTS_HALF 0x00000000
144#define E1000_RCTL_RDMTS_HEX 0x00010000
145#define E1000_RCTL_MO_SHIFT 12
146#define E1000_RCTL_MO_3 0x00003000
147#define E1000_RCTL_BAM 0x00008000
148
149#define E1000_RCTL_SZ_2048 0x00000000
150#define E1000_RCTL_SZ_1024 0x00010000
151#define E1000_RCTL_SZ_512 0x00020000
152#define E1000_RCTL_SZ_256 0x00030000
153
154#define E1000_RCTL_SZ_16384 0x00010000
155#define E1000_RCTL_SZ_8192 0x00020000
156#define E1000_RCTL_SZ_4096 0x00030000
157#define E1000_RCTL_VFE 0x00040000
158#define E1000_RCTL_CFIEN 0x00080000
159#define E1000_RCTL_CFI 0x00100000
160#define E1000_RCTL_DPF 0x00400000
161#define E1000_RCTL_PMCF 0x00800000
162#define E1000_RCTL_BSEX 0x02000000
163#define E1000_RCTL_SECRC 0x04000000
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180
181#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
182#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
183#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
184#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
185
186#define E1000_PSRCTL_BSIZE0_SHIFT 7
187#define E1000_PSRCTL_BSIZE1_SHIFT 2
188#define E1000_PSRCTL_BSIZE2_SHIFT 6
189#define E1000_PSRCTL_BSIZE3_SHIFT 14
190
191
192#define E1000_SWFW_EEP_SM 0x1
193#define E1000_SWFW_PHY0_SM 0x2
194#define E1000_SWFW_PHY1_SM 0x4
195#define E1000_SWFW_CSR_SM 0x8
196
197
198#define E1000_CTRL_FD 0x00000001
199#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004
200#define E1000_CTRL_LRST 0x00000008
201#define E1000_CTRL_ASDE 0x00000020
202#define E1000_CTRL_SLU 0x00000040
203#define E1000_CTRL_ILOS 0x00000080
204#define E1000_CTRL_SPD_SEL 0x00000300
205#define E1000_CTRL_SPD_10 0x00000000
206#define E1000_CTRL_SPD_100 0x00000100
207#define E1000_CTRL_SPD_1000 0x00000200
208#define E1000_CTRL_FRCSPD 0x00000800
209#define E1000_CTRL_FRCDPX 0x00001000
210#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000
211#define E1000_CTRL_LANPHYPC_VALUE 0x00020000
212#define E1000_CTRL_MEHE 0x00080000
213#define E1000_CTRL_SWDPIN0 0x00040000
214#define E1000_CTRL_SWDPIN1 0x00080000
215#define E1000_CTRL_ADVD3WUC 0x00100000
216#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
217#define E1000_CTRL_SWDPIO0 0x00400000
218#define E1000_CTRL_RST 0x04000000
219#define E1000_CTRL_RFCE 0x08000000
220#define E1000_CTRL_TFCE 0x10000000
221#define E1000_CTRL_VME 0x40000000
222#define E1000_CTRL_PHY_RST 0x80000000
223
224#define E1000_PCS_LCTL_FORCE_FCTRL 0x80
225
226#define E1000_PCS_LSTS_AN_COMPLETE 0x10000
227
228
229#define E1000_STATUS_FD 0x00000001
230#define E1000_STATUS_LU 0x00000002
231#define E1000_STATUS_FUNC_MASK 0x0000000C
232#define E1000_STATUS_FUNC_SHIFT 2
233#define E1000_STATUS_FUNC_1 0x00000004
234#define E1000_STATUS_TXOFF 0x00000010
235#define E1000_STATUS_SPEED_MASK 0x000000C0
236#define E1000_STATUS_SPEED_10 0x00000000
237#define E1000_STATUS_SPEED_100 0x00000040
238#define E1000_STATUS_SPEED_1000 0x00000080
239#define E1000_STATUS_LAN_INIT_DONE 0x00000200
240#define E1000_STATUS_PHYRA 0x00000400
241#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
242
243#define HALF_DUPLEX 1
244#define FULL_DUPLEX 2
245
246#define ADVERTISE_10_HALF 0x0001
247#define ADVERTISE_10_FULL 0x0002
248#define ADVERTISE_100_HALF 0x0004
249#define ADVERTISE_100_FULL 0x0008
250#define ADVERTISE_1000_HALF 0x0010
251#define ADVERTISE_1000_FULL 0x0020
252
253
254#define E1000_ALL_SPEED_DUPLEX ( \
255 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
256 ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
257#define E1000_ALL_NOT_GIG ( \
258 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
259 ADVERTISE_100_FULL)
260#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
261#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
262#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
263
264#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
265
266
267#define E1000_PHY_LED0_MODE_MASK 0x00000007
268#define E1000_PHY_LED0_IVRT 0x00000008
269#define E1000_PHY_LED0_MASK 0x0000001F
270
271#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
272#define E1000_LEDCTL_LED0_MODE_SHIFT 0
273#define E1000_LEDCTL_LED0_IVRT 0x00000040
274#define E1000_LEDCTL_LED0_BLINK 0x00000080
275
276#define E1000_LEDCTL_MODE_LINK_UP 0x2
277#define E1000_LEDCTL_MODE_LED_ON 0xE
278#define E1000_LEDCTL_MODE_LED_OFF 0xF
279
280
281#define E1000_TXD_DTYP_D 0x00100000
282#define E1000_TXD_POPTS_IXSM 0x01
283#define E1000_TXD_POPTS_TXSM 0x02
284#define E1000_TXD_CMD_EOP 0x01000000
285#define E1000_TXD_CMD_IFCS 0x02000000
286#define E1000_TXD_CMD_IC 0x04000000
287#define E1000_TXD_CMD_RS 0x08000000
288#define E1000_TXD_CMD_RPS 0x10000000
289#define E1000_TXD_CMD_DEXT 0x20000000
290#define E1000_TXD_CMD_VLE 0x40000000
291#define E1000_TXD_CMD_IDE 0x80000000
292#define E1000_TXD_STAT_DD 0x00000001
293#define E1000_TXD_STAT_EC 0x00000002
294#define E1000_TXD_STAT_LC 0x00000004
295#define E1000_TXD_STAT_TU 0x00000008
296#define E1000_TXD_CMD_TCP 0x01000000
297#define E1000_TXD_CMD_IP 0x02000000
298#define E1000_TXD_CMD_TSE 0x04000000
299#define E1000_TXD_STAT_TC 0x00000004
300#define E1000_TXD_EXTCMD_TSTAMP 0x00000010
301
302
303#define E1000_TCTL_EN 0x00000002
304#define E1000_TCTL_PSP 0x00000008
305#define E1000_TCTL_CT 0x00000ff0
306#define E1000_TCTL_COLD 0x003ff000
307#define E1000_TCTL_RTLC 0x01000000
308#define E1000_TCTL_MULR 0x10000000
309
310
311#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
312#define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410
313
314
315#define E1000_RXCSUM_TUOFL 0x00000200
316#define E1000_RXCSUM_IPPCSE 0x00001000
317#define E1000_RXCSUM_PCSD 0x00002000
318
319
320#define E1000_RFCTL_NFSW_DIS 0x00000040
321#define E1000_RFCTL_NFSR_DIS 0x00000080
322#define E1000_RFCTL_ACK_DIS 0x00001000
323#define E1000_RFCTL_EXTEN 0x00008000
324#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
325#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
326
327
328#define E1000_COLLISION_THRESHOLD 15
329#define E1000_CT_SHIFT 4
330#define E1000_COLLISION_DISTANCE 63
331#define E1000_COLD_SHIFT 12
332
333
334#define DEFAULT_82543_TIPG_IPGT_COPPER 8
335
336#define E1000_TIPG_IPGT_MASK 0x000003FF
337
338#define DEFAULT_82543_TIPG_IPGR1 8
339#define E1000_TIPG_IPGR1_SHIFT 10
340
341#define DEFAULT_82543_TIPG_IPGR2 6
342#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
343#define E1000_TIPG_IPGR2_SHIFT 20
344
345#define MAX_JUMBO_FRAME_SIZE 0x3F00
346#define E1000_TX_PTR_GAP 0x1F
347
348
349#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
350#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
351#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
352#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
353#define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
354#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
355#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
356#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
357#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
358
359#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
360#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
361#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
362#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
363
364#define E1000_KABGTXD_BGSQLBIAS 0x00050000
365
366
367#define E1000_LPIC_LPIET_SHIFT 24
368
369
370#define E1000_PBA_8K 0x0008
371#define E1000_PBA_16K 0x0010
372
373#define E1000_PBA_RXA_MASK 0xFFFF
374
375#define E1000_PBS_16K E1000_PBA_16K
376
377
378#define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF
379#define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00
380#define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8
381#define E1000_PBECCSTS_ECC_ENABLE 0x00010000
382
383#define IFS_MAX 80
384#define IFS_MIN 40
385#define IFS_RATIO 4
386#define IFS_STEP 10
387#define MIN_NUM_XMITS 1000
388
389
390#define E1000_SWSM_SMBI 0x00000001
391#define E1000_SWSM_SWESMBI 0x00000002
392#define E1000_SWSM_DRV_LOAD 0x00000008
393
394#define E1000_SWSM2_LOCK 0x00000002
395
396
397#define E1000_ICR_TXDW 0x00000001
398#define E1000_ICR_LSC 0x00000004
399#define E1000_ICR_RXSEQ 0x00000008
400#define E1000_ICR_RXDMT0 0x00000010
401#define E1000_ICR_RXT0 0x00000080
402#define E1000_ICR_ECCER 0x00400000
403
404#define E1000_ICR_INT_ASSERTED 0x80000000
405#define E1000_ICR_RXQ0 0x00100000
406#define E1000_ICR_RXQ1 0x00200000
407#define E1000_ICR_TXQ0 0x00400000
408#define E1000_ICR_TXQ1 0x00800000
409#define E1000_ICR_OTHER 0x01000000
410
411
412#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000
413#define E1000_PBA_ECC_COUNTER_SHIFT 20
414#define E1000_PBA_ECC_CORR_EN 0x00000001
415#define E1000_PBA_ECC_STAT_CLR 0x00000002
416#define E1000_PBA_ECC_INT_EN 0x00000004
417
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425
426#define IMS_ENABLE_MASK ( \
427 E1000_IMS_RXT0 | \
428 E1000_IMS_TXDW | \
429 E1000_IMS_RXDMT0 | \
430 E1000_IMS_RXSEQ | \
431 E1000_IMS_LSC)
432
433
434#define E1000_IMS_TXDW E1000_ICR_TXDW
435#define E1000_IMS_LSC E1000_ICR_LSC
436#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ
437#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0
438#define E1000_IMS_RXT0 E1000_ICR_RXT0
439#define E1000_IMS_ECCER E1000_ICR_ECCER
440#define E1000_IMS_RXQ0 E1000_ICR_RXQ0
441#define E1000_IMS_RXQ1 E1000_ICR_RXQ1
442#define E1000_IMS_TXQ0 E1000_ICR_TXQ0
443#define E1000_IMS_TXQ1 E1000_ICR_TXQ1
444#define E1000_IMS_OTHER E1000_ICR_OTHER
445
446
447#define E1000_ICS_LSC E1000_ICR_LSC
448#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ
449#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0
450#define E1000_ICS_OTHER E1000_ICR_OTHER
451
452
453#define E1000_TXDCTL_PTHRESH 0x0000003F
454#define E1000_TXDCTL_HTHRESH 0x00003F00
455#define E1000_TXDCTL_WTHRESH 0x003F0000
456#define E1000_TXDCTL_GRAN 0x01000000
457#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000
458#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F
459
460#define E1000_TXDCTL_COUNT_DESC 0x00400000
461
462
463#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
464#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
465#define FLOW_CONTROL_TYPE 0x8808
466
467
468#define E1000_VLAN_FILTER_TBL_SIZE 128
469
470
471
472
473
474
475
476
477#define E1000_RAR_ENTRIES 15
478#define E1000_RAH_AV 0x80000000
479#define E1000_RAL_MAC_ADDR_LEN 4
480#define E1000_RAH_MAC_ADDR_LEN 2
481
482
483#define E1000_ERR_NVM 1
484#define E1000_ERR_PHY 2
485#define E1000_ERR_CONFIG 3
486#define E1000_ERR_PARAM 4
487#define E1000_ERR_MAC_INIT 5
488#define E1000_ERR_PHY_TYPE 6
489#define E1000_ERR_RESET 9
490#define E1000_ERR_MASTER_REQUESTS_PENDING 10
491#define E1000_ERR_HOST_INTERFACE_COMMAND 11
492#define E1000_BLK_PHY_RESET 12
493#define E1000_ERR_SWFW_SYNC 13
494#define E1000_NOT_IMPLEMENTED 14
495#define E1000_ERR_INVALID_ARGUMENT 16
496#define E1000_ERR_NO_SPACE 17
497#define E1000_ERR_NVM_PBA_SECTION 18
498
499
500#define FIBER_LINK_UP_LIMIT 50
501#define COPPER_LINK_UP_LIMIT 10
502#define PHY_AUTO_NEG_LIMIT 45
503#define PHY_FORCE_LIMIT 20
504
505#define MASTER_DISABLE_TIMEOUT 800
506
507#define PHY_CFG_TIMEOUT 100
508
509#define MDIO_OWNERSHIP_TIMEOUT 10
510
511#define AUTO_READ_DONE_TIMEOUT 10
512
513
514#define E1000_FCRTH_RTH 0x0000FFF8
515#define E1000_FCRTL_RTL 0x0000FFF8
516#define E1000_FCRTL_XONE 0x80000000
517
518
519#define E1000_TXCW_FD 0x00000020
520#define E1000_TXCW_PAUSE 0x00000080
521#define E1000_TXCW_ASM_DIR 0x00000100
522#define E1000_TXCW_PAUSE_MASK 0x00000180
523#define E1000_TXCW_ANE 0x80000000
524
525
526#define E1000_RXCW_CW 0x0000ffff
527#define E1000_RXCW_IV 0x08000000
528#define E1000_RXCW_C 0x20000000
529#define E1000_RXCW_SYNCH 0x40000000
530
531
532#define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000
533#define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000
534#define E1000_TSYNCTXCTL_START_SYNC 0x80000000
535
536#define E1000_TSYNCTXCTL_VALID 0x00000001
537#define E1000_TSYNCTXCTL_ENABLED 0x00000010
538
539#define E1000_TSYNCRXCTL_VALID 0x00000001
540#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E
541#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
542#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
543#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
544#define E1000_TSYNCRXCTL_TYPE_ALL 0x08
545#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
546#define E1000_TSYNCRXCTL_ENABLED 0x00000010
547#define E1000_TSYNCRXCTL_SYSCFI 0x00000020
548
549#define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000
550#define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000
551
552#define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000
553#define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000
554
555#define E1000_TIMINCA_INCPERIOD_SHIFT 24
556#define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF
557
558
559#define E1000_GCR_RXD_NO_SNOOP 0x00000001
560#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
561#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
562#define E1000_GCR_TXD_NO_SNOOP 0x00000008
563#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
564#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
565
566#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
567 E1000_GCR_RXDSCW_NO_SNOOP | \
568 E1000_GCR_RXDSCR_NO_SNOOP | \
569 E1000_GCR_TXD_NO_SNOOP | \
570 E1000_GCR_TXDSCW_NO_SNOOP | \
571 E1000_GCR_TXDSCR_NO_SNOOP)
572
573
574#define E1000_EECD_SK 0x00000001
575#define E1000_EECD_CS 0x00000002
576#define E1000_EECD_DI 0x00000004
577#define E1000_EECD_DO 0x00000008
578#define E1000_EECD_REQ 0x00000040
579#define E1000_EECD_GNT 0x00000080
580#define E1000_EECD_PRES 0x00000100
581#define E1000_EECD_SIZE 0x00000200
582
583#define E1000_EECD_ADDR_BITS 0x00000400
584#define E1000_NVM_GRANT_ATTEMPTS 1000
585#define E1000_EECD_AUTO_RD 0x00000200
586#define E1000_EECD_SIZE_EX_MASK 0x00007800
587#define E1000_EECD_SIZE_EX_SHIFT 11
588#define E1000_EECD_FLUPD 0x00080000
589#define E1000_EECD_AUPDEN 0x00100000
590#define E1000_EECD_SEC1VAL 0x00400000
591#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
592
593#define E1000_NVM_RW_REG_DATA 16
594#define E1000_NVM_RW_REG_DONE 2
595#define E1000_NVM_RW_REG_START 1
596#define E1000_NVM_RW_ADDR_SHIFT 2
597#define E1000_NVM_POLL_WRITE 1
598#define E1000_NVM_POLL_READ 0
599#define E1000_FLASH_UPDATES 2000
600
601
602#define NVM_COMPAT 0x0003
603#define NVM_ID_LED_SETTINGS 0x0004
604#define NVM_FUTURE_INIT_WORD1 0x0019
605#define NVM_COMPAT_VALID_CSUM 0x0001
606#define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040
607
608#define NVM_INIT_CONTROL2_REG 0x000F
609#define NVM_INIT_CONTROL3_PORT_B 0x0014
610#define NVM_INIT_3GIO_3 0x001A
611#define NVM_INIT_CONTROL3_PORT_A 0x0024
612#define NVM_CFG 0x0012
613#define NVM_ALT_MAC_ADDR_PTR 0x0037
614#define NVM_CHECKSUM_REG 0x003F
615
616#define E1000_NVM_CFG_DONE_PORT_0 0x40000
617#define E1000_NVM_CFG_DONE_PORT_1 0x80000
618
619
620#define NVM_WORD0F_PAUSE_MASK 0x3000
621#define NVM_WORD0F_PAUSE 0x1000
622#define NVM_WORD0F_ASM_DIR 0x2000
623
624
625#define NVM_WORD1A_ASPM_MASK 0x000C
626
627
628#define NVM_COMPAT_LOM 0x0800
629
630
631#define E1000_PBANUM_LENGTH 11
632
633
634#define NVM_SUM 0xBABA
635
636
637#define NVM_PBA_OFFSET_0 8
638#define NVM_PBA_OFFSET_1 9
639#define NVM_PBA_PTR_GUARD 0xFAFA
640#define NVM_WORD_SIZE_BASE_SHIFT 6
641
642
643#define NVM_MAX_RETRY_SPI 5000
644#define NVM_READ_OPCODE_SPI 0x03
645#define NVM_WRITE_OPCODE_SPI 0x02
646#define NVM_A8_OPCODE_SPI 0x08
647#define NVM_WREN_OPCODE_SPI 0x06
648#define NVM_RDSR_OPCODE_SPI 0x05
649
650
651#define NVM_STATUS_RDY_SPI 0x01
652
653
654#define ID_LED_RESERVED_0000 0x0000
655#define ID_LED_RESERVED_FFFF 0xFFFF
656#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
657 (ID_LED_OFF1_OFF2 << 8) | \
658 (ID_LED_DEF1_DEF2 << 4) | \
659 (ID_LED_DEF1_DEF2))
660#define ID_LED_DEF1_DEF2 0x1
661#define ID_LED_DEF1_ON2 0x2
662#define ID_LED_DEF1_OFF2 0x3
663#define ID_LED_ON1_DEF2 0x4
664#define ID_LED_ON1_ON2 0x5
665#define ID_LED_ON1_OFF2 0x6
666#define ID_LED_OFF1_DEF2 0x7
667#define ID_LED_OFF1_ON2 0x8
668#define ID_LED_OFF1_OFF2 0x9
669
670#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
671#define IGP_ACTIVITY_LED_ENABLE 0x0300
672#define IGP_LED3_MODE 0x07000000
673
674
675#define PCI_HEADER_TYPE_REGISTER 0x0E
676#define PCIE_LINK_STATUS 0x12
677
678#define PCI_HEADER_TYPE_MULTIFUNC 0x80
679#define PCIE_LINK_WIDTH_MASK 0x3F0
680#define PCIE_LINK_WIDTH_SHIFT 4
681
682#define PHY_REVISION_MASK 0xFFFFFFF0
683#define MAX_PHY_REG_ADDRESS 0x1F
684#define MAX_PHY_MULTI_PAGE_REG 0xF
685
686
687
688
689
690#define M88E1000_E_PHY_ID 0x01410C50
691#define M88E1000_I_PHY_ID 0x01410C30
692#define M88E1011_I_PHY_ID 0x01410C20
693#define IGP01E1000_I_PHY_ID 0x02A80380
694#define M88E1111_I_PHY_ID 0x01410CC0
695#define GG82563_E_PHY_ID 0x01410CA0
696#define IGP03E1000_E_PHY_ID 0x02A80390
697#define IFE_E_PHY_ID 0x02A80330
698#define IFE_PLUS_E_PHY_ID 0x02A80320
699#define IFE_C_E_PHY_ID 0x02A80310
700#define BME1000_E_PHY_ID 0x01410CB0
701#define BME1000_E_PHY_ID_R2 0x01410CB1
702#define I82577_E_PHY_ID 0x01540050
703#define I82578_E_PHY_ID 0x004DD040
704#define I82579_E_PHY_ID 0x01540090
705#define I217_E_PHY_ID 0x015400A0
706
707
708#define M88E1000_PHY_SPEC_CTRL 0x10
709#define M88E1000_PHY_SPEC_STATUS 0x11
710#define M88E1000_EXT_PHY_SPEC_CTRL 0x14
711
712#define M88E1000_PHY_PAGE_SELECT 0x1D
713#define M88E1000_PHY_GEN_CONTROL 0x1E
714
715
716#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002
717#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
718
719#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020
720
721#define M88E1000_PSCR_AUTO_X_1000T 0x0040
722
723#define M88E1000_PSCR_AUTO_X_MODE 0x0060
724#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800
725
726
727#define M88E1000_PSSR_REV_POLARITY 0x0002
728#define M88E1000_PSSR_DOWNSHIFT 0x0020
729#define M88E1000_PSSR_MDIX 0x0040
730
731#define M88E1000_PSSR_CABLE_LENGTH 0x0380
732#define M88E1000_PSSR_SPEED 0xC000
733#define M88E1000_PSSR_1000MBS 0x8000
734
735#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
736
737
738
739
740#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
741#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
742
743
744
745#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
746#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
747#define M88E1000_EPSCR_TX_CLK_25 0x0070
748
749
750#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
751#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
752
753#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
754#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
755
756
757#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800
758
759
760
761
762
763#define GG82563_PAGE_SHIFT 5
764#define GG82563_REG(page, reg) \
765 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
766#define GG82563_MIN_ALT_REG 30
767
768
769#define GG82563_PHY_SPEC_CTRL \
770 GG82563_REG(0, 16)
771#define GG82563_PHY_PAGE_SELECT \
772 GG82563_REG(0, 22)
773#define GG82563_PHY_SPEC_CTRL_2 \
774 GG82563_REG(0, 26)
775#define GG82563_PHY_PAGE_SELECT_ALT \
776 GG82563_REG(0, 29)
777
778#define GG82563_PHY_MAC_SPEC_CTRL \
779 GG82563_REG(2, 21)
780
781#define GG82563_PHY_DSP_DISTANCE \
782 GG82563_REG(5, 26)
783
784
785#define GG82563_PHY_KMRN_MODE_CTRL \
786 GG82563_REG(193, 16)
787#define GG82563_PHY_PWR_MGMT_CTRL \
788 GG82563_REG(193, 20)
789
790
791#define GG82563_PHY_INBAND_CTRL \
792 GG82563_REG(194, 18)
793
794
795#define E1000_MDIC_REG_MASK 0x001F0000
796#define E1000_MDIC_REG_SHIFT 16
797#define E1000_MDIC_PHY_SHIFT 21
798#define E1000_MDIC_OP_WRITE 0x04000000
799#define E1000_MDIC_OP_READ 0x08000000
800#define E1000_MDIC_READY 0x10000000
801#define E1000_MDIC_ERROR 0x40000000
802
803
804#define E1000_GEN_POLL_TIMEOUT 640
805
806#endif
807