LXR linux/drivers/net/ethernet/qlogic/qed/qed

   1/* QLogic qed NIC Driver
   2 * Copyright (c) 2015 QLogic Corporation
   3 *
   4 * This software is available under the terms of the GNU General Public License
   5 * (GPL) Version 2, available from the file COPYING in the main directory of
   6 * this source tree.
   7 */
   8
   9#ifndef _QED_INT_H
  10#define _QED_INT_H
  11
  12#include <linux/types.h>
  13#include <linux/slab.h>
  14#include "qed.h"
  15
  16/* Fields of IGU PF CONFIGRATION REGISTER */
  17#define IGU_PF_CONF_FUNC_EN       (0x1 << 0)    /* function enable        */
  18#define IGU_PF_CONF_MSI_MSIX_EN   (0x1 << 1)    /* MSI/MSIX enable        */
  19#define IGU_PF_CONF_INT_LINE_EN   (0x1 << 2)    /* INT enable             */
  20#define IGU_PF_CONF_ATTN_BIT_EN   (0x1 << 3)    /* attention enable       */
  21#define IGU_PF_CONF_SINGLE_ISR_EN (0x1 << 4)    /* single ISR mode enable */
  22#define IGU_PF_CONF_SIMD_MODE     (0x1 << 5)    /* simd all ones mode     */
  23/* Fields of IGU VF CONFIGRATION REGISTER */
  24#define IGU_VF_CONF_FUNC_EN        (0x1 << 0)   /* function enable        */
  25#define IGU_VF_CONF_MSI_MSIX_EN    (0x1 << 1)   /* MSI/MSIX enable        */
  26#define IGU_VF_CONF_SINGLE_ISR_EN  (0x1 << 4)   /* single ISR mode enable */
  27#define IGU_VF_CONF_PARENT_MASK    (0xF)        /* Parent PF              */
  28#define IGU_VF_CONF_PARENT_SHIFT   5            /* Parent PF              */
  29
  30/* Igu control commands
  31 */
  32enum igu_ctrl_cmd {
  33        IGU_CTRL_CMD_TYPE_RD,
  34        IGU_CTRL_CMD_TYPE_WR,
  35        MAX_IGU_CTRL_CMD
  36};
  37
  38/* Control register for the IGU command register
  39 */
  40struct igu_ctrl_reg {
  41        u32 ctrl_data;
  42#define IGU_CTRL_REG_FID_MASK           0xFFFF  /* Opaque_FID    */
  43#define IGU_CTRL_REG_FID_SHIFT          0
  44#define IGU_CTRL_REG_PXP_ADDR_MASK      0xFFF   /* Command address */
  45#define IGU_CTRL_REG_PXP_ADDR_SHIFT     16
  46#define IGU_CTRL_REG_RESERVED_MASK      0x1
  47#define IGU_CTRL_REG_RESERVED_SHIFT     28
  48#define IGU_CTRL_REG_TYPE_MASK          0x1 /* use enum igu_ctrl_cmd */
  49#define IGU_CTRL_REG_TYPE_SHIFT         31
  50};
  51
  52enum qed_coalescing_fsm {
  53        QED_COAL_RX_STATE_MACHINE,
  54        QED_COAL_TX_STATE_MACHINE
  55};
  56
  57/**
  58 * @brief qed_int_cau_conf_pi - configure cau for a given
  59 *        status block
  60 *
  61 * @param p_hwfn
  62 * @param p_ptt
  63 * @param igu_sb_id
  64 * @param pi_index
  65 * @param state
  66 * @param timeset
  67 */
  68void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
  69                         struct qed_ptt *p_ptt,
  70                         u16 igu_sb_id,
  71                         u32 pi_index,
  72                         enum qed_coalescing_fsm coalescing_fsm,
  73                         u8 timeset);
  74
  75/**
  76 * @brief qed_int_igu_enable_int - enable device interrupts
  77 *
  78 * @param p_hwfn
  79 * @param p_ptt
  80 * @param int_mode - interrupt mode to use
  81 */
  82void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
  83                            struct qed_ptt *p_ptt,
  84                            enum qed_int_mode int_mode);
  85
  86/**
  87 * @brief qed_int_igu_disable_int - disable device interrupts
  88 *
  89 * @param p_hwfn
  90 * @param p_ptt
  91 */
  92void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
  93                             struct qed_ptt *p_ptt);
  94
  95/**
  96 * @brief qed_int_igu_read_sisr_reg - Reads the single isr multiple dpc
  97 *        register from igu.
  98 *
  99 * @param p_hwfn
 100 *
 101 * @return u64
 102 */
 103u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn);
 104
 105#define QED_SP_SB_ID 0xffff
 106/**
 107 * @brief qed_int_sb_init - Initializes the sb_info structure.
 108 *
 109 * once the structure is initialized it can be passed to sb related functions.
 110 *
 111 * @param p_hwfn
 112 * @param p_ptt
 113 * @param sb_info       points to an uninitialized (but
 114 *                      allocated) sb_info structure
 115 * @param sb_virt_addr
 116 * @param sb_phy_addr
 117 * @param sb_id the sb_id to be used (zero based in driver)
 118 *                      should use QED_SP_SB_ID for SP Status block
 119 *
 120 * @return int
 121 */
 122int qed_int_sb_init(struct qed_hwfn *p_hwfn,
 123                    struct qed_ptt *p_ptt,
 124                    struct qed_sb_info *sb_info,
 125                    void *sb_virt_addr,
 126                    dma_addr_t sb_phy_addr,
 127                    u16 sb_id);
 128/**
 129 * @brief qed_int_sb_setup - Setup the sb.
 130 *
 131 * @param p_hwfn
 132 * @param p_ptt
 133 * @param sb_info       initialized sb_info structure
 134 */
 135void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
 136                      struct qed_ptt *p_ptt,
 137                      struct qed_sb_info *sb_info);
 138
 139/**
 140 * @brief qed_int_sb_release - releases the sb_info structure.
 141 *
 142 * once the structure is released, it's memory can be freed
 143 *
 144 * @param p_hwfn
 145 * @param sb_info       points to an allocated sb_info structure
 146 * @param sb_id         the sb_id to be used (zero based in driver)
 147 *                      should never be equal to QED_SP_SB_ID
 148 *                      (SP Status block)
 149 *
 150 * @return int
 151 */
 152int qed_int_sb_release(struct qed_hwfn *p_hwfn,
 153                       struct qed_sb_info *sb_info,
 154                       u16 sb_id);
 155
 156/**
 157 * @brief qed_int_sp_dpc - To be called when an interrupt is received on the
 158 *        default status block.
 159 *
 160 * @param p_hwfn - pointer to hwfn
 161 *
 162 */
 163void qed_int_sp_dpc(unsigned long hwfn_cookie);
 164
 165/**
 166 * @brief qed_int_get_num_sbs - get the number of status
 167 *        blocks configured for this funciton in the igu.
 168 *
 169 * @param p_hwfn
 170 * @param p_sb_cnt_info
 171 *
 172 * @return int - number of status blocks configured
 173 */
 174void qed_int_get_num_sbs(struct qed_hwfn        *p_hwfn,
 175                         struct qed_sb_cnt_info *p_sb_cnt_info);
 176
 177/**
 178 * @brief qed_int_disable_post_isr_release - performs the cleanup post ISR
 179 *        release. The API need to be called after releasing all slowpath IRQs
 180 *        of the device.
 181 *
 182 * @param cdev
 183 *
 184 */
 185void qed_int_disable_post_isr_release(struct qed_dev *cdev);
 186
 187#define QED_CAU_DEF_RX_TIMER_RES 0
 188#define QED_CAU_DEF_TX_TIMER_RES 0
 189
 190#define QED_SB_ATT_IDX  0x0001
 191#define QED_SB_EVENT_MASK       0x0003
 192
 193#define SB_ALIGNED_SIZE(p_hwfn) \
 194        ALIGNED_TYPE_SIZE(struct status_block, p_hwfn)
 195
 196struct qed_igu_block {
 197        u8      status;
 198#define QED_IGU_STATUS_FREE     0x01
 199#define QED_IGU_STATUS_VALID    0x02
 200#define QED_IGU_STATUS_PF       0x04
 201
 202        u8      vector_number;
 203        u8      function_id;
 204        u8      is_pf;
 205};
 206
 207struct qed_igu_map {
 208        struct qed_igu_block igu_blocks[MAX_TOT_SB_PER_PATH];
 209};
 210
 211struct qed_igu_info {
 212        struct qed_igu_map      igu_map;
 213        u16                     igu_dsb_id;
 214        u16                     igu_base_sb;
 215        u16                     igu_base_sb_iov;
 216        u16                     igu_sb_cnt;
 217        u16                     igu_sb_cnt_iov;
 218        u16                     free_blks;
 219};
 220
 221/* TODO Names of function may change... */
 222void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
 223                              struct qed_ptt *p_ptt,
 224                              bool b_set,
 225                              bool b_slowpath);
 226
 227void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn);
 228
 229/**
 230 * @brief qed_int_igu_read_cam - Reads the IGU CAM.
 231 *      This function needs to be called during hardware
 232 *      prepare. It reads the info from igu cam to know which
 233 *      status block is the default / base status block etc.
 234 *
 235 * @param p_hwfn
 236 * @param p_ptt
 237 *
 238 * @return int
 239 */
 240int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
 241                         struct qed_ptt *p_ptt);
 242
 243typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn,
 244                                 void *cookie);
 245/**
 246 * @brief qed_int_register_cb - Register callback func for
 247 *      slowhwfn statusblock.
 248 *
 249 *      Every protocol that uses the slowhwfn status block
 250 *      should register a callback function that will be called
 251 *      once there is an update of the sp status block.
 252 *
 253 * @param p_hwfn
 254 * @param comp_cb - function to be called when there is an
 255 *                  interrupt on the sp sb
 256 *
 257 * @param cookie  - passed to the callback function
 258 * @param sb_idx  - OUT parameter which gives the chosen index
 259 *                  for this protocol.
 260 * @param p_fw_cons  - pointer to the actual address of the
 261 *                     consumer for this protocol.
 262 *
 263 * @return int
 264 */
 265int qed_int_register_cb(struct qed_hwfn *p_hwfn,
 266                        qed_int_comp_cb_t comp_cb,
 267                        void *cookie,
 268                        u8 *sb_idx,
 269                        __le16 **p_fw_cons);
 270
 271/**
 272 * @brief qed_int_unregister_cb - Unregisters callback
 273 *      function from sp sb.
 274 *      Partner of qed_int_register_cb -> should be called
 275 *      when no longer required.
 276 *
 277 * @param p_hwfn
 278 * @param pi
 279 *
 280 * @return int
 281 */
 282int qed_int_unregister_cb(struct qed_hwfn *p_hwfn,
 283                          u8 pi);
 284
 285/**
 286 * @brief qed_int_get_sp_sb_id - Get the slowhwfn sb id.
 287 *
 288 * @param p_hwfn
 289 *
 290 * @return u16
 291 */
 292u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn);
 293
 294/**
 295 * @brief Status block cleanup. Should be called for each status
 296 *        block that will be used -> both PF / VF
 297 *
 298 * @param p_hwfn
 299 * @param p_ptt
 300 * @param sb_id         - igu status block id
 301 * @param opaque        - opaque fid of the sb owner.
 302 * @param b_set         - set(1) / clear(0)
 303 */
 304void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
 305                                     struct qed_ptt *p_ptt,
 306                                     u32 sb_id,
 307                                     u16 opaque,
 308                                     bool b_set);
 309
 310/**
 311 * @brief qed_int_cau_conf - configure cau for a given status
 312 *        block
 313 *
 314 * @param p_hwfn
 315 * @param ptt
 316 * @param sb_phys
 317 * @param igu_sb_id
 318 * @param vf_number
 319 * @param vf_valid
 320 */
 321void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
 322                         struct qed_ptt *p_ptt,
 323                         dma_addr_t sb_phys,
 324                         u16 igu_sb_id,
 325                         u16 vf_number,
 326                         u8 vf_valid);
 327
 328/**
 329 * @brief qed_int_alloc
 330 *
 331 * @param p_hwfn
 332 * @param p_ptt
 333 *
 334 * @return int
 335 */
 336int qed_int_alloc(struct qed_hwfn *p_hwfn,
 337                  struct qed_ptt *p_ptt);
 338
 339/**
 340 * @brief qed_int_free
 341 *
 342 * @param p_hwfn
 343 */
 344void qed_int_free(struct qed_hwfn *p_hwfn);
 345
 346/**
 347 * @brief qed_int_setup
 348 *
 349 * @param p_hwfn
 350 * @param p_ptt
 351 */
 352void qed_int_setup(struct qed_hwfn *p_hwfn,
 353                   struct qed_ptt *p_ptt);
 354
 355/**
 356 * @brief - Returns an Rx queue index appropriate for usage with given SB.
 357 *
 358 * @param p_hwfn
 359 * @param sb_id - absolute index of SB
 360 *
 361 * @return index of Rx queue
 362 */
 363u16 qed_int_queue_id_from_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id);
 364
 365/**
 366 * @brief - Enable Interrupt & Attention for hw function
 367 *
 368 * @param p_hwfn
 369 * @param p_ptt
 370 * @param int_mode
 371 *
 372 * @return int
 373 */
 374int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
 375                       enum qed_int_mode int_mode);
 376
 377/**
 378 * @brief - Initialize CAU status block entry
 379 *
 380 * @param p_hwfn
 381 * @param p_sb_entry
 382 * @param pf_id
 383 * @param vf_number
 384 * @param vf_valid
 385 */
 386void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
 387                           struct cau_sb_entry *p_sb_entry,
 388                           u8 pf_id,
 389                           u16 vf_number,
 390                           u8 vf_valid);
 391
 392int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
 393                          u8 timer_res, u16 sb_id, bool tx);
 394
 395#define QED_MAPPING_MEMORY_SIZE(dev)    (NUM_OF_SBS(dev))
 396
 397#endif
 398