1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#include "../wifi.h"
27#include "../pci.h"
28#include "../ps.h"
29#include "reg.h"
30#include "def.h"
31#include "phy.h"
32#include "rf.h"
33#include "dm.h"
34#include "table.h"
35#include "../rtl8723com/phy_common.h"
36
37static void _rtl8723e_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
38 enum radio_path rfpath, u32 offset,
39 u32 data);
40static bool _rtl8723e_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
41static bool _rtl8723e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
42static bool _rtl8723e_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
43 u8 configtype);
44static bool _rtl8723e_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
45 u8 configtype);
46static bool _rtl8723e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
47 u8 channel, u8 *stage, u8 *step,
48 u32 *delay);
49static u8 _rtl8723e_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
50 enum wireless_mode wirelessmode,
51 long power_indbm);
52static void rtl8723e_phy_set_rf_on(struct ieee80211_hw *hw);
53static void rtl8723e_phy_set_io(struct ieee80211_hw *hw);
54
55u32 rtl8723e_phy_query_rf_reg(struct ieee80211_hw *hw,
56 enum radio_path rfpath,
57 u32 regaddr, u32 bitmask)
58{
59 struct rtl_priv *rtlpriv = rtl_priv(hw);
60 u32 original_value = 0, readback_value, bitshift;
61 struct rtl_phy *rtlphy = &rtlpriv->phy;
62 unsigned long flags;
63
64 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
65 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
66 regaddr, rfpath, bitmask);
67
68 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
69
70 if (rtlphy->rf_mode != RF_OP_BY_FW) {
71 original_value = rtl8723_phy_rf_serial_read(hw,
72 rfpath, regaddr);
73 }
74
75 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
76 readback_value = (original_value & bitmask) >> bitshift;
77
78 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
79
80 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
81 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
82 regaddr, rfpath, bitmask, original_value);
83
84 return readback_value;
85}
86
87void rtl8723e_phy_set_rf_reg(struct ieee80211_hw *hw,
88 enum radio_path rfpath,
89 u32 regaddr, u32 bitmask, u32 data)
90{
91 struct rtl_priv *rtlpriv = rtl_priv(hw);
92 struct rtl_phy *rtlphy = &rtlpriv->phy;
93 u32 original_value = 0, bitshift;
94 unsigned long flags;
95
96 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
97 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
98 regaddr, bitmask, data, rfpath);
99
100 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
101
102 if (rtlphy->rf_mode != RF_OP_BY_FW) {
103 if (bitmask != RFREG_OFFSET_MASK) {
104 original_value = rtl8723_phy_rf_serial_read(hw,
105 rfpath,
106 regaddr);
107 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
108 data =
109 ((original_value & (~bitmask)) |
110 (data << bitshift));
111 }
112
113 rtl8723_phy_rf_serial_write(hw, rfpath, regaddr, data);
114 } else {
115 if (bitmask != RFREG_OFFSET_MASK) {
116 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
117 data =
118 ((original_value & (~bitmask)) |
119 (data << bitshift));
120 }
121 _rtl8723e_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
122 }
123
124 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
125
126 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
127 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
128 regaddr, bitmask, data, rfpath);
129
130}
131
132static void _rtl8723e_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
133 enum radio_path rfpath, u32 offset,
134 u32 data)
135{
136 RT_ASSERT(false, "deprecated!\n");
137}
138
139static void _rtl8723e_phy_bb_config_1t(struct ieee80211_hw *hw)
140{
141 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
142 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
143 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
144 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
145 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
146 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
147 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
148 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
149 rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
150 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
151}
152
153bool rtl8723e_phy_mac_config(struct ieee80211_hw *hw)
154{
155 struct rtl_priv *rtlpriv = rtl_priv(hw);
156 bool rtstatus = _rtl8723e_phy_config_mac_with_headerfile(hw);
157 rtl_write_byte(rtlpriv, 0x04CA, 0x0A);
158 return rtstatus;
159}
160
161bool rtl8723e_phy_bb_config(struct ieee80211_hw *hw)
162{
163 bool rtstatus = true;
164 struct rtl_priv *rtlpriv = rtl_priv(hw);
165 u8 tmpu1b;
166 u8 b_reg_hwparafile = 1;
167
168 rtl8723_phy_init_bb_rf_reg_def(hw);
169
170
171 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_PLL_CTRL);
172 udelay(2);
173 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, (tmpu1b|BIT(1)));
174 udelay(2);
175
176 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL+1, 0xff);
177 udelay(2);
178
179
180 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
181 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
182 (tmpu1b | FEN_BB_GLB_RSTN | FEN_BBRSTB));
183
184
185 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+1);
186 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+1, (tmpu1b & (~BIT(6))));
187
188
189 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2);
190 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, (tmpu1b & (~BIT(4))));
191
192
193 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x07);
194
195 if (b_reg_hwparafile == 1)
196 rtstatus = _rtl8723e_phy_bb8192c_config_parafile(hw);
197 return rtstatus;
198}
199
200bool rtl8723e_phy_rf_config(struct ieee80211_hw *hw)
201{
202 return rtl8723e_phy_rf6052_config(hw);
203}
204
205static bool _rtl8723e_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
206{
207 struct rtl_priv *rtlpriv = rtl_priv(hw);
208 struct rtl_phy *rtlphy = &rtlpriv->phy;
209 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
210 bool rtstatus;
211
212 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
213 rtstatus = _rtl8723e_phy_config_bb_with_headerfile(hw,
214 BASEBAND_CONFIG_PHY_REG);
215 if (rtstatus != true) {
216 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!\n");
217 return false;
218 }
219
220 if (rtlphy->rf_type == RF_1T2R) {
221 _rtl8723e_phy_bb_config_1t(hw);
222 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
223 }
224 if (rtlefuse->autoload_failflag == false) {
225 rtlphy->pwrgroup_cnt = 0;
226 rtstatus = _rtl8723e_phy_config_bb_with_pgheaderfile(hw,
227 BASEBAND_CONFIG_PHY_REG);
228 }
229 if (rtstatus != true) {
230 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!\n");
231 return false;
232 }
233 rtstatus =
234 _rtl8723e_phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_AGC_TAB);
235 if (rtstatus != true) {
236 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
237 return false;
238 }
239 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
240 RFPGA0_XA_HSSIPARAMETER2,
241 0x200));
242
243 return true;
244}
245
246static bool _rtl8723e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
247{
248 struct rtl_priv *rtlpriv = rtl_priv(hw);
249 u32 i;
250 u32 arraylength;
251 u32 *ptrarray;
252
253 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl723MACPHY_Array\n");
254 arraylength = RTL8723E_MACARRAYLENGTH;
255 ptrarray = RTL8723EMAC_ARRAY;
256
257 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
258 "Img:RTL8192CEMAC_2T_ARRAY\n");
259 for (i = 0; i < arraylength; i = i + 2)
260 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
261 return true;
262}
263
264static bool _rtl8723e_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
265 u8 configtype)
266{
267 int i;
268 u32 *phy_regarray_table;
269 u32 *agctab_array_table;
270 u16 phy_reg_arraylen, agctab_arraylen;
271 struct rtl_priv *rtlpriv = rtl_priv(hw);
272
273 agctab_arraylen = RTL8723E_AGCTAB_1TARRAYLENGTH;
274 agctab_array_table = RTL8723EAGCTAB_1TARRAY;
275 phy_reg_arraylen = RTL8723E_PHY_REG_1TARRAY_LENGTH;
276 phy_regarray_table = RTL8723EPHY_REG_1TARRAY;
277 if (configtype == BASEBAND_CONFIG_PHY_REG) {
278 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
279 if (phy_regarray_table[i] == 0xfe)
280 mdelay(50);
281 else if (phy_regarray_table[i] == 0xfd)
282 mdelay(5);
283 else if (phy_regarray_table[i] == 0xfc)
284 mdelay(1);
285 else if (phy_regarray_table[i] == 0xfb)
286 udelay(50);
287 else if (phy_regarray_table[i] == 0xfa)
288 udelay(5);
289 else if (phy_regarray_table[i] == 0xf9)
290 udelay(1);
291 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
292 phy_regarray_table[i + 1]);
293 udelay(1);
294 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
295 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
296 phy_regarray_table[i],
297 phy_regarray_table[i + 1]);
298 }
299 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
300 for (i = 0; i < agctab_arraylen; i = i + 2) {
301 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
302 agctab_array_table[i + 1]);
303 udelay(1);
304 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
305 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
306 agctab_array_table[i],
307 agctab_array_table[i + 1]);
308 }
309 }
310 return true;
311}
312
313static void store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
314 u32 regaddr, u32 bitmask,
315 u32 data)
316{
317 struct rtl_priv *rtlpriv = rtl_priv(hw);
318 struct rtl_phy *rtlphy = &rtlpriv->phy;
319
320 if (regaddr == RTXAGC_A_RATE18_06) {
321 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
322 data;
323 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
324 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
325 rtlphy->pwrgroup_cnt,
326 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
327 pwrgroup_cnt][0]);
328 }
329 if (regaddr == RTXAGC_A_RATE54_24) {
330 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
331 data;
332 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
333 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
334 rtlphy->pwrgroup_cnt,
335 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
336 pwrgroup_cnt][1]);
337 }
338 if (regaddr == RTXAGC_A_CCK1_MCS32) {
339 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
340 data;
341 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
342 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
343 rtlphy->pwrgroup_cnt,
344 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
345 pwrgroup_cnt][6]);
346 }
347 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
348 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
349 data;
350 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
351 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
352 rtlphy->pwrgroup_cnt,
353 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
354 pwrgroup_cnt][7]);
355 }
356 if (regaddr == RTXAGC_A_MCS03_MCS00) {
357 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
358 data;
359 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
360 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
361 rtlphy->pwrgroup_cnt,
362 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
363 pwrgroup_cnt][2]);
364 }
365 if (regaddr == RTXAGC_A_MCS07_MCS04) {
366 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
367 data;
368 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
369 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
370 rtlphy->pwrgroup_cnt,
371 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
372 pwrgroup_cnt][3]);
373 }
374 if (regaddr == RTXAGC_A_MCS11_MCS08) {
375 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
376 data;
377 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
378 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
379 rtlphy->pwrgroup_cnt,
380 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
381 pwrgroup_cnt][4]);
382 }
383 if (regaddr == RTXAGC_A_MCS15_MCS12) {
384 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
385 data;
386 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
387 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
388 rtlphy->pwrgroup_cnt,
389 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
390 pwrgroup_cnt][5]);
391 }
392 if (regaddr == RTXAGC_B_RATE18_06) {
393 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
394 data;
395 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
396 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
397 rtlphy->pwrgroup_cnt,
398 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
399 pwrgroup_cnt][8]);
400 }
401 if (regaddr == RTXAGC_B_RATE54_24) {
402 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
403 data;
404 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
405 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
406 rtlphy->pwrgroup_cnt,
407 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
408 pwrgroup_cnt][9]);
409 }
410 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
411 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
412 data;
413 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
414 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
415 rtlphy->pwrgroup_cnt,
416 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
417 pwrgroup_cnt][14]);
418 }
419 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
420 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
421 data;
422 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
423 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
424 rtlphy->pwrgroup_cnt,
425 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
426 pwrgroup_cnt][15]);
427 }
428 if (regaddr == RTXAGC_B_MCS03_MCS00) {
429 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
430 data;
431 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
432 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
433 rtlphy->pwrgroup_cnt,
434 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
435 pwrgroup_cnt][10]);
436 }
437 if (regaddr == RTXAGC_B_MCS07_MCS04) {
438 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
439 data;
440 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
441 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
442 rtlphy->pwrgroup_cnt,
443 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
444 pwrgroup_cnt][11]);
445 }
446 if (regaddr == RTXAGC_B_MCS11_MCS08) {
447 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
448 data;
449 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
450 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
451 rtlphy->pwrgroup_cnt,
452 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
453 pwrgroup_cnt][12]);
454 }
455 if (regaddr == RTXAGC_B_MCS15_MCS12) {
456 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
457 data;
458 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
459 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
460 rtlphy->pwrgroup_cnt,
461 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
462 pwrgroup_cnt][13]);
463
464 rtlphy->pwrgroup_cnt++;
465 }
466}
467
468static bool _rtl8723e_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
469 u8 configtype)
470{
471 struct rtl_priv *rtlpriv = rtl_priv(hw);
472 int i;
473 u32 *phy_regarray_table_pg;
474 u16 phy_regarray_pg_len;
475
476 phy_regarray_pg_len = RTL8723E_PHY_REG_ARRAY_PGLENGTH;
477 phy_regarray_table_pg = RTL8723EPHY_REG_ARRAY_PG;
478
479 if (configtype == BASEBAND_CONFIG_PHY_REG) {
480 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
481 if (phy_regarray_table_pg[i] == 0xfe)
482 mdelay(50);
483 else if (phy_regarray_table_pg[i] == 0xfd)
484 mdelay(5);
485 else if (phy_regarray_table_pg[i] == 0xfc)
486 mdelay(1);
487 else if (phy_regarray_table_pg[i] == 0xfb)
488 udelay(50);
489 else if (phy_regarray_table_pg[i] == 0xfa)
490 udelay(5);
491 else if (phy_regarray_table_pg[i] == 0xf9)
492 udelay(1);
493
494 store_pwrindex_diffrate_offset(hw,
495 phy_regarray_table_pg[i],
496 phy_regarray_table_pg[i + 1],
497 phy_regarray_table_pg[i + 2]);
498 }
499 } else {
500 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
501 "configtype != BaseBand_Config_PHY_REG\n");
502 }
503 return true;
504}
505
506bool rtl8723e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
507 enum radio_path rfpath)
508{
509 int i;
510 bool rtstatus = true;
511 u32 *radioa_array_table;
512 u32 *radiob_array_table;
513 u16 radioa_arraylen, radiob_arraylen;
514
515 radioa_arraylen = RTL8723ERADIOA_1TARRAYLENGTH;
516 radioa_array_table = RTL8723E_RADIOA_1TARRAY;
517 radiob_arraylen = RTL8723E_RADIOB_1TARRAYLENGTH;
518 radiob_array_table = RTL8723E_RADIOB_1TARRAY;
519
520 rtstatus = true;
521
522 switch (rfpath) {
523 case RF90_PATH_A:
524 for (i = 0; i < radioa_arraylen; i = i + 2) {
525 if (radioa_array_table[i] == 0xfe) {
526 mdelay(50);
527 } else if (radioa_array_table[i] == 0xfd) {
528 mdelay(5);
529 } else if (radioa_array_table[i] == 0xfc) {
530 mdelay(1);
531 } else if (radioa_array_table[i] == 0xfb) {
532 udelay(50);
533 } else if (radioa_array_table[i] == 0xfa) {
534 udelay(5);
535 } else if (radioa_array_table[i] == 0xf9) {
536 udelay(1);
537 } else {
538 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
539 RFREG_OFFSET_MASK,
540 radioa_array_table[i + 1]);
541 udelay(1);
542 }
543 }
544 break;
545 case RF90_PATH_B:
546 case RF90_PATH_C:
547 case RF90_PATH_D:
548 break;
549 }
550 return true;
551}
552
553void rtl8723e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
554{
555 struct rtl_priv *rtlpriv = rtl_priv(hw);
556 struct rtl_phy *rtlphy = &rtlpriv->phy;
557
558 rtlphy->default_initialgain[0] =
559 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
560 rtlphy->default_initialgain[1] =
561 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
562 rtlphy->default_initialgain[2] =
563 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
564 rtlphy->default_initialgain[3] =
565 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
566
567 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
568 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
569 rtlphy->default_initialgain[0],
570 rtlphy->default_initialgain[1],
571 rtlphy->default_initialgain[2],
572 rtlphy->default_initialgain[3]);
573
574 rtlphy->framesync = (u8) rtl_get_bbreg(hw,
575 ROFDM0_RXDETECTOR3, MASKBYTE0);
576 rtlphy->framesync_c34 = rtl_get_bbreg(hw,
577 ROFDM0_RXDETECTOR2, MASKDWORD);
578
579 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
580 "Default framesync (0x%x) = 0x%x\n",
581 ROFDM0_RXDETECTOR3, rtlphy->framesync);
582}
583
584void rtl8723e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
585{
586 struct rtl_priv *rtlpriv = rtl_priv(hw);
587 struct rtl_phy *rtlphy = &rtlpriv->phy;
588 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
589 u8 txpwr_level;
590 long txpwr_dbm;
591
592 txpwr_level = rtlphy->cur_cck_txpwridx;
593 txpwr_dbm = rtl8723_phy_txpwr_idx_to_dbm(hw,
594 WIRELESS_MODE_B, txpwr_level);
595 txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
596 rtlefuse->legacy_ht_txpowerdiff;
597 if (rtl8723_phy_txpwr_idx_to_dbm(hw,
598 WIRELESS_MODE_G,
599 txpwr_level) > txpwr_dbm)
600 txpwr_dbm =
601 rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
602 txpwr_level);
603 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
604 if (rtl8723_phy_txpwr_idx_to_dbm(hw,
605 WIRELESS_MODE_N_24G,
606 txpwr_level) > txpwr_dbm)
607 txpwr_dbm =
608 rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
609 txpwr_level);
610 *powerlevel = txpwr_dbm;
611}
612
613static void _rtl8723e_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
614 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
615{
616 struct rtl_priv *rtlpriv = rtl_priv(hw);
617 struct rtl_phy *rtlphy = &rtlpriv->phy;
618 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
619 u8 index = (channel - 1);
620
621 cckpowerlevel[RF90_PATH_A] =
622 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
623 cckpowerlevel[RF90_PATH_B] =
624 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
625 if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
626 ofdmpowerlevel[RF90_PATH_A] =
627 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
628 ofdmpowerlevel[RF90_PATH_B] =
629 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
630 } else if (get_rf_type(rtlphy) == RF_2T2R) {
631 ofdmpowerlevel[RF90_PATH_A] =
632 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
633 ofdmpowerlevel[RF90_PATH_B] =
634 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
635 }
636}
637
638static void _rtl8723e_ccxpower_index_check(struct ieee80211_hw *hw,
639 u8 channel, u8 *cckpowerlevel,
640 u8 *ofdmpowerlevel)
641{
642 struct rtl_priv *rtlpriv = rtl_priv(hw);
643 struct rtl_phy *rtlphy = &rtlpriv->phy;
644
645 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
646 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
647
648}
649
650void rtl8723e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
651{
652 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
653 u8 cckpowerlevel[2], ofdmpowerlevel[2];
654
655 if (rtlefuse->txpwr_fromeprom == false)
656 return;
657 _rtl8723e_get_txpower_index(hw, channel,
658 &cckpowerlevel[0], &ofdmpowerlevel[0]);
659 _rtl8723e_ccxpower_index_check(hw,
660 channel, &cckpowerlevel[0],
661 &ofdmpowerlevel[0]);
662 rtl8723e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
663 rtl8723e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
664}
665
666bool rtl8723e_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
667{
668 struct rtl_priv *rtlpriv = rtl_priv(hw);
669 struct rtl_phy *rtlphy = &rtlpriv->phy;
670 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
671 u8 idx;
672 u8 rf_path;
673 u8 ccktxpwridx = _rtl8723e_phy_dbm_to_txpwr_idx(hw,
674 WIRELESS_MODE_B,
675 power_indbm);
676 u8 ofdmtxpwridx = _rtl8723e_phy_dbm_to_txpwr_idx(hw,
677 WIRELESS_MODE_N_24G,
678 power_indbm);
679 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
680 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
681 else
682 ofdmtxpwridx = 0;
683 RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
684 "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
685 power_indbm, ccktxpwridx, ofdmtxpwridx);
686 for (idx = 0; idx < 14; idx++) {
687 for (rf_path = 0; rf_path < 2; rf_path++) {
688 rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
689 rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
690 ofdmtxpwridx;
691 rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
692 ofdmtxpwridx;
693 }
694 }
695 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel);
696 return true;
697}
698
699static u8 _rtl8723e_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
700 enum wireless_mode wirelessmode,
701 long power_indbm)
702{
703 u8 txpwridx;
704 long offset;
705
706 switch (wirelessmode) {
707 case WIRELESS_MODE_B:
708 offset = -7;
709 break;
710 case WIRELESS_MODE_G:
711 case WIRELESS_MODE_N_24G:
712 offset = -8;
713 break;
714 default:
715 offset = -8;
716 break;
717 }
718
719 if ((power_indbm - offset) > 0)
720 txpwridx = (u8)((power_indbm - offset) * 2);
721 else
722 txpwridx = 0;
723
724 if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
725 txpwridx = MAX_TXPWR_IDX_NMODE_92S;
726
727 return txpwridx;
728}
729
730void rtl8723e_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
731{
732 struct rtl_priv *rtlpriv = rtl_priv(hw);
733 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
734 enum io_type iotype;
735
736 if (!is_hal_stop(rtlhal)) {
737 switch (operation) {
738 case SCAN_OPT_BACKUP_BAND0:
739 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
740 rtlpriv->cfg->ops->set_hw_reg(hw,
741 HW_VAR_IO_CMD,
742 (u8 *)&iotype);
743
744 break;
745 case SCAN_OPT_RESTORE:
746 iotype = IO_CMD_RESUME_DM_BY_SCAN;
747 rtlpriv->cfg->ops->set_hw_reg(hw,
748 HW_VAR_IO_CMD,
749 (u8 *)&iotype);
750 break;
751 default:
752 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
753 "Unknown Scan Backup operation.\n");
754 break;
755 }
756 }
757}
758
759void rtl8723e_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
760{
761 struct rtl_priv *rtlpriv = rtl_priv(hw);
762 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
763 struct rtl_phy *rtlphy = &rtlpriv->phy;
764 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
765 u8 reg_bw_opmode;
766 u8 reg_prsr_rsc;
767
768 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
769 "Switch to %s bandwidth\n",
770 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
771 "20MHz" : "40MHz");
772
773 if (is_hal_stop(rtlhal)) {
774 rtlphy->set_bwmode_inprogress = false;
775 return;
776 }
777
778 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
779 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
780
781 switch (rtlphy->current_chan_bw) {
782 case HT_CHANNEL_WIDTH_20:
783 reg_bw_opmode |= BW_OPMODE_20MHZ;
784 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
785 break;
786 case HT_CHANNEL_WIDTH_20_40:
787 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
788 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
789 reg_prsr_rsc =
790 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
791 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
792 break;
793 default:
794 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
795 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
796 break;
797 }
798
799 switch (rtlphy->current_chan_bw) {
800 case HT_CHANNEL_WIDTH_20:
801 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
802 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
803 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
804 break;
805 case HT_CHANNEL_WIDTH_20_40:
806 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
807 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
808
809 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
810 (mac->cur_40_prime_sc >> 1));
811 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
812 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
813
814 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
815 (mac->cur_40_prime_sc ==
816 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
817 break;
818 default:
819 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
820 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
821 break;
822 }
823 rtl8723e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
824 rtlphy->set_bwmode_inprogress = false;
825 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
826}
827
828void rtl8723e_phy_set_bw_mode(struct ieee80211_hw *hw,
829 enum nl80211_channel_type ch_type)
830{
831 struct rtl_priv *rtlpriv = rtl_priv(hw);
832 struct rtl_phy *rtlphy = &rtlpriv->phy;
833 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
834 u8 tmp_bw = rtlphy->current_chan_bw;
835
836 if (rtlphy->set_bwmode_inprogress)
837 return;
838 rtlphy->set_bwmode_inprogress = true;
839 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
840 rtl8723e_phy_set_bw_mode_callback(hw);
841 } else {
842 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
843 "false driver sleep or unload\n");
844 rtlphy->set_bwmode_inprogress = false;
845 rtlphy->current_chan_bw = tmp_bw;
846 }
847}
848
849void rtl8723e_phy_sw_chnl_callback(struct ieee80211_hw *hw)
850{
851 struct rtl_priv *rtlpriv = rtl_priv(hw);
852 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
853 struct rtl_phy *rtlphy = &rtlpriv->phy;
854 u32 delay;
855
856 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
857 "switch to channel%d\n", rtlphy->current_channel);
858 if (is_hal_stop(rtlhal))
859 return;
860 do {
861 if (!rtlphy->sw_chnl_inprogress)
862 break;
863 if (!_rtl8723e_phy_sw_chnl_step_by_step
864 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
865 &rtlphy->sw_chnl_step, &delay)) {
866 if (delay > 0)
867 mdelay(delay);
868 else
869 continue;
870 } else {
871 rtlphy->sw_chnl_inprogress = false;
872 }
873 break;
874 } while (true);
875 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
876}
877
878u8 rtl8723e_phy_sw_chnl(struct ieee80211_hw *hw)
879{
880 struct rtl_priv *rtlpriv = rtl_priv(hw);
881 struct rtl_phy *rtlphy = &rtlpriv->phy;
882 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
883
884 if (rtlphy->sw_chnl_inprogress)
885 return 0;
886 if (rtlphy->set_bwmode_inprogress)
887 return 0;
888 RT_ASSERT((rtlphy->current_channel <= 14),
889 "WIRELESS_MODE_G but channel>14");
890 rtlphy->sw_chnl_inprogress = true;
891 rtlphy->sw_chnl_stage = 0;
892 rtlphy->sw_chnl_step = 0;
893 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
894 rtl8723e_phy_sw_chnl_callback(hw);
895 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
896 "sw_chnl_inprogress false schedule workitem\n");
897 rtlphy->sw_chnl_inprogress = false;
898 } else {
899 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
900 "sw_chnl_inprogress false driver sleep or unload\n");
901 rtlphy->sw_chnl_inprogress = false;
902 }
903 return 1;
904}
905
906static void _rtl8723e_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel)
907{
908 struct rtl_priv *rtlpriv = rtl_priv(hw);
909 struct rtl_phy *rtlphy = &rtlpriv->phy;
910 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
911
912 if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
913 if (channel == 6 && rtlphy->current_chan_bw ==
914 HT_CHANNEL_WIDTH_20)
915 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1,
916 MASKDWORD, 0x00255);
917 else{
918 u32 backuprf0x1a = (u32)rtl_get_rfreg(hw,
919 RF90_PATH_A, RF_RX_G1,
920 RFREG_OFFSET_MASK);
921 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1,
922 MASKDWORD, backuprf0x1a);
923 }
924 }
925}
926
927static bool _rtl8723e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
928 u8 channel, u8 *stage, u8 *step,
929 u32 *delay)
930{
931 struct rtl_priv *rtlpriv = rtl_priv(hw);
932 struct rtl_phy *rtlphy = &rtlpriv->phy;
933 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
934 u32 precommoncmdcnt;
935 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
936 u32 postcommoncmdcnt;
937 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
938 u32 rfdependcmdcnt;
939 struct swchnlcmd *currentcmd = NULL;
940 u8 rfpath;
941 u8 num_total_rfpath = rtlphy->num_total_rfpath;
942
943 precommoncmdcnt = 0;
944 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
945 MAX_PRECMD_CNT,
946 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
947 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
948 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
949
950 postcommoncmdcnt = 0;
951
952 rtl8723_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
953 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
954
955 rfdependcmdcnt = 0;
956
957 RT_ASSERT((channel >= 1 && channel <= 14),
958 "illegal channel for Zebra: %d\n", channel);
959
960 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
961 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
962 RF_CHNLBW, channel, 10);
963
964 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
965 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
966 0);
967
968 do {
969 switch (*stage) {
970 case 0:
971 currentcmd = &precommoncmd[*step];
972 break;
973 case 1:
974 currentcmd = &rfdependcmd[*step];
975 break;
976 case 2:
977 currentcmd = &postcommoncmd[*step];
978 break;
979 default:
980 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
981 "Invalid 'stage' = %d, Check it!\n", *stage);
982 return true;
983 }
984
985 if (currentcmd->cmdid == CMDID_END) {
986 if ((*stage) == 2) {
987 return true;
988 } else {
989 (*stage)++;
990 (*step) = 0;
991 continue;
992 }
993 }
994
995 switch (currentcmd->cmdid) {
996 case CMDID_SET_TXPOWEROWER_LEVEL:
997 rtl8723e_phy_set_txpower_level(hw, channel);
998 break;
999 case CMDID_WRITEPORT_ULONG:
1000 rtl_write_dword(rtlpriv, currentcmd->para1,
1001 currentcmd->para2);
1002 break;
1003 case CMDID_WRITEPORT_USHORT:
1004 rtl_write_word(rtlpriv, currentcmd->para1,
1005 (u16) currentcmd->para2);
1006 break;
1007 case CMDID_WRITEPORT_UCHAR:
1008 rtl_write_byte(rtlpriv, currentcmd->para1,
1009 (u8) currentcmd->para2);
1010 break;
1011 case CMDID_RF_WRITEREG:
1012 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
1013 rtlphy->rfreg_chnlval[rfpath] =
1014 ((rtlphy->rfreg_chnlval[rfpath] &
1015 0xfffffc00) | currentcmd->para2);
1016
1017 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1018 currentcmd->para1,
1019 RFREG_OFFSET_MASK,
1020 rtlphy->rfreg_chnlval[rfpath]);
1021 }
1022 _rtl8723e_phy_sw_rf_seting(hw, channel);
1023 break;
1024 default:
1025 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1026 "switch case %#x not processed\n",
1027 currentcmd->cmdid);
1028 break;
1029 }
1030
1031 break;
1032 } while (true);
1033
1034 (*delay) = currentcmd->msdelay;
1035 (*step)++;
1036 return false;
1037}
1038
1039static u8 _rtl8723e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1040{
1041 u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
1042 u8 result = 0x00;
1043
1044 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1045 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1046 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1047 rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
1048 config_pathb ? 0x28160202 : 0x28160502);
1049
1050 if (config_pathb) {
1051 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1052 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1053 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1054 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
1055 }
1056
1057 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
1058 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1059 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1060
1061 mdelay(IQK_DELAY_TIME);
1062
1063 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1064 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1065 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1066 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1067
1068 if (!(reg_eac & BIT(28)) &&
1069 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1070 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1071 result |= 0x01;
1072 else
1073 return result;
1074
1075 if (!(reg_eac & BIT(27)) &&
1076 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1077 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1078 result |= 0x02;
1079 return result;
1080}
1081
1082static u8 _rtl8723e_phy_path_b_iqk(struct ieee80211_hw *hw)
1083{
1084 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1085 u8 result = 0x00;
1086
1087 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1088 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1089 mdelay(IQK_DELAY_TIME);
1090 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1091 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1092 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1093 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1094 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1095
1096 if (!(reg_eac & BIT(31)) &&
1097 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1098 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1099 result |= 0x01;
1100 else
1101 return result;
1102 if (!(reg_eac & BIT(30)) &&
1103 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1104 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1105 result |= 0x02;
1106 return result;
1107}
1108
1109static bool _rtl8723e_phy_simularity_compare(struct ieee80211_hw *hw,
1110 long result[][8], u8 c1, u8 c2)
1111{
1112 u32 i, j, diff, simularity_bitmap, bound;
1113
1114 u8 final_candidate[2] = { 0xFF, 0xFF };
1115 bool bresult = true;
1116
1117 bound = 4;
1118
1119 simularity_bitmap = 0;
1120
1121 for (i = 0; i < bound; i++) {
1122 diff = (result[c1][i] > result[c2][i]) ?
1123 (result[c1][i] - result[c2][i]) :
1124 (result[c2][i] - result[c1][i]);
1125
1126 if (diff > MAX_TOLERANCE) {
1127 if ((i == 2 || i == 6) && !simularity_bitmap) {
1128 if (result[c1][i] + result[c1][i + 1] == 0)
1129 final_candidate[(i / 4)] = c2;
1130 else if (result[c2][i] + result[c2][i + 1] == 0)
1131 final_candidate[(i / 4)] = c1;
1132 else
1133 simularity_bitmap = simularity_bitmap |
1134 (1 << i);
1135 } else
1136 simularity_bitmap =
1137 simularity_bitmap | (1 << i);
1138 }
1139 }
1140
1141 if (simularity_bitmap == 0) {
1142 for (i = 0; i < (bound / 4); i++) {
1143 if (final_candidate[i] != 0xFF) {
1144 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1145 result[3][j] =
1146 result[final_candidate[i]][j];
1147 bresult = false;
1148 }
1149 }
1150 return bresult;
1151 } else if (!(simularity_bitmap & 0x0F)) {
1152 for (i = 0; i < 4; i++)
1153 result[3][i] = result[c1][i];
1154 return false;
1155 } else {
1156 return false;
1157 }
1158
1159}
1160
1161static void _rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw,
1162 long result[][8], u8 t, bool is2t)
1163{
1164 struct rtl_priv *rtlpriv = rtl_priv(hw);
1165 struct rtl_phy *rtlphy = &rtlpriv->phy;
1166 u32 i;
1167 u8 patha_ok, pathb_ok;
1168 u32 adda_reg[IQK_ADDA_REG_NUM] = {
1169 0x85c, 0xe6c, 0xe70, 0xe74,
1170 0xe78, 0xe7c, 0xe80, 0xe84,
1171 0xe88, 0xe8c, 0xed0, 0xed4,
1172 0xed8, 0xedc, 0xee0, 0xeec
1173 };
1174
1175 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1176 0x522, 0x550, 0x551, 0x040
1177 };
1178
1179 const u32 retrycount = 2;
1180
1181 u32 bbvalue;
1182
1183 if (t == 0) {
1184 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
1185
1186 rtl8723_save_adda_registers(hw, adda_reg,
1187 rtlphy->adda_backup, 16);
1188 rtl8723_phy_save_mac_registers(hw, iqk_mac_reg,
1189 rtlphy->iqk_mac_backup);
1190 }
1191 rtl8723_phy_path_adda_on(hw, adda_reg, true, is2t);
1192 if (t == 0) {
1193 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1194 RFPGA0_XA_HSSIPARAMETER1,
1195 BIT(8));
1196 }
1197
1198 if (!rtlphy->rfpi_enable)
1199 rtl8723_phy_pi_mode_switch(hw, true);
1200 if (t == 0) {
1201 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1202 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1203 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1204 }
1205 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1206 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1207 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1208 if (is2t) {
1209 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1210 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1211 }
1212 rtl8723_phy_mac_setting_calibration(hw, iqk_mac_reg,
1213 rtlphy->iqk_mac_backup);
1214 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1215 if (is2t)
1216 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1217 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1218 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1219 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1220 for (i = 0; i < retrycount; i++) {
1221 patha_ok = _rtl8723e_phy_path_a_iqk(hw, is2t);
1222 if (patha_ok == 0x03) {
1223 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1224 0x3FF0000) >> 16;
1225 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1226 0x3FF0000) >> 16;
1227 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1228 0x3FF0000) >> 16;
1229 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1230 0x3FF0000) >> 16;
1231 break;
1232 } else if (i == (retrycount - 1) && patha_ok == 0x01)
1233
1234 result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1235 MASKDWORD) & 0x3FF0000) >>
1236 16;
1237 result[t][1] =
1238 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1239
1240 }
1241
1242 if (is2t) {
1243 rtl8723_phy_path_a_standby(hw);
1244 rtl8723_phy_path_adda_on(hw, adda_reg, false, is2t);
1245 for (i = 0; i < retrycount; i++) {
1246 pathb_ok = _rtl8723e_phy_path_b_iqk(hw);
1247 if (pathb_ok == 0x03) {
1248 result[t][4] = (rtl_get_bbreg(hw,
1249 0xeb4,
1250 MASKDWORD) &
1251 0x3FF0000) >> 16;
1252 result[t][5] =
1253 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1254 0x3FF0000) >> 16;
1255 result[t][6] =
1256 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1257 0x3FF0000) >> 16;
1258 result[t][7] =
1259 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1260 0x3FF0000) >> 16;
1261 break;
1262 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1263 result[t][4] = (rtl_get_bbreg(hw,
1264 0xeb4,
1265 MASKDWORD) &
1266 0x3FF0000) >> 16;
1267 }
1268 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1269 0x3FF0000) >> 16;
1270 }
1271 }
1272 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1273 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1274 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1275 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1276 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1277 if (is2t)
1278 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1279 if (t != 0) {
1280 if (!rtlphy->rfpi_enable)
1281 rtl8723_phy_pi_mode_switch(hw, false);
1282 rtl8723_phy_reload_adda_registers(hw, adda_reg,
1283 rtlphy->adda_backup, 16);
1284 rtl8723_phy_reload_mac_registers(hw, iqk_mac_reg,
1285 rtlphy->iqk_mac_backup);
1286 }
1287}
1288
1289static void _rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1290{
1291 u8 tmpreg;
1292 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
1293 struct rtl_priv *rtlpriv = rtl_priv(hw);
1294
1295 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
1296
1297 if ((tmpreg & 0x70) != 0)
1298 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
1299 else
1300 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1301
1302 if ((tmpreg & 0x70) != 0) {
1303 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
1304
1305 if (is2t)
1306 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
1307 MASK12BITS);
1308
1309 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
1310 (rf_a_mode & 0x8FFFF) | 0x10000);
1311
1312 if (is2t)
1313 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1314 (rf_b_mode & 0x8FFFF) | 0x10000);
1315 }
1316 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
1317
1318 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
1319
1320 mdelay(100);
1321
1322 if ((tmpreg & 0x70) != 0) {
1323 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
1324 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
1325
1326 if (is2t)
1327 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1328 rf_b_mode);
1329 } else {
1330 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1331 }
1332}
1333
1334static void _rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1335 bool bmain, bool is2t)
1336{
1337 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1338
1339 if (is_hal_stop(rtlhal)) {
1340 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1341 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1342 }
1343 if (is2t) {
1344 if (bmain)
1345 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1346 BIT(5) | BIT(6), 0x1);
1347 else
1348 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1349 BIT(5) | BIT(6), 0x2);
1350 } else {
1351 if (bmain)
1352 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1353 else
1354 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1355
1356 }
1357
1358}
1359
1360#undef IQK_ADDA_REG_NUM
1361#undef IQK_DELAY_TIME
1362
1363void rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1364{
1365 struct rtl_priv *rtlpriv = rtl_priv(hw);
1366 struct rtl_phy *rtlphy = &rtlpriv->phy;
1367
1368 long result[4][8];
1369 u8 i, final_candidate;
1370 bool b_patha_ok, b_pathb_ok;
1371 long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
1372 reg_ecc, reg_tmp = 0;
1373 bool is12simular, is13simular, is23simular;
1374 u32 iqk_bb_reg[10] = {
1375 ROFDM0_XARXIQIMBALANCE,
1376 ROFDM0_XBRXIQIMBALANCE,
1377 ROFDM0_ECCATHRESHOLD,
1378 ROFDM0_AGCRSSITABLE,
1379 ROFDM0_XATXIQIMBALANCE,
1380 ROFDM0_XBTXIQIMBALANCE,
1381 ROFDM0_XCTXIQIMBALANCE,
1382 ROFDM0_XCTXAFE,
1383 ROFDM0_XDTXAFE,
1384 ROFDM0_RXIQEXTANTA
1385 };
1386
1387 if (b_recovery) {
1388 rtl8723_phy_reload_adda_registers(hw,
1389 iqk_bb_reg,
1390 rtlphy->iqk_bb_backup, 10);
1391 return;
1392 }
1393 for (i = 0; i < 8; i++) {
1394 result[0][i] = 0;
1395 result[1][i] = 0;
1396 result[2][i] = 0;
1397 result[3][i] = 0;
1398 }
1399 final_candidate = 0xff;
1400 b_patha_ok = false;
1401 b_pathb_ok = false;
1402 is12simular = false;
1403 is23simular = false;
1404 is13simular = false;
1405 for (i = 0; i < 3; i++) {
1406 _rtl8723e_phy_iq_calibrate(hw, result, i, false);
1407 if (i == 1) {
1408 is12simular =
1409 _rtl8723e_phy_simularity_compare(hw, result, 0, 1);
1410 if (is12simular) {
1411 final_candidate = 0;
1412 break;
1413 }
1414 }
1415 if (i == 2) {
1416 is13simular =
1417 _rtl8723e_phy_simularity_compare(hw, result, 0, 2);
1418 if (is13simular) {
1419 final_candidate = 0;
1420 break;
1421 }
1422 is23simular =
1423 _rtl8723e_phy_simularity_compare(hw, result, 1, 2);
1424 if (is23simular)
1425 final_candidate = 1;
1426 else {
1427 for (i = 0; i < 8; i++)
1428 reg_tmp += result[3][i];
1429
1430 if (reg_tmp != 0)
1431 final_candidate = 3;
1432 else
1433 final_candidate = 0xFF;
1434 }
1435 }
1436 }
1437 for (i = 0; i < 4; i++) {
1438 reg_e94 = result[i][0];
1439 reg_e9c = result[i][1];
1440 reg_ea4 = result[i][2];
1441 reg_eac = result[i][3];
1442 reg_eb4 = result[i][4];
1443 reg_ebc = result[i][5];
1444 reg_ec4 = result[i][6];
1445 reg_ecc = result[i][7];
1446 }
1447 if (final_candidate != 0xff) {
1448 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1449 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1450 reg_ea4 = result[final_candidate][2];
1451 reg_eac = result[final_candidate][3];
1452 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1453 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1454 reg_ec4 = result[final_candidate][6];
1455 reg_ecc = result[final_candidate][7];
1456 b_patha_ok = true;
1457 b_pathb_ok = true;
1458 } else {
1459 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1460 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1461 }
1462 if (reg_e94 != 0)
1463 rtl8723_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
1464 final_candidate,
1465 (reg_ea4 == 0));
1466 rtl8723_save_adda_registers(hw, iqk_bb_reg,
1467 rtlphy->iqk_bb_backup, 10);
1468}
1469
1470void rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw)
1471{
1472 _rtl8723e_phy_lc_calibrate(hw, false);
1473}
1474
1475void rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1476{
1477 _rtl8723e_phy_set_rfpath_switch(hw, bmain, false);
1478}
1479
1480bool rtl8723e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1481{
1482 struct rtl_priv *rtlpriv = rtl_priv(hw);
1483 struct rtl_phy *rtlphy = &rtlpriv->phy;
1484 bool postprocessing = false;
1485
1486 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1487 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1488 iotype, rtlphy->set_io_inprogress);
1489 do {
1490 switch (iotype) {
1491 case IO_CMD_RESUME_DM_BY_SCAN:
1492 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1493 "[IO CMD] Resume DM after scan.\n");
1494 postprocessing = true;
1495 break;
1496 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1497 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1498 "[IO CMD] Pause DM before scan.\n");
1499 postprocessing = true;
1500 break;
1501 default:
1502 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1503 "switch case %#x not processed\n", iotype);
1504 break;
1505 }
1506 } while (false);
1507 if (postprocessing && !rtlphy->set_io_inprogress) {
1508 rtlphy->set_io_inprogress = true;
1509 rtlphy->current_io_type = iotype;
1510 } else {
1511 return false;
1512 }
1513 rtl8723e_phy_set_io(hw);
1514 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
1515 return true;
1516}
1517
1518static void rtl8723e_phy_set_io(struct ieee80211_hw *hw)
1519{
1520 struct rtl_priv *rtlpriv = rtl_priv(hw);
1521 struct rtl_phy *rtlphy = &rtlpriv->phy;
1522 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
1523
1524 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1525 "--->Cmd(%#x), set_io_inprogress(%d)\n",
1526 rtlphy->current_io_type, rtlphy->set_io_inprogress);
1527 switch (rtlphy->current_io_type) {
1528 case IO_CMD_RESUME_DM_BY_SCAN:
1529 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1530 rtl8723e_dm_write_dig(hw);
1531 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel);
1532 break;
1533 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1534 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
1535 dm_digtable->cur_igvalue = 0x17;
1536 rtl8723e_dm_write_dig(hw);
1537 break;
1538 default:
1539 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1540 "switch case %#x not processed\n",
1541 rtlphy->current_io_type);
1542 break;
1543 }
1544 rtlphy->set_io_inprogress = false;
1545 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1546 "(%#x)\n", rtlphy->current_io_type);
1547}
1548
1549static void rtl8723e_phy_set_rf_on(struct ieee80211_hw *hw)
1550{
1551 struct rtl_priv *rtlpriv = rtl_priv(hw);
1552
1553 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
1554 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1555 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1556 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1557 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1558 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1559}
1560
1561static void _rtl8723e_phy_set_rf_sleep(struct ieee80211_hw *hw)
1562{
1563 u32 u4b_tmp;
1564 u8 delay = 5;
1565 struct rtl_priv *rtlpriv = rtl_priv(hw);
1566
1567 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1568 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1569 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1570 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1571 while (u4b_tmp != 0 && delay > 0) {
1572 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
1573 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1574 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1575 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1576 delay--;
1577 }
1578 if (delay == 0) {
1579 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1580 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1581 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1582 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1583 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1584 "Switch RF timeout !!!.\n");
1585 return;
1586 }
1587 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1588 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
1589}
1590
1591static bool _rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw,
1592 enum rf_pwrstate rfpwr_state)
1593{
1594 struct rtl_priv *rtlpriv = rtl_priv(hw);
1595 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1596 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1597 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1598 bool bresult = true;
1599 u8 i, queue_id;
1600 struct rtl8192_tx_ring *ring = NULL;
1601
1602 switch (rfpwr_state) {
1603 case ERFON:
1604 if ((ppsc->rfpwr_state == ERFOFF) &&
1605 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
1606 bool rtstatus;
1607 u32 initializecount = 0;
1608
1609 do {
1610 initializecount++;
1611 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1612 "IPS Set eRf nic enable\n");
1613 rtstatus = rtl_ps_enable_nic(hw);
1614 } while (!rtstatus && (initializecount < 10));
1615 RT_CLEAR_PS_LEVEL(ppsc,
1616 RT_RF_OFF_LEVL_HALT_NIC);
1617 } else {
1618 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1619 "Set ERFON sleeped:%d ms\n",
1620 jiffies_to_msecs(jiffies -
1621 ppsc->
1622 last_sleep_jiffies));
1623 ppsc->last_awake_jiffies = jiffies;
1624 rtl8723e_phy_set_rf_on(hw);
1625 }
1626 if (mac->link_state == MAC80211_LINKED) {
1627 rtlpriv->cfg->ops->led_control(hw,
1628 LED_CTL_LINK);
1629 } else {
1630 rtlpriv->cfg->ops->led_control(hw,
1631 LED_CTL_NO_LINK);
1632 }
1633 break;
1634 case ERFOFF:
1635 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
1636 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1637 "IPS Set eRf nic disable\n");
1638 rtl_ps_disable_nic(hw);
1639 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1640 } else {
1641 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
1642 rtlpriv->cfg->ops->led_control(hw,
1643 LED_CTL_NO_LINK);
1644 } else {
1645 rtlpriv->cfg->ops->led_control(hw,
1646 LED_CTL_POWER_OFF);
1647 }
1648 }
1649 break;
1650 case ERFSLEEP:
1651 if (ppsc->rfpwr_state == ERFOFF)
1652 break;
1653 for (queue_id = 0, i = 0;
1654 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
1655 ring = &pcipriv->dev.tx_ring[queue_id];
1656 if (queue_id == BEACON_QUEUE ||
1657 skb_queue_len(&ring->queue) == 0) {
1658 queue_id++;
1659 continue;
1660 } else {
1661 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1662 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
1663 (i + 1), queue_id,
1664 skb_queue_len(&ring->queue));
1665
1666 udelay(10);
1667 i++;
1668 }
1669 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1670 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1671 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
1672 MAX_DOZE_WAITING_TIMES_9x,
1673 queue_id,
1674 skb_queue_len(&ring->queue));
1675 break;
1676 }
1677 }
1678 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1679 "Set ERFSLEEP awaked:%d ms\n",
1680 jiffies_to_msecs(jiffies -
1681 ppsc->last_awake_jiffies));
1682 ppsc->last_sleep_jiffies = jiffies;
1683 _rtl8723e_phy_set_rf_sleep(hw);
1684 break;
1685 default:
1686 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1687 "switch case %#x not processed\n", rfpwr_state);
1688 bresult = false;
1689 break;
1690 }
1691 if (bresult)
1692 ppsc->rfpwr_state = rfpwr_state;
1693 return bresult;
1694}
1695
1696bool rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw,
1697 enum rf_pwrstate rfpwr_state)
1698{
1699 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1700
1701 bool bresult = false;
1702
1703 if (rfpwr_state == ppsc->rfpwr_state)
1704 return bresult;
1705 bresult = _rtl8723e_phy_set_rf_power_state(hw, rfpwr_state);
1706 return bresult;
1707}
1708
