1
2
3
4
5
6
7
8
9
10
11
12
13
14
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/regmap.h>
21#include <dt-bindings/pinctrl/mt65xx.h>
22
23#include "pinctrl-mtk-common.h"
24#include "pinctrl-mtk-mt8135.h"
25
26#define DRV_BASE1 0x500
27#define DRV_BASE2 0x510
28#define PUPD_BASE1 0x400
29#define PUPD_BASE2 0x450
30#define R0_BASE1 0x4d0
31#define R1_BASE1 0x200
32#define R1_BASE2 0x250
33
34struct mtk_spec_pull_set {
35 unsigned char pin;
36 unsigned char pupd_bit;
37 unsigned short pupd_offset;
38 unsigned short r0_offset;
39 unsigned short r1_offset;
40 unsigned char r0_bit;
41 unsigned char r1_bit;
42};
43
44#define SPEC_PULL(_pin, _pupd_offset, _pupd_bit, _r0_offset, \
45 _r0_bit, _r1_offset, _r1_bit) \
46 { \
47 .pin = _pin, \
48 .pupd_offset = _pupd_offset, \
49 .pupd_bit = _pupd_bit, \
50 .r0_offset = _r0_offset, \
51 .r0_bit = _r0_bit, \
52 .r1_offset = _r1_offset, \
53 .r1_bit = _r1_bit, \
54 }
55
56static const struct mtk_drv_group_desc mt8135_drv_grp[] = {
57
58 MTK_DRV_GRP(2, 16, 0, 2, 2),
59
60 MTK_DRV_GRP(4, 16, 1, 2, 4),
61
62 MTK_DRV_GRP(2, 8, 0, 1, 2),
63
64 MTK_DRV_GRP(4, 32, 0, 2, 4)
65};
66
67static const struct mtk_pin_drv_grp mt8135_pin_drv[] = {
68 MTK_PIN_DRV_GRP(0, DRV_BASE1, 0, 0),
69 MTK_PIN_DRV_GRP(1, DRV_BASE1, 0, 0),
70 MTK_PIN_DRV_GRP(2, DRV_BASE1, 0, 0),
71 MTK_PIN_DRV_GRP(3, DRV_BASE1, 0, 0),
72 MTK_PIN_DRV_GRP(4, DRV_BASE1, 4, 0),
73 MTK_PIN_DRV_GRP(5, DRV_BASE1, 8, 0),
74 MTK_PIN_DRV_GRP(6, DRV_BASE1, 0, 0),
75 MTK_PIN_DRV_GRP(7, DRV_BASE1, 0, 0),
76 MTK_PIN_DRV_GRP(8, DRV_BASE1, 0, 0),
77 MTK_PIN_DRV_GRP(9, DRV_BASE1, 0, 0),
78
79 MTK_PIN_DRV_GRP(10, DRV_BASE1, 12, 1),
80 MTK_PIN_DRV_GRP(11, DRV_BASE1, 12, 1),
81 MTK_PIN_DRV_GRP(12, DRV_BASE1, 12, 1),
82 MTK_PIN_DRV_GRP(13, DRV_BASE1, 12, 1),
83 MTK_PIN_DRV_GRP(14, DRV_BASE1, 12, 1),
84 MTK_PIN_DRV_GRP(15, DRV_BASE1, 12, 1),
85 MTK_PIN_DRV_GRP(16, DRV_BASE1, 12, 1),
86 MTK_PIN_DRV_GRP(17, DRV_BASE1, 16, 1),
87 MTK_PIN_DRV_GRP(18, DRV_BASE1, 16, 1),
88 MTK_PIN_DRV_GRP(19, DRV_BASE1, 16, 1),
89 MTK_PIN_DRV_GRP(20, DRV_BASE1, 16, 1),
90 MTK_PIN_DRV_GRP(21, DRV_BASE1, 16, 1),
91 MTK_PIN_DRV_GRP(22, DRV_BASE1, 16, 1),
92 MTK_PIN_DRV_GRP(23, DRV_BASE1, 16, 1),
93 MTK_PIN_DRV_GRP(24, DRV_BASE1, 16, 1),
94 MTK_PIN_DRV_GRP(33, DRV_BASE1, 24, 1),
95 MTK_PIN_DRV_GRP(34, DRV_BASE2, 12, 2),
96 MTK_PIN_DRV_GRP(37, DRV_BASE2, 20, 1),
97 MTK_PIN_DRV_GRP(38, DRV_BASE2, 20, 1),
98 MTK_PIN_DRV_GRP(39, DRV_BASE2, 20, 1),
99 MTK_PIN_DRV_GRP(40, DRV_BASE2, 24, 1),
100 MTK_PIN_DRV_GRP(41, DRV_BASE2, 24, 1),
101 MTK_PIN_DRV_GRP(42, DRV_BASE2, 24, 1),
102 MTK_PIN_DRV_GRP(43, DRV_BASE2, 28, 1),
103 MTK_PIN_DRV_GRP(44, DRV_BASE2, 28, 1),
104 MTK_PIN_DRV_GRP(45, DRV_BASE2, 28, 1),
105 MTK_PIN_DRV_GRP(46, DRV_BASE2, 28, 1),
106 MTK_PIN_DRV_GRP(47, DRV_BASE2, 28, 1),
107
108 MTK_PIN_DRV_GRP(49, DRV_BASE2+0x10, 0, 1),
109 MTK_PIN_DRV_GRP(50, DRV_BASE2+0x10, 4, 1),
110 MTK_PIN_DRV_GRP(51, DRV_BASE2+0x10, 8, 1),
111 MTK_PIN_DRV_GRP(52, DRV_BASE2+0x10, 12, 2),
112 MTK_PIN_DRV_GRP(53, DRV_BASE2+0x10, 16, 1),
113 MTK_PIN_DRV_GRP(54, DRV_BASE2+0x10, 20, 1),
114 MTK_PIN_DRV_GRP(55, DRV_BASE2+0x10, 24, 1),
115 MTK_PIN_DRV_GRP(56, DRV_BASE2+0x10, 28, 1),
116
117 MTK_PIN_DRV_GRP(57, DRV_BASE2+0x20, 0, 1),
118 MTK_PIN_DRV_GRP(58, DRV_BASE2+0x20, 0, 1),
119 MTK_PIN_DRV_GRP(59, DRV_BASE2+0x20, 0, 1),
120 MTK_PIN_DRV_GRP(60, DRV_BASE2+0x20, 0, 1),
121 MTK_PIN_DRV_GRP(61, DRV_BASE2+0x20, 0, 1),
122 MTK_PIN_DRV_GRP(62, DRV_BASE2+0x20, 0, 1),
123 MTK_PIN_DRV_GRP(63, DRV_BASE2+0x20, 4, 1),
124 MTK_PIN_DRV_GRP(64, DRV_BASE2+0x20, 8, 1),
125 MTK_PIN_DRV_GRP(65, DRV_BASE2+0x20, 12, 1),
126 MTK_PIN_DRV_GRP(66, DRV_BASE2+0x20, 16, 1),
127 MTK_PIN_DRV_GRP(67, DRV_BASE2+0x20, 20, 1),
128 MTK_PIN_DRV_GRP(68, DRV_BASE2+0x20, 24, 1),
129 MTK_PIN_DRV_GRP(69, DRV_BASE2+0x20, 28, 1),
130
131 MTK_PIN_DRV_GRP(70, DRV_BASE2+0x30, 0, 1),
132 MTK_PIN_DRV_GRP(71, DRV_BASE2+0x30, 4, 1),
133 MTK_PIN_DRV_GRP(72, DRV_BASE2+0x30, 8, 1),
134 MTK_PIN_DRV_GRP(73, DRV_BASE2+0x30, 12, 1),
135 MTK_PIN_DRV_GRP(74, DRV_BASE2+0x30, 16, 1),
136 MTK_PIN_DRV_GRP(75, DRV_BASE2+0x30, 20, 1),
137 MTK_PIN_DRV_GRP(76, DRV_BASE2+0x30, 24, 1),
138 MTK_PIN_DRV_GRP(77, DRV_BASE2+0x30, 28, 3),
139 MTK_PIN_DRV_GRP(78, DRV_BASE2+0x30, 28, 3),
140
141 MTK_PIN_DRV_GRP(79, DRV_BASE2+0x40, 0, 3),
142 MTK_PIN_DRV_GRP(80, DRV_BASE2+0x40, 4, 3),
143
144 MTK_PIN_DRV_GRP(81, DRV_BASE2+0x30, 28, 3),
145 MTK_PIN_DRV_GRP(82, DRV_BASE2+0x30, 28, 3),
146
147 MTK_PIN_DRV_GRP(83, DRV_BASE2+0x40, 8, 3),
148 MTK_PIN_DRV_GRP(84, DRV_BASE2+0x40, 8, 3),
149 MTK_PIN_DRV_GRP(85, DRV_BASE2+0x40, 12, 3),
150 MTK_PIN_DRV_GRP(86, DRV_BASE2+0x40, 16, 3),
151 MTK_PIN_DRV_GRP(87, DRV_BASE2+0x40, 8, 3),
152 MTK_PIN_DRV_GRP(88, DRV_BASE2+0x40, 8, 3),
153
154 MTK_PIN_DRV_GRP(89, DRV_BASE2+0x50, 12, 0),
155 MTK_PIN_DRV_GRP(90, DRV_BASE2+0x50, 12, 0),
156 MTK_PIN_DRV_GRP(91, DRV_BASE2+0x50, 12, 0),
157 MTK_PIN_DRV_GRP(92, DRV_BASE2+0x50, 12, 0),
158 MTK_PIN_DRV_GRP(93, DRV_BASE2+0x50, 12, 0),
159 MTK_PIN_DRV_GRP(94, DRV_BASE2+0x50, 12, 0),
160 MTK_PIN_DRV_GRP(95, DRV_BASE2+0x50, 12, 0),
161
162 MTK_PIN_DRV_GRP(96, DRV_BASE1+0xb0, 28, 0),
163
164 MTK_PIN_DRV_GRP(97, DRV_BASE2+0x50, 12, 0),
165 MTK_PIN_DRV_GRP(98, DRV_BASE2+0x50, 16, 0),
166 MTK_PIN_DRV_GRP(99, DRV_BASE2+0x50, 20, 1),
167 MTK_PIN_DRV_GRP(102, DRV_BASE2+0x50, 24, 1),
168 MTK_PIN_DRV_GRP(103, DRV_BASE2+0x50, 28, 1),
169
170
171 MTK_PIN_DRV_GRP(104, DRV_BASE2+0x60, 0, 1),
172 MTK_PIN_DRV_GRP(105, DRV_BASE2+0x60, 4, 1),
173 MTK_PIN_DRV_GRP(106, DRV_BASE2+0x60, 4, 1),
174 MTK_PIN_DRV_GRP(107, DRV_BASE2+0x60, 4, 1),
175 MTK_PIN_DRV_GRP(108, DRV_BASE2+0x60, 4, 1),
176 MTK_PIN_DRV_GRP(109, DRV_BASE2+0x60, 8, 2),
177 MTK_PIN_DRV_GRP(110, DRV_BASE2+0x60, 12, 2),
178 MTK_PIN_DRV_GRP(111, DRV_BASE2+0x60, 16, 2),
179 MTK_PIN_DRV_GRP(112, DRV_BASE2+0x60, 20, 2),
180 MTK_PIN_DRV_GRP(113, DRV_BASE2+0x60, 24, 2),
181 MTK_PIN_DRV_GRP(114, DRV_BASE2+0x60, 28, 2),
182
183 MTK_PIN_DRV_GRP(115, DRV_BASE2+0x70, 0, 2),
184 MTK_PIN_DRV_GRP(116, DRV_BASE2+0x70, 4, 2),
185 MTK_PIN_DRV_GRP(117, DRV_BASE2+0x70, 8, 2),
186 MTK_PIN_DRV_GRP(118, DRV_BASE2+0x70, 12, 2),
187 MTK_PIN_DRV_GRP(119, DRV_BASE2+0x70, 16, 2),
188 MTK_PIN_DRV_GRP(120, DRV_BASE2+0x70, 20, 2),
189
190 MTK_PIN_DRV_GRP(181, DRV_BASE1+0xa0, 12, 1),
191 MTK_PIN_DRV_GRP(182, DRV_BASE1+0xa0, 16, 1),
192 MTK_PIN_DRV_GRP(183, DRV_BASE1+0xa0, 20, 1),
193 MTK_PIN_DRV_GRP(184, DRV_BASE1+0xa0, 24, 1),
194 MTK_PIN_DRV_GRP(185, DRV_BASE1+0xa0, 28, 1),
195
196 MTK_PIN_DRV_GRP(186, DRV_BASE1+0xb0, 0, 2),
197 MTK_PIN_DRV_GRP(187, DRV_BASE1+0xb0, 0, 2),
198 MTK_PIN_DRV_GRP(188, DRV_BASE1+0xb0, 0, 2),
199 MTK_PIN_DRV_GRP(189, DRV_BASE1+0xb0, 0, 2),
200 MTK_PIN_DRV_GRP(190, DRV_BASE1+0xb0, 4, 1),
201 MTK_PIN_DRV_GRP(191, DRV_BASE1+0xb0, 8, 1),
202 MTK_PIN_DRV_GRP(192, DRV_BASE1+0xb0, 12, 1),
203
204 MTK_PIN_DRV_GRP(197, DRV_BASE1+0xb0, 16, 0),
205 MTK_PIN_DRV_GRP(198, DRV_BASE1+0xb0, 16, 0),
206 MTK_PIN_DRV_GRP(199, DRV_BASE1+0xb0, 20, 0),
207 MTK_PIN_DRV_GRP(200, DRV_BASE1+0xb0, 24, 0),
208 MTK_PIN_DRV_GRP(201, DRV_BASE1+0xb0, 16, 0),
209 MTK_PIN_DRV_GRP(202, DRV_BASE1+0xb0, 16, 0)
210};
211
212static const struct mtk_spec_pull_set spec_pupd[] = {
213 SPEC_PULL(0, PUPD_BASE1, 0, R0_BASE1, 9, R1_BASE1, 0),
214 SPEC_PULL(1, PUPD_BASE1, 1, R0_BASE1, 8, R1_BASE1, 1),
215 SPEC_PULL(2, PUPD_BASE1, 2, R0_BASE1, 7, R1_BASE1, 2),
216 SPEC_PULL(3, PUPD_BASE1, 3, R0_BASE1, 6, R1_BASE1, 3),
217 SPEC_PULL(4, PUPD_BASE1, 4, R0_BASE1, 1, R1_BASE1, 4),
218 SPEC_PULL(5, PUPD_BASE1, 5, R0_BASE1, 0, R1_BASE1, 5),
219 SPEC_PULL(6, PUPD_BASE1, 6, R0_BASE1, 5, R1_BASE1, 6),
220 SPEC_PULL(7, PUPD_BASE1, 7, R0_BASE1, 4, R1_BASE1, 7),
221 SPEC_PULL(8, PUPD_BASE1, 8, R0_BASE1, 3, R1_BASE1, 8),
222 SPEC_PULL(9, PUPD_BASE1, 9, R0_BASE1, 2, R1_BASE1, 9),
223 SPEC_PULL(89, PUPD_BASE2, 9, R0_BASE1, 18, R1_BASE2, 9),
224 SPEC_PULL(90, PUPD_BASE2, 10, R0_BASE1, 19, R1_BASE2, 10),
225 SPEC_PULL(91, PUPD_BASE2, 11, R0_BASE1, 23, R1_BASE2, 11),
226 SPEC_PULL(92, PUPD_BASE2, 12, R0_BASE1, 24, R1_BASE2, 12),
227 SPEC_PULL(93, PUPD_BASE2, 13, R0_BASE1, 25, R1_BASE2, 13),
228 SPEC_PULL(94, PUPD_BASE2, 14, R0_BASE1, 22, R1_BASE2, 14),
229 SPEC_PULL(95, PUPD_BASE2, 15, R0_BASE1, 20, R1_BASE2, 15),
230 SPEC_PULL(96, PUPD_BASE2+0x10, 0, R0_BASE1, 16, R1_BASE2+0x10, 0),
231 SPEC_PULL(97, PUPD_BASE2+0x10, 1, R0_BASE1, 21, R1_BASE2+0x10, 1),
232 SPEC_PULL(98, PUPD_BASE2+0x10, 2, R0_BASE1, 17, R1_BASE2+0x10, 2),
233 SPEC_PULL(197, PUPD_BASE1+0xc0, 5, R0_BASE1, 13, R1_BASE2+0xc0, 5),
234 SPEC_PULL(198, PUPD_BASE2+0xc0, 6, R0_BASE1, 14, R1_BASE2+0xc0, 6),
235 SPEC_PULL(199, PUPD_BASE2+0xc0, 7, R0_BASE1, 11, R1_BASE2+0xc0, 7),
236 SPEC_PULL(200, PUPD_BASE2+0xc0, 8, R0_BASE1, 10, R1_BASE2+0xc0, 8),
237 SPEC_PULL(201, PUPD_BASE2+0xc0, 9, R0_BASE1, 13, R1_BASE2+0xc0, 9),
238 SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10)
239};
240
241static int spec_pull_set(struct regmap *regmap, unsigned int pin,
242 unsigned char align, bool isup, unsigned int r1r0)
243{
244 unsigned int i;
245 unsigned int reg_pupd, reg_set_r0, reg_set_r1;
246 unsigned int reg_rst_r0, reg_rst_r1;
247 bool find = false;
248
249 for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) {
250 if (pin == spec_pupd[i].pin) {
251 find = true;
252 break;
253 }
254 }
255
256 if (!find)
257 return -EINVAL;
258
259 if (isup)
260 reg_pupd = spec_pupd[i].pupd_offset + align;
261 else
262 reg_pupd = spec_pupd[i].pupd_offset + (align << 1);
263
264 regmap_write(regmap, reg_pupd, spec_pupd[i].pupd_bit);
265
266 reg_set_r0 = spec_pupd[i].r0_offset + align;
267 reg_rst_r0 = spec_pupd[i].r0_offset + (align << 1);
268 reg_set_r1 = spec_pupd[i].r1_offset + align;
269 reg_rst_r1 = spec_pupd[i].r1_offset + (align << 1);
270
271 switch (r1r0) {
272 case MTK_PUPD_SET_R1R0_00:
273 regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);
274 regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);
275 break;
276 case MTK_PUPD_SET_R1R0_01:
277 regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);
278 regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);
279 break;
280 case MTK_PUPD_SET_R1R0_10:
281 regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);
282 regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);
283 break;
284 case MTK_PUPD_SET_R1R0_11:
285 regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);
286 regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);
287 break;
288 default:
289 return -EINVAL;
290 }
291
292 return 0;
293}
294
295static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
296 .pins = mtk_pins_mt8135,
297 .npins = ARRAY_SIZE(mtk_pins_mt8135),
298 .grp_desc = mt8135_drv_grp,
299 .n_grp_cls = ARRAY_SIZE(mt8135_drv_grp),
300 .pin_drv_grp = mt8135_pin_drv,
301 .n_pin_drv_grps = ARRAY_SIZE(mt8135_pin_drv),
302 .spec_pull_set = spec_pull_set,
303 .dir_offset = 0x0000,
304 .ies_offset = 0x0100,
305 .pullen_offset = 0x0200,
306 .smt_offset = 0x0300,
307 .pullsel_offset = 0x0400,
308 .dout_offset = 0x0800,
309 .din_offset = 0x0A00,
310 .pinmux_offset = 0x0C00,
311 .type1_start = 34,
312 .type1_end = 149,
313 .port_shf = 4,
314 .port_mask = 0xf,
315 .port_align = 4,
316 .eint_offsets = {
317 .name = "mt8135_eint",
318 .stat = 0x000,
319 .ack = 0x040,
320 .mask = 0x080,
321 .mask_set = 0x0c0,
322 .mask_clr = 0x100,
323 .sens = 0x140,
324 .sens_set = 0x180,
325 .sens_clr = 0x1c0,
326 .soft = 0x200,
327 .soft_set = 0x240,
328 .soft_clr = 0x280,
329 .pol = 0x300,
330 .pol_set = 0x340,
331 .pol_clr = 0x380,
332 .dom_en = 0x400,
333 .dbnc_ctrl = 0x500,
334 .dbnc_set = 0x600,
335 .dbnc_clr = 0x700,
336 .port_mask = 7,
337 .ports = 6,
338 },
339 .ap_num = 192,
340 .db_cnt = 16,
341};
342
343static int mt8135_pinctrl_probe(struct platform_device *pdev)
344{
345 return mtk_pctrl_init(pdev, &mt8135_pinctrl_data, NULL);
346}
347
348static const struct of_device_id mt8135_pctrl_match[] = {
349 {
350 .compatible = "mediatek,mt8135-pinctrl",
351 },
352 { }
353};
354
355static struct platform_driver mtk_pinctrl_driver = {
356 .probe = mt8135_pinctrl_probe,
357 .driver = {
358 .name = "mediatek-mt8135-pinctrl",
359 .of_match_table = mt8135_pctrl_match,
360 },
361};
362
363static int __init mtk_pinctrl_init(void)
364{
365 return platform_driver_register(&mtk_pinctrl_driver);
366}
367arch_initcall(mtk_pinctrl_init);
368
