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33#include <linux/module.h>
34
35#include "../comedi_pci.h"
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58#define PCI1760_OMB_REG(x) (0x0c + (x))
59#define PCI1760_IMB_REG(x) (0x1c + (x))
60#define PCI1760_INTCSR_REG(x) (0x38 + (x))
61#define PCI1760_INTCSR1_IRQ_ENA BIT(5)
62#define PCI1760_INTCSR2_OMB_IRQ BIT(0)
63#define PCI1760_INTCSR2_IMB_IRQ BIT(1)
64#define PCI1760_INTCSR2_IRQ_STATUS BIT(6)
65#define PCI1760_INTCSR2_IRQ_ASSERTED BIT(7)
66
67
68#define PCI1760_CMD_CLR_IMB2 0x00
69#define PCI1760_CMD_SET_DO 0x01
70#define PCI1760_CMD_GET_DO 0x02
71#define PCI1760_CMD_GET_STATUS 0x03
72#define PCI1760_CMD_GET_FW_VER 0x0e
73#define PCI1760_CMD_GET_HW_VER 0x0f
74#define PCI1760_CMD_SET_PWM_HI(x) (0x10 + (x) * 2)
75#define PCI1760_CMD_SET_PWM_LO(x) (0x11 + (x) * 2)
76#define PCI1760_CMD_SET_PWM_CNT(x) (0x14 + (x))
77#define PCI1760_CMD_ENA_PWM 0x1f
78#define PCI1760_CMD_ENA_FILT 0x20
79#define PCI1760_CMD_ENA_PAT_MATCH 0x21
80#define PCI1760_CMD_SET_PAT_MATCH 0x22
81#define PCI1760_CMD_ENA_RISE_EDGE 0x23
82#define PCI1760_CMD_ENA_FALL_EDGE 0x24
83#define PCI1760_CMD_ENA_CNT 0x28
84#define PCI1760_CMD_RST_CNT 0x29
85#define PCI1760_CMD_ENA_CNT_OFLOW 0x2a
86#define PCI1760_CMD_ENA_CNT_MATCH 0x2b
87#define PCI1760_CMD_SET_CNT_EDGE 0x2c
88#define PCI1760_CMD_GET_CNT 0x2f
89#define PCI1760_CMD_SET_HI_SAMP(x) (0x30 + (x))
90#define PCI1760_CMD_SET_LO_SAMP(x) (0x38 + (x))
91#define PCI1760_CMD_SET_CNT(x) (0x40 + (x))
92#define PCI1760_CMD_SET_CNT_MATCH(x) (0x48 + (x))
93#define PCI1760_CMD_GET_INT_FLAGS 0x60
94#define PCI1760_CMD_GET_INT_FLAGS_MATCH BIT(0)
95#define PCI1760_CMD_GET_INT_FLAGS_COS BIT(1)
96#define PCI1760_CMD_GET_INT_FLAGS_OFLOW BIT(2)
97#define PCI1760_CMD_GET_OS 0x61
98#define PCI1760_CMD_GET_CNT_STATUS 0x62
99
100#define PCI1760_CMD_TIMEOUT 250
101#define PCI1760_CMD_RETRIES 3
102
103#define PCI1760_PWM_TIMEBASE 100000
104
105static int pci1760_send_cmd(struct comedi_device *dev,
106 unsigned char cmd, unsigned short val)
107{
108 unsigned long timeout;
109
110
111 outb(val & 0xff, dev->iobase + PCI1760_OMB_REG(0));
112 outb((val >> 8) & 0xff, dev->iobase + PCI1760_OMB_REG(1));
113 outb(cmd, dev->iobase + PCI1760_OMB_REG(2));
114 outb(0, dev->iobase + PCI1760_OMB_REG(3));
115
116
117 timeout = jiffies + usecs_to_jiffies(PCI1760_CMD_TIMEOUT);
118 do {
119 if (inb(dev->iobase + PCI1760_IMB_REG(2)) == cmd) {
120
121 return inb(dev->iobase + PCI1760_IMB_REG(0)) |
122 (inb(dev->iobase + PCI1760_IMB_REG(1)) << 8);
123 }
124 cpu_relax();
125 } while (time_before(jiffies, timeout));
126
127 return -EBUSY;
128}
129
130static int pci1760_cmd(struct comedi_device *dev,
131 unsigned char cmd, unsigned short val)
132{
133 int repeats;
134 int ret;
135
136
137 if (inb(dev->iobase + PCI1760_IMB_REG(2)) == cmd) {
138 ret = pci1760_send_cmd(dev, PCI1760_CMD_CLR_IMB2, 0);
139 if (ret < 0) {
140
141 ret = pci1760_send_cmd(dev, PCI1760_CMD_CLR_IMB2, 0);
142 if (ret < 0)
143 return -ETIMEDOUT;
144 }
145 }
146
147
148 for (repeats = 0; repeats < PCI1760_CMD_RETRIES; repeats++) {
149 ret = pci1760_send_cmd(dev, cmd, val);
150 if (ret >= 0)
151 return ret;
152 }
153
154
155 return -ETIMEDOUT;
156}
157
158static int pci1760_di_insn_bits(struct comedi_device *dev,
159 struct comedi_subdevice *s,
160 struct comedi_insn *insn,
161 unsigned int *data)
162{
163 data[1] = inb(dev->iobase + PCI1760_IMB_REG(3));
164
165 return insn->n;
166}
167
168static int pci1760_do_insn_bits(struct comedi_device *dev,
169 struct comedi_subdevice *s,
170 struct comedi_insn *insn,
171 unsigned int *data)
172{
173 int ret;
174
175 if (comedi_dio_update_state(s, data)) {
176 ret = pci1760_cmd(dev, PCI1760_CMD_SET_DO, s->state);
177 if (ret < 0)
178 return ret;
179 }
180
181 data[1] = s->state;
182
183 return insn->n;
184}
185
186static int pci1760_pwm_ns_to_div(unsigned int flags, unsigned int ns)
187{
188 unsigned int divisor;
189
190 switch (flags) {
191 case CMDF_ROUND_NEAREST:
192 divisor = DIV_ROUND_CLOSEST(ns, PCI1760_PWM_TIMEBASE);
193 break;
194 case CMDF_ROUND_UP:
195 divisor = DIV_ROUND_UP(ns, PCI1760_PWM_TIMEBASE);
196 break;
197 case CMDF_ROUND_DOWN:
198 divisor = ns / PCI1760_PWM_TIMEBASE;
199 break;
200 default:
201 return -EINVAL;
202 }
203
204 if (divisor < 1)
205 divisor = 1;
206 if (divisor > 0xffff)
207 divisor = 0xffff;
208
209 return divisor;
210}
211
212static int pci1760_pwm_enable(struct comedi_device *dev,
213 unsigned int chan, bool enable)
214{
215 int ret;
216
217 ret = pci1760_cmd(dev, PCI1760_CMD_GET_STATUS, PCI1760_CMD_ENA_PWM);
218 if (ret < 0)
219 return ret;
220
221 if (enable)
222 ret |= BIT(chan);
223 else
224 ret &= ~BIT(chan);
225
226 return pci1760_cmd(dev, PCI1760_CMD_ENA_PWM, ret);
227}
228
229static int pci1760_pwm_insn_config(struct comedi_device *dev,
230 struct comedi_subdevice *s,
231 struct comedi_insn *insn,
232 unsigned int *data)
233{
234 unsigned int chan = CR_CHAN(insn->chanspec);
235 int hi_div;
236 int lo_div;
237 int ret;
238
239 switch (data[0]) {
240 case INSN_CONFIG_ARM:
241 ret = pci1760_pwm_enable(dev, chan, false);
242 if (ret < 0)
243 return ret;
244
245 if (data[1] > 0xffff)
246 return -EINVAL;
247 ret = pci1760_cmd(dev, PCI1760_CMD_SET_PWM_CNT(chan), data[1]);
248 if (ret < 0)
249 return ret;
250
251 ret = pci1760_pwm_enable(dev, chan, true);
252 if (ret < 0)
253 return ret;
254 break;
255 case INSN_CONFIG_DISARM:
256 ret = pci1760_pwm_enable(dev, chan, false);
257 if (ret < 0)
258 return ret;
259 break;
260 case INSN_CONFIG_PWM_OUTPUT:
261 ret = pci1760_pwm_enable(dev, chan, false);
262 if (ret < 0)
263 return ret;
264
265 hi_div = pci1760_pwm_ns_to_div(data[1], data[2]);
266 lo_div = pci1760_pwm_ns_to_div(data[3], data[4]);
267 if (hi_div < 0 || lo_div < 0)
268 return -EINVAL;
269 if ((hi_div * PCI1760_PWM_TIMEBASE) != data[2] ||
270 (lo_div * PCI1760_PWM_TIMEBASE) != data[4]) {
271 data[2] = hi_div * PCI1760_PWM_TIMEBASE;
272 data[4] = lo_div * PCI1760_PWM_TIMEBASE;
273 return -EAGAIN;
274 }
275 ret = pci1760_cmd(dev, PCI1760_CMD_SET_PWM_HI(chan), hi_div);
276 if (ret < 0)
277 return ret;
278 ret = pci1760_cmd(dev, PCI1760_CMD_SET_PWM_LO(chan), lo_div);
279 if (ret < 0)
280 return ret;
281 break;
282 case INSN_CONFIG_GET_PWM_OUTPUT:
283 hi_div = pci1760_cmd(dev, PCI1760_CMD_GET_STATUS,
284 PCI1760_CMD_SET_PWM_HI(chan));
285 lo_div = pci1760_cmd(dev, PCI1760_CMD_GET_STATUS,
286 PCI1760_CMD_SET_PWM_LO(chan));
287 if (hi_div < 0 || lo_div < 0)
288 return -ETIMEDOUT;
289
290 data[1] = hi_div * PCI1760_PWM_TIMEBASE;
291 data[2] = lo_div * PCI1760_PWM_TIMEBASE;
292 break;
293 case INSN_CONFIG_GET_PWM_STATUS:
294 ret = pci1760_cmd(dev, PCI1760_CMD_GET_STATUS,
295 PCI1760_CMD_ENA_PWM);
296 if (ret < 0)
297 return ret;
298
299 data[1] = (ret & BIT(chan)) ? 1 : 0;
300 break;
301 default:
302 return -EINVAL;
303 }
304
305 return insn->n;
306}
307
308static void pci1760_reset(struct comedi_device *dev)
309{
310 int i;
311
312
313 outb(0, dev->iobase + PCI1760_INTCSR_REG(0));
314 outb(0, dev->iobase + PCI1760_INTCSR_REG(1));
315 outb(0, dev->iobase + PCI1760_INTCSR_REG(3));
316
317
318 pci1760_cmd(dev, PCI1760_CMD_ENA_CNT, 0);
319
320
321 pci1760_cmd(dev, PCI1760_CMD_ENA_CNT_OFLOW, 0);
322
323
324 pci1760_cmd(dev, PCI1760_CMD_ENA_CNT_MATCH, 0);
325
326
327 for (i = 0; i < 8; i++) {
328 pci1760_cmd(dev, PCI1760_CMD_SET_CNT_MATCH(i), 0x8000);
329 pci1760_cmd(dev, PCI1760_CMD_SET_CNT(i), 0x0000);
330 }
331
332
333 pci1760_cmd(dev, PCI1760_CMD_RST_CNT, 0xff);
334
335
336 pci1760_cmd(dev, PCI1760_CMD_SET_CNT_EDGE, 0);
337
338
339 pci1760_cmd(dev, PCI1760_CMD_ENA_FILT, 0);
340
341
342 pci1760_cmd(dev, PCI1760_CMD_ENA_PAT_MATCH, 0);
343
344
345 pci1760_cmd(dev, PCI1760_CMD_SET_PAT_MATCH, 0);
346}
347
348static int pci1760_auto_attach(struct comedi_device *dev,
349 unsigned long context)
350{
351 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
352 struct comedi_subdevice *s;
353 int ret;
354
355 ret = comedi_pci_enable(dev);
356 if (ret)
357 return ret;
358 dev->iobase = pci_resource_start(pcidev, 0);
359
360 pci1760_reset(dev);
361
362 ret = comedi_alloc_subdevices(dev, 4);
363 if (ret)
364 return ret;
365
366
367 s = &dev->subdevices[0];
368 s->type = COMEDI_SUBD_DI;
369 s->subdev_flags = SDF_READABLE;
370 s->n_chan = 8;
371 s->maxdata = 1;
372 s->range_table = &range_digital;
373 s->insn_bits = pci1760_di_insn_bits;
374
375
376 s = &dev->subdevices[1];
377 s->type = COMEDI_SUBD_DO;
378 s->subdev_flags = SDF_WRITABLE;
379 s->n_chan = 8;
380 s->maxdata = 1;
381 s->range_table = &range_digital;
382 s->insn_bits = pci1760_do_insn_bits;
383
384
385 ret = pci1760_cmd(dev, PCI1760_CMD_GET_DO, 0);
386 if (ret < 0)
387 return ret;
388 s->state = ret;
389
390
391 s = &dev->subdevices[2];
392 s->type = COMEDI_SUBD_PWM;
393 s->subdev_flags = SDF_PWM_COUNTER;
394 s->n_chan = 2;
395 s->insn_config = pci1760_pwm_insn_config;
396
397
398 s = &dev->subdevices[3];
399 s->type = COMEDI_SUBD_UNUSED;
400
401 return 0;
402}
403
404static struct comedi_driver pci1760_driver = {
405 .driver_name = "adv_pci1760",
406 .module = THIS_MODULE,
407 .auto_attach = pci1760_auto_attach,
408 .detach = comedi_pci_detach,
409};
410
411static int pci1760_pci_probe(struct pci_dev *dev,
412 const struct pci_device_id *id)
413{
414 return comedi_pci_auto_config(dev, &pci1760_driver, id->driver_data);
415}
416
417static const struct pci_device_id pci1760_pci_table[] = {
418 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1760) },
419 { 0 }
420};
421MODULE_DEVICE_TABLE(pci, pci1760_pci_table);
422
423static struct pci_driver pci1760_pci_driver = {
424 .name = "adv_pci1760",
425 .id_table = pci1760_pci_table,
426 .probe = pci1760_pci_probe,
427 .remove = comedi_pci_auto_unconfig,
428};
429module_comedi_pci_driver(pci1760_driver, pci1760_pci_driver);
430
431MODULE_AUTHOR("Comedi http://www.comedi.org");
432MODULE_DESCRIPTION("Comedi driver for Advantech PCI-1760");
433MODULE_LICENSE("GPL");
434