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62#include <linux/module.h>
63#include <linux/delay.h>
64#include <linux/interrupt.h>
65#include <linux/kernel.h>
66#include <linux/types.h>
67
68#include "../comedi_pci.h"
69
70#include "s626.h"
71
72struct s626_buffer_dma {
73 dma_addr_t physical_base;
74 void *logical_base;
75};
76
77struct s626_private {
78 uint8_t ai_cmd_running;
79 unsigned int ai_sample_timer;
80
81 int ai_convert_count;
82 unsigned int ai_convert_timer;
83
84 uint16_t counter_int_enabs;
85
86 uint8_t adc_items;
87 struct s626_buffer_dma rps_buf;
88
89 struct s626_buffer_dma ana_buf;
90
91 uint32_t *dac_wbuf;
92
93 uint16_t dacpol;
94 uint8_t trim_setpoint[12];
95 uint32_t i2c_adrs;
96
97};
98
99
100#define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
101#define S626_OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
102
103
104
105
106
107static void s626_mc_enable(struct comedi_device *dev,
108 unsigned int cmd, unsigned int reg)
109{
110 unsigned int val = (cmd << 16) | cmd;
111
112 mmiowb();
113 writel(val, dev->mmio + reg);
114}
115
116static void s626_mc_disable(struct comedi_device *dev,
117 unsigned int cmd, unsigned int reg)
118{
119 writel(cmd << 16, dev->mmio + reg);
120 mmiowb();
121}
122
123static bool s626_mc_test(struct comedi_device *dev,
124 unsigned int cmd, unsigned int reg)
125{
126 unsigned int val;
127
128 val = readl(dev->mmio + reg);
129
130 return (val & cmd) ? true : false;
131}
132
133#define S626_BUGFIX_STREG(REGADRS) ((REGADRS) - 4)
134
135
136#define S626_VECTPORT(VECTNUM) (S626_P_TSL2 + ((VECTNUM) << 2))
137
138static const struct comedi_lrange s626_range_table = {
139 2, {
140 BIP_RANGE(5),
141 BIP_RANGE(10)
142 }
143};
144
145
146
147
148static void s626_debi_transfer(struct comedi_device *dev)
149{
150 static const int timeout = 10000;
151 int i;
152
153
154 s626_mc_enable(dev, S626_MC2_UPLD_DEBI, S626_P_MC2);
155
156
157
158
159
160 for (i = 0; i < timeout; i++) {
161 if (s626_mc_test(dev, S626_MC2_UPLD_DEBI, S626_P_MC2))
162 break;
163 udelay(1);
164 }
165 if (i == timeout)
166 dev_err(dev->class_dev,
167 "Timeout while uploading to DEBI control register\n");
168
169
170 for (i = 0; i < timeout; i++) {
171 if (!(readl(dev->mmio + S626_P_PSR) & S626_PSR_DEBI_S))
172 break;
173 udelay(1);
174 }
175 if (i == timeout)
176 dev_err(dev->class_dev, "DEBI transfer timeout\n");
177}
178
179
180
181
182static uint16_t s626_debi_read(struct comedi_device *dev, uint16_t addr)
183{
184
185 writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
186
187
188 s626_debi_transfer(dev);
189
190 return readl(dev->mmio + S626_P_DEBIAD);
191}
192
193
194
195
196static void s626_debi_write(struct comedi_device *dev, uint16_t addr,
197 uint16_t wdata)
198{
199
200 writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
201 writel(wdata, dev->mmio + S626_P_DEBIAD);
202
203
204 s626_debi_transfer(dev);
205}
206
207
208
209
210
211
212static void s626_debi_replace(struct comedi_device *dev, unsigned int addr,
213 unsigned int mask, unsigned int wdata)
214{
215 unsigned int val;
216
217 addr &= 0xffff;
218 writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
219 s626_debi_transfer(dev);
220
221 writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
222 val = readl(dev->mmio + S626_P_DEBIAD);
223 val &= mask;
224 val |= wdata;
225 writel(val & 0xffff, dev->mmio + S626_P_DEBIAD);
226 s626_debi_transfer(dev);
227}
228
229
230
231static int s626_i2c_handshake_eoc(struct comedi_device *dev,
232 struct comedi_subdevice *s,
233 struct comedi_insn *insn,
234 unsigned long context)
235{
236 bool status;
237
238 status = s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
239 if (status)
240 return 0;
241 return -EBUSY;
242}
243
244static int s626_i2c_handshake(struct comedi_device *dev, uint32_t val)
245{
246 unsigned int ctrl;
247 int ret;
248
249
250 writel(val, dev->mmio + S626_P_I2CCTRL);
251
252
253
254
255
256 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
257 ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
258 if (ret)
259 return ret;
260
261
262 do {
263 ctrl = readl(dev->mmio + S626_P_I2CCTRL);
264 } while ((ctrl & (S626_I2C_BUSY | S626_I2C_ERR)) == S626_I2C_BUSY);
265
266
267 return ctrl & S626_I2C_ERR;
268}
269
270
271static uint8_t s626_i2c_read(struct comedi_device *dev, uint8_t addr)
272{
273 struct s626_private *devpriv = dev->private;
274
275
276
277
278
279
280
281 if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
282 devpriv->i2c_adrs) |
283 S626_I2C_B1(S626_I2C_ATTRSTOP, addr) |
284 S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
285
286 return 0;
287
288
289
290
291
292
293
294 if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
295 (devpriv->i2c_adrs | 1)) |
296 S626_I2C_B1(S626_I2C_ATTRSTOP, 0) |
297 S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
298
299 return 0;
300
301 return (readl(dev->mmio + S626_P_I2CCTRL) >> 16) & 0xff;
302}
303
304
305
306
307static const uint8_t s626_trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
308
309
310static const uint8_t s626_trimadrs[] = {
311 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63
312};
313
314enum {
315 s626_send_dac_wait_not_mc1_a2out,
316 s626_send_dac_wait_ssr_af2_out,
317 s626_send_dac_wait_fb_buffer2_msb_00,
318 s626_send_dac_wait_fb_buffer2_msb_ff
319};
320
321static int s626_send_dac_eoc(struct comedi_device *dev,
322 struct comedi_subdevice *s,
323 struct comedi_insn *insn,
324 unsigned long context)
325{
326 unsigned int status;
327
328 switch (context) {
329 case s626_send_dac_wait_not_mc1_a2out:
330 status = readl(dev->mmio + S626_P_MC1);
331 if (!(status & S626_MC1_A2OUT))
332 return 0;
333 break;
334 case s626_send_dac_wait_ssr_af2_out:
335 status = readl(dev->mmio + S626_P_SSR);
336 if (status & S626_SSR_AF2_OUT)
337 return 0;
338 break;
339 case s626_send_dac_wait_fb_buffer2_msb_00:
340 status = readl(dev->mmio + S626_P_FB_BUFFER2);
341 if (!(status & 0xff000000))
342 return 0;
343 break;
344 case s626_send_dac_wait_fb_buffer2_msb_ff:
345 status = readl(dev->mmio + S626_P_FB_BUFFER2);
346 if (status & 0xff000000)
347 return 0;
348 break;
349 default:
350 return -EINVAL;
351 }
352 return -EBUSY;
353}
354
355
356
357
358
359
360static int s626_send_dac(struct comedi_device *dev, uint32_t val)
361{
362 struct s626_private *devpriv = dev->private;
363 int ret;
364
365
366
367
368
369
370
371
372
373
374
375
376
377 s626_debi_write(dev, S626_LP_DACPOL, devpriv->dacpol);
378
379
380
381
382
383 *devpriv->dac_wbuf = val;
384
385
386
387
388
389
390
391 s626_mc_enable(dev, S626_MC1_A2OUT, S626_P_MC1);
392
393
394
395
396
397
398
399
400 writel(S626_ISR_AFOU, dev->mmio + S626_P_ISR);
401
402
403
404
405
406
407
408
409 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
410 s626_send_dac_wait_not_mc1_a2out);
411 if (ret) {
412 dev_err(dev->class_dev, "DMA transfer timeout\n");
413 return ret;
414 }
415
416
417
418
419
420
421
422
423
424 writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2,
425 dev->mmio + S626_VECTPORT(0));
426
427
428
429
430
431
432
433
434 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
435 s626_send_dac_wait_ssr_af2_out);
436 if (ret) {
437 dev_err(dev->class_dev,
438 "TSL timeout waiting for slot 1 to execute\n");
439 return ret;
440 }
441
442
443
444
445
446
447
448
449 writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS,
450 dev->mmio + S626_VECTPORT(0));
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472 if (readl(dev->mmio + S626_P_FB_BUFFER2) & 0xff000000) {
473
474
475
476
477
478
479
480 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
481 s626_send_dac_wait_fb_buffer2_msb_00);
482 if (ret) {
483 dev_err(dev->class_dev,
484 "TSL timeout waiting for slot 0 to execute\n");
485 return ret;
486 }
487 }
488
489
490
491
492
493
494
495
496
497 writel(S626_RSD3 | S626_SIB_A2 | S626_EOS,
498 dev->mmio + S626_VECTPORT(0));
499
500
501
502
503
504
505 ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
506 s626_send_dac_wait_fb_buffer2_msb_ff);
507 if (ret) {
508 dev_err(dev->class_dev,
509 "TSL timeout waiting for slot 0 to execute\n");
510 return ret;
511 }
512 return 0;
513}
514
515
516
517
518static int s626_set_dac(struct comedi_device *dev,
519 uint16_t chan, int16_t dacdata)
520{
521 struct s626_private *devpriv = dev->private;
522 uint16_t signmask;
523 uint32_t ws_image;
524 uint32_t val;
525
526
527
528
529 signmask = 1 << chan;
530 if (dacdata < 0) {
531 dacdata = -dacdata;
532 devpriv->dacpol |= signmask;
533 } else {
534 devpriv->dacpol &= ~signmask;
535 }
536
537
538 if ((uint16_t)dacdata > 0x1FFF)
539 dacdata = 0x1FFF;
540
541
542
543
544
545
546
547
548
549
550
551
552
553 ws_image = (chan & 2) ? S626_WS1 : S626_WS2;
554
555 writel(S626_XSD2 | S626_XFIFO_1 | ws_image,
556 dev->mmio + S626_VECTPORT(2));
557
558 writel(S626_XSD2 | S626_XFIFO_0 | ws_image,
559 dev->mmio + S626_VECTPORT(3));
560
561 writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3,
562 dev->mmio + S626_VECTPORT(4));
563
564 writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS,
565 dev->mmio + S626_VECTPORT(5));
566
567
568
569
570
571
572
573
574 val = 0x0F000000;
575
576 val |= 0x00004000;
577
578 val |= ((uint32_t)(chan & 1) << 15);
579
580 val |= (uint32_t)dacdata;
581 return s626_send_dac(dev, val);
582}
583
584static int s626_write_trim_dac(struct comedi_device *dev,
585 uint8_t logical_chan, uint8_t dac_data)
586{
587 struct s626_private *devpriv = dev->private;
588 uint32_t chan;
589
590
591
592
593
594 devpriv->trim_setpoint[logical_chan] = (uint8_t)dac_data;
595
596
597 chan = s626_trimchan[logical_chan];
598
599
600
601
602
603
604
605
606 writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3,
607 dev->mmio + S626_VECTPORT(2));
608
609 writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3,
610 dev->mmio + S626_VECTPORT(3));
611
612 writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1,
613 dev->mmio + S626_VECTPORT(4));
614
615 writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS,
616 dev->mmio + S626_VECTPORT(5));
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631 return s626_send_dac(dev, (chan << 8) | dac_data);
632}
633
634static int s626_load_trim_dacs(struct comedi_device *dev)
635{
636 uint8_t i;
637 int ret;
638
639
640 for (i = 0; i < ARRAY_SIZE(s626_trimchan); i++) {
641 ret = s626_write_trim_dac(dev, i,
642 s626_i2c_read(dev, s626_trimadrs[i]));
643 if (ret)
644 return ret;
645 }
646 return 0;
647}
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663static void s626_set_latch_source(struct comedi_device *dev,
664 unsigned int chan, uint16_t value)
665{
666 s626_debi_replace(dev, S626_LP_CRB(chan),
667 ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_LATCHSRC),
668 S626_SET_CRB_LATCHSRC(value));
669}
670
671
672
673
674static void s626_preload(struct comedi_device *dev,
675 unsigned int chan, uint32_t value)
676{
677 s626_debi_write(dev, S626_LP_CNTR(chan), value);
678 s626_debi_write(dev, S626_LP_CNTR(chan) + 2, value >> 16);
679}
680
681
682
683
684
685
686static void s626_reset_cap_flags(struct comedi_device *dev,
687 unsigned int chan)
688{
689 uint16_t set;
690
691 set = S626_SET_CRB_INTRESETCMD(1);
692 if (chan < 3)
693 set |= S626_SET_CRB_INTRESET_A(1);
694 else
695 set |= S626_SET_CRB_INTRESET_B(1);
696
697 s626_debi_replace(dev, S626_LP_CRB(chan), ~S626_CRBMSK_INTCTRL, set);
698}
699
700
701
702
703
704
705
706static void s626_set_mode_a(struct comedi_device *dev,
707 unsigned int chan, uint16_t setup,
708 uint16_t disable_int_src)
709{
710 struct s626_private *devpriv = dev->private;
711 uint16_t cra;
712 uint16_t crb;
713 unsigned int cntsrc, clkmult, clkpol;
714
715
716
717 cra = S626_SET_CRA_LOADSRC_A(S626_GET_STD_LOADSRC(setup));
718
719 cra |= S626_SET_CRA_INDXSRC_A(S626_GET_STD_INDXSRC(setup));
720
721
722 crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_A(1);
723
724 crb |= S626_SET_CRB_CLKENAB_A(S626_GET_STD_CLKENAB(setup));
725
726
727 if (!disable_int_src)
728 cra |= S626_SET_CRA_INTSRC_A(S626_GET_STD_INTSRC(setup));
729
730
731 clkpol = S626_GET_STD_CLKPOL(setup);
732 switch (S626_GET_STD_ENCMODE(setup)) {
733 case S626_ENCMODE_EXTENDER:
734
735
736 case S626_ENCMODE_TIMER:
737
738 cntsrc = S626_CNTSRC_SYSCLK;
739
740 cntsrc |= clkpol;
741
742 clkpol = 1;
743
744 clkmult = S626_CLKMULT_1X;
745 break;
746 default:
747
748 cntsrc = S626_CNTSRC_ENCODER;
749
750
751 clkmult = S626_GET_STD_CLKMULT(setup);
752 if (clkmult == S626_CLKMULT_SPECIAL)
753 clkmult = S626_CLKMULT_1X;
754 break;
755 }
756 cra |= S626_SET_CRA_CNTSRC_A(cntsrc) | S626_SET_CRA_CLKPOL_A(clkpol) |
757 S626_SET_CRA_CLKMULT_A(clkmult);
758
759
760
761
762
763 if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
764 cra |= S626_SET_CRA_INDXPOL_A(S626_GET_STD_INDXPOL(setup));
765
766
767
768
769
770 if (disable_int_src)
771 devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
772 S626_INDXMASK(chan));
773
774
775
776
777
778 s626_debi_replace(dev, S626_LP_CRA(chan),
779 S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B, cra);
780 s626_debi_replace(dev, S626_LP_CRB(chan),
781 ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), crb);
782}
783
784static void s626_set_mode_b(struct comedi_device *dev,
785 unsigned int chan, uint16_t setup,
786 uint16_t disable_int_src)
787{
788 struct s626_private *devpriv = dev->private;
789 uint16_t cra;
790 uint16_t crb;
791 unsigned int cntsrc, clkmult, clkpol;
792
793
794
795 cra = S626_SET_CRA_INDXSRC_B(S626_GET_STD_INDXSRC(setup));
796
797
798 crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_B(1);
799
800 crb |= S626_SET_CRB_CLKENAB_B(S626_GET_STD_CLKENAB(setup));
801
802 crb |= S626_SET_CRB_LOADSRC_B(S626_GET_STD_LOADSRC(setup));
803
804
805 if (!disable_int_src)
806 crb |= S626_SET_CRB_INTSRC_B(S626_GET_STD_INTSRC(setup));
807
808
809 clkpol = S626_GET_STD_CLKPOL(setup);
810 switch (S626_GET_STD_ENCMODE(setup)) {
811 case S626_ENCMODE_TIMER:
812
813 cntsrc = S626_CNTSRC_SYSCLK;
814
815 cntsrc |= clkpol;
816
817 clkpol = 1;
818
819 clkmult = S626_CLKMULT_1X;
820 break;
821 case S626_ENCMODE_EXTENDER:
822
823 cntsrc = S626_CNTSRC_SYSCLK;
824
825 cntsrc |= clkpol;
826
827 clkpol = 1;
828
829 clkmult = S626_CLKMULT_SPECIAL;
830 break;
831 default:
832
833 cntsrc = S626_CNTSRC_ENCODER;
834
835
836 clkmult = S626_GET_STD_CLKMULT(setup);
837 if (clkmult == S626_CLKMULT_SPECIAL)
838 clkmult = S626_CLKMULT_1X;
839 break;
840 }
841 cra |= S626_SET_CRA_CNTSRC_B(cntsrc);
842 crb |= S626_SET_CRB_CLKPOL_B(clkpol) | S626_SET_CRB_CLKMULT_B(clkmult);
843
844
845
846
847
848 if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
849 crb |= S626_SET_CRB_INDXPOL_B(S626_GET_STD_INDXPOL(setup));
850
851
852
853
854
855 if (disable_int_src)
856 devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
857 S626_INDXMASK(chan));
858
859
860
861
862
863 s626_debi_replace(dev, S626_LP_CRA(chan),
864 ~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B), cra);
865 s626_debi_replace(dev, S626_LP_CRB(chan),
866 S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, crb);
867}
868
869static void s626_set_mode(struct comedi_device *dev,
870 unsigned int chan,
871 uint16_t setup, uint16_t disable_int_src)
872{
873 if (chan < 3)
874 s626_set_mode_a(dev, chan, setup, disable_int_src);
875 else
876 s626_set_mode_b(dev, chan, setup, disable_int_src);
877}
878
879
880
881
882static void s626_set_enable(struct comedi_device *dev,
883 unsigned int chan, uint16_t enab)
884{
885 unsigned int mask = S626_CRBMSK_INTCTRL;
886 unsigned int set;
887
888 if (chan < 3) {
889 mask |= S626_CRBMSK_CLKENAB_A;
890 set = S626_SET_CRB_CLKENAB_A(enab);
891 } else {
892 mask |= S626_CRBMSK_CLKENAB_B;
893 set = S626_SET_CRB_CLKENAB_B(enab);
894 }
895 s626_debi_replace(dev, S626_LP_CRB(chan), ~mask, set);
896}
897
898
899
900
901
902
903static void s626_set_load_trig(struct comedi_device *dev,
904 unsigned int chan, uint16_t trig)
905{
906 uint16_t reg;
907 uint16_t mask;
908 uint16_t set;
909
910 if (chan < 3) {
911 reg = S626_LP_CRA(chan);
912 mask = S626_CRAMSK_LOADSRC_A;
913 set = S626_SET_CRA_LOADSRC_A(trig);
914 } else {
915 reg = S626_LP_CRB(chan);
916 mask = S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL;
917 set = S626_SET_CRB_LOADSRC_B(trig);
918 }
919 s626_debi_replace(dev, reg, ~mask, set);
920}
921
922
923
924
925
926
927static void s626_set_int_src(struct comedi_device *dev,
928 unsigned int chan, uint16_t int_source)
929{
930 struct s626_private *devpriv = dev->private;
931 uint16_t cra_reg = S626_LP_CRA(chan);
932 uint16_t crb_reg = S626_LP_CRB(chan);
933
934 if (chan < 3) {
935
936 s626_debi_replace(dev, crb_reg, ~S626_CRBMSK_INTCTRL,
937 S626_SET_CRB_INTRESETCMD(1) |
938 S626_SET_CRB_INTRESET_A(1));
939
940
941 s626_debi_replace(dev, cra_reg, ~S626_CRAMSK_INTSRC_A,
942 S626_SET_CRA_INTSRC_A(int_source));
943 } else {
944 uint16_t crb;
945
946
947 crb = s626_debi_read(dev, crb_reg);
948 crb &= ~S626_CRBMSK_INTCTRL;
949
950
951 s626_debi_write(dev, crb_reg,
952 crb | S626_SET_CRB_INTRESETCMD(1) |
953 S626_SET_CRB_INTRESET_B(1));
954
955
956 s626_debi_write(dev, crb_reg,
957 (crb & ~S626_CRBMSK_INTSRC_B) |
958 S626_SET_CRB_INTSRC_B(int_source));
959 }
960
961
962 devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
963 S626_INDXMASK(chan));
964 switch (int_source) {
965 case 0:
966 default:
967 break;
968 case 1:
969 devpriv->counter_int_enabs |= S626_OVERMASK(chan);
970 break;
971 case 2:
972 devpriv->counter_int_enabs |= S626_INDXMASK(chan);
973 break;
974 case 3:
975 devpriv->counter_int_enabs |= (S626_OVERMASK(chan) |
976 S626_INDXMASK(chan));
977 break;
978 }
979}
980
981
982
983
984static void s626_pulse_index(struct comedi_device *dev,
985 unsigned int chan)
986{
987 if (chan < 3) {
988 uint16_t cra;
989
990 cra = s626_debi_read(dev, S626_LP_CRA(chan));
991
992
993 s626_debi_write(dev, S626_LP_CRA(chan),
994 (cra ^ S626_CRAMSK_INDXPOL_A));
995 s626_debi_write(dev, S626_LP_CRA(chan), cra);
996 } else {
997 uint16_t crb;
998
999 crb = s626_debi_read(dev, S626_LP_CRB(chan));
1000 crb &= ~S626_CRBMSK_INTCTRL;
1001
1002
1003 s626_debi_write(dev, S626_LP_CRB(chan),
1004 (crb ^ S626_CRBMSK_INDXPOL_B));
1005 s626_debi_write(dev, S626_LP_CRB(chan), crb);
1006 }
1007}
1008
1009static unsigned int s626_ai_reg_to_uint(unsigned int data)
1010{
1011 return ((data >> 18) & 0x3fff) ^ 0x2000;
1012}
1013
1014static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
1015{
1016 unsigned int group = chan / 16;
1017 unsigned int mask = 1 << (chan - (16 * group));
1018 unsigned int status;
1019
1020
1021 status = s626_debi_read(dev, S626_LP_RDEDGSEL(group));
1022 s626_debi_write(dev, S626_LP_WREDGSEL(group), mask | status);
1023
1024
1025 status = s626_debi_read(dev, S626_LP_RDINTSEL(group));
1026 s626_debi_write(dev, S626_LP_WRINTSEL(group), mask | status);
1027
1028
1029 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_EDCAP);
1030
1031
1032 status = s626_debi_read(dev, S626_LP_RDCAPSEL(group));
1033 s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask | status);
1034
1035 return 0;
1036}
1037
1038static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
1039 unsigned int mask)
1040{
1041
1042 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1043
1044
1045 s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask);
1046
1047 return 0;
1048}
1049
1050static int s626_dio_clear_irq(struct comedi_device *dev)
1051{
1052 unsigned int group;
1053
1054
1055 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1056
1057
1058 for (group = 0; group < S626_DIO_BANKS; group++)
1059 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
1060
1061 return 0;
1062}
1063
1064static void s626_handle_dio_interrupt(struct comedi_device *dev,
1065 uint16_t irqbit, uint8_t group)
1066{
1067 struct s626_private *devpriv = dev->private;
1068 struct comedi_subdevice *s = dev->read_subdev;
1069 struct comedi_cmd *cmd = &s->async->cmd;
1070
1071 s626_dio_reset_irq(dev, group, irqbit);
1072
1073 if (devpriv->ai_cmd_running) {
1074
1075 if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 &&
1076 cmd->start_src == TRIG_EXT) {
1077
1078 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1079
1080 if (cmd->scan_begin_src == TRIG_EXT)
1081 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1082 }
1083 if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 &&
1084 cmd->scan_begin_src == TRIG_EXT) {
1085
1086 s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1087
1088 if (cmd->convert_src == TRIG_EXT) {
1089 devpriv->ai_convert_count = cmd->chanlist_len;
1090
1091 s626_dio_set_irq(dev, cmd->convert_arg);
1092 }
1093
1094 if (cmd->convert_src == TRIG_TIMER) {
1095 devpriv->ai_convert_count = cmd->chanlist_len;
1096 s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS);
1097 }
1098 }
1099 if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 &&
1100 cmd->convert_src == TRIG_EXT) {
1101
1102 s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1103
1104 devpriv->ai_convert_count--;
1105 if (devpriv->ai_convert_count > 0)
1106 s626_dio_set_irq(dev, cmd->convert_arg);
1107 }
1108 }
1109}
1110
1111static void s626_check_dio_interrupts(struct comedi_device *dev)
1112{
1113 uint16_t irqbit;
1114 uint8_t group;
1115
1116 for (group = 0; group < S626_DIO_BANKS; group++) {
1117
1118 irqbit = s626_debi_read(dev, S626_LP_RDCAPFLG(group));
1119
1120
1121 if (irqbit) {
1122 s626_handle_dio_interrupt(dev, irqbit, group);
1123 return;
1124 }
1125 }
1126}
1127
1128static void s626_check_counter_interrupts(struct comedi_device *dev)
1129{
1130 struct s626_private *devpriv = dev->private;
1131 struct comedi_subdevice *s = dev->read_subdev;
1132 struct comedi_async *async = s->async;
1133 struct comedi_cmd *cmd = &async->cmd;
1134 uint16_t irqbit;
1135
1136
1137 irqbit = s626_debi_read(dev, S626_LP_RDMISC2);
1138
1139
1140 if (irqbit & S626_IRQ_COINT1A) {
1141
1142 s626_reset_cap_flags(dev, 0);
1143 }
1144 if (irqbit & S626_IRQ_COINT2A) {
1145
1146 s626_reset_cap_flags(dev, 1);
1147 }
1148 if (irqbit & S626_IRQ_COINT3A) {
1149
1150 s626_reset_cap_flags(dev, 2);
1151 }
1152 if (irqbit & S626_IRQ_COINT1B) {
1153
1154 s626_reset_cap_flags(dev, 3);
1155 }
1156 if (irqbit & S626_IRQ_COINT2B) {
1157
1158 s626_reset_cap_flags(dev, 4);
1159
1160 if (devpriv->ai_convert_count > 0) {
1161 devpriv->ai_convert_count--;
1162 if (devpriv->ai_convert_count == 0)
1163 s626_set_enable(dev, 4, S626_CLKENAB_INDEX);
1164
1165 if (cmd->convert_src == TRIG_TIMER) {
1166
1167 s626_mc_enable(dev, S626_MC2_ADC_RPS,
1168 S626_P_MC2);
1169 }
1170 }
1171 }
1172 if (irqbit & S626_IRQ_COINT3B) {
1173
1174 s626_reset_cap_flags(dev, 5);
1175
1176 if (cmd->scan_begin_src == TRIG_TIMER) {
1177
1178 s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1179 }
1180
1181 if (cmd->convert_src == TRIG_TIMER) {
1182 devpriv->ai_convert_count = cmd->chanlist_len;
1183 s626_set_enable(dev, 4, S626_CLKENAB_ALWAYS);
1184 }
1185 }
1186}
1187
1188static bool s626_handle_eos_interrupt(struct comedi_device *dev)
1189{
1190 struct s626_private *devpriv = dev->private;
1191 struct comedi_subdevice *s = dev->read_subdev;
1192 struct comedi_async *async = s->async;
1193 struct comedi_cmd *cmd = &async->cmd;
1194
1195
1196
1197
1198
1199 uint32_t *readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1200 int i;
1201
1202
1203 for (i = 0; i < cmd->chanlist_len; i++) {
1204 unsigned short tempdata;
1205
1206
1207
1208
1209
1210 tempdata = s626_ai_reg_to_uint(*readaddr);
1211 readaddr++;
1212
1213 comedi_buf_write_samples(s, &tempdata, 1);
1214 }
1215
1216 if (cmd->stop_src == TRIG_COUNT && async->scans_done >= cmd->stop_arg)
1217 async->events |= COMEDI_CB_EOA;
1218
1219 if (async->events & COMEDI_CB_CANCEL_MASK)
1220 devpriv->ai_cmd_running = 0;
1221
1222 if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT)
1223 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1224
1225 comedi_handle_events(dev, s);
1226
1227 return !devpriv->ai_cmd_running;
1228}
1229
1230static irqreturn_t s626_irq_handler(int irq, void *d)
1231{
1232 struct comedi_device *dev = d;
1233 unsigned long flags;
1234 uint32_t irqtype, irqstatus;
1235
1236 if (!dev->attached)
1237 return IRQ_NONE;
1238
1239 spin_lock_irqsave(&dev->spinlock, flags);
1240
1241
1242 irqstatus = readl(dev->mmio + S626_P_IER);
1243
1244
1245 irqtype = readl(dev->mmio + S626_P_ISR);
1246
1247
1248 writel(0, dev->mmio + S626_P_IER);
1249
1250
1251 writel(irqtype, dev->mmio + S626_P_ISR);
1252
1253 switch (irqtype) {
1254 case S626_IRQ_RPS1:
1255 if (s626_handle_eos_interrupt(dev))
1256 irqstatus = 0;
1257 break;
1258 case S626_IRQ_GPIO3:
1259
1260 s626_check_dio_interrupts(dev);
1261 s626_check_counter_interrupts(dev);
1262 break;
1263 }
1264
1265
1266 writel(irqstatus, dev->mmio + S626_P_IER);
1267
1268 spin_unlock_irqrestore(&dev->spinlock, flags);
1269 return IRQ_HANDLED;
1270}
1271
1272
1273
1274
1275static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl)
1276{
1277 struct s626_private *devpriv = dev->private;
1278 struct comedi_subdevice *s = dev->read_subdev;
1279 struct comedi_cmd *cmd = &s->async->cmd;
1280 uint32_t *rps;
1281 uint32_t jmp_adrs;
1282 uint16_t i;
1283 uint16_t n;
1284 uint32_t local_ppl;
1285
1286
1287 s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1288
1289
1290 rps = (uint32_t *)devpriv->rps_buf.logical_base;
1291
1292
1293 writel((uint32_t)devpriv->rps_buf.physical_base,
1294 dev->mmio + S626_P_RPSADDR1);
1295
1296
1297 if (cmd->scan_begin_src != TRIG_FOLLOW) {
1298
1299 *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1300 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1301 }
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1313 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1314 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1315
1316 *rps++ = S626_GSEL_BIPOLAR5V;
1317 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1318
1319
1320 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1321
1322 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1323
1324
1325
1326
1327
1328
1329 for (devpriv->adc_items = 0; devpriv->adc_items < 16;
1330 devpriv->adc_items++) {
1331
1332
1333
1334
1335
1336
1337 local_ppl = (*ppl << 8) | (*ppl & 0x10 ? S626_GSEL_BIPOLAR5V :
1338 S626_GSEL_BIPOLAR10V);
1339
1340
1341
1342 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1343 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1344
1345 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1346 *rps++ = local_ppl;
1347
1348 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1349
1350 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1351
1352 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1353
1354 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1355
1356 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL;
1357 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1358
1359 *rps++ = local_ppl;
1360
1361 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1362
1363 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1364
1365 *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1366
1367
1368
1369
1370
1371
1372
1373
1374 jmp_adrs =
1375 (uint32_t)devpriv->rps_buf.physical_base +
1376 (uint32_t)((unsigned long)rps -
1377 (unsigned long)devpriv->
1378 rps_buf.logical_base);
1379 for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) {
1380 jmp_adrs += 8;
1381
1382 *rps++ = S626_RPS_JUMP;
1383 *rps++ = jmp_adrs;
1384 }
1385
1386 if (cmd->convert_src != TRIG_NOW) {
1387
1388 *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1389 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1390 }
1391
1392
1393 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1394 *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1395 *rps++ = S626_RPS_NOP;
1396
1397
1398 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1399 *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1400
1401
1402
1403
1404
1405
1406 *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;
1407
1408
1409 *rps++ = S626_RPS_STREG |
1410 (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1411 *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1412 (devpriv->adc_items << 2);
1413
1414
1415
1416
1417
1418 if (*ppl++ & S626_EOPL) {
1419 devpriv->adc_items++;
1420 break;
1421 }
1422 }
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432 for (n = 0; n < (2 * S626_RPSCLK_PER_US); n++)
1433 *rps++ = S626_RPS_NOP;
1434
1435
1436
1437
1438
1439
1440 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1441 *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1442 *rps++ = S626_RPS_NOP;
1443
1444 *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1445 *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1446
1447
1448
1449
1450
1451 *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;
1452
1453
1454 *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1455 *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1456 (devpriv->adc_items << 2);
1457
1458
1459
1460
1461
1462
1463 if (devpriv->ai_cmd_running == 1)
1464 *rps++ = S626_RPS_IRQ;
1465
1466
1467 *rps++ = S626_RPS_JUMP;
1468 *rps++ = (uint32_t)devpriv->rps_buf.physical_base;
1469
1470
1471}
1472
1473static int s626_ai_eoc(struct comedi_device *dev,
1474 struct comedi_subdevice *s,
1475 struct comedi_insn *insn,
1476 unsigned long context)
1477{
1478 unsigned int status;
1479
1480 status = readl(dev->mmio + S626_P_PSR);
1481 if (status & S626_PSR_GPIO2)
1482 return 0;
1483 return -EBUSY;
1484}
1485
1486static int s626_ai_insn_read(struct comedi_device *dev,
1487 struct comedi_subdevice *s,
1488 struct comedi_insn *insn,
1489 unsigned int *data)
1490{
1491 uint16_t chan = CR_CHAN(insn->chanspec);
1492 uint16_t range = CR_RANGE(insn->chanspec);
1493 uint16_t adc_spec = 0;
1494 uint32_t gpio_image;
1495 uint32_t tmp;
1496 int ret;
1497 int n;
1498
1499
1500
1501
1502
1503 if (range == 0)
1504 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR5V);
1505 else
1506 adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR10V);
1507
1508
1509 s626_debi_write(dev, S626_LP_GSEL, adc_spec);
1510
1511
1512 s626_debi_write(dev, S626_LP_ISEL, adc_spec);
1513
1514 for (n = 0; n < insn->n; n++) {
1515
1516 udelay(10);
1517
1518
1519 gpio_image = readl(dev->mmio + S626_P_GPIO);
1520
1521 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1522
1523 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1524 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1525
1526 writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1527
1528
1529
1530
1531
1532
1533
1534
1535 ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
1536 if (ret)
1537 return ret;
1538
1539
1540 if (n != 0) {
1541 tmp = readl(dev->mmio + S626_P_FB_BUFFER1);
1542 data[n - 1] = s626_ai_reg_to_uint(tmp);
1543 }
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554 udelay(4);
1555 }
1556
1557
1558
1559
1560
1561 gpio_image = readl(dev->mmio + S626_P_GPIO);
1562
1563 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1564
1565 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1566 writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1567
1568 writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1569
1570
1571
1572
1573 ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
1574 if (ret)
1575 return ret;
1576
1577
1578
1579
1580 if (n != 0) {
1581 tmp = readl(dev->mmio + S626_P_FB_BUFFER1);
1582 data[n - 1] = s626_ai_reg_to_uint(tmp);
1583 }
1584
1585 return n;
1586}
1587
1588static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
1589{
1590 int n;
1591
1592 for (n = 0; n < cmd->chanlist_len; n++) {
1593 if (CR_RANGE(cmd->chanlist[n]) == 0)
1594 ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_5V;
1595 else
1596 ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_10V;
1597 }
1598 if (n != 0)
1599 ppl[n - 1] |= S626_EOPL;
1600
1601 return n;
1602}
1603
1604static int s626_ai_inttrig(struct comedi_device *dev,
1605 struct comedi_subdevice *s,
1606 unsigned int trig_num)
1607{
1608 struct comedi_cmd *cmd = &s->async->cmd;
1609
1610 if (trig_num != cmd->start_arg)
1611 return -EINVAL;
1612
1613
1614 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1615
1616 s->async->inttrig = NULL;
1617
1618 return 1;
1619}
1620
1621
1622
1623
1624
1625
1626
1627
1628static int s626_ns_to_timer(unsigned int *nanosec, unsigned int flags)
1629{
1630 int divider, base;
1631
1632 base = 500;
1633
1634 switch (flags & CMDF_ROUND_MASK) {
1635 case CMDF_ROUND_NEAREST:
1636 default:
1637 divider = DIV_ROUND_CLOSEST(*nanosec, base);
1638 break;
1639 case CMDF_ROUND_DOWN:
1640 divider = (*nanosec) / base;
1641 break;
1642 case CMDF_ROUND_UP:
1643 divider = DIV_ROUND_UP(*nanosec, base);
1644 break;
1645 }
1646
1647 *nanosec = base * divider;
1648 return divider - 1;
1649}
1650
1651static void s626_timer_load(struct comedi_device *dev,
1652 unsigned int chan, int tick)
1653{
1654 uint16_t setup =
1655
1656 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
1657
1658 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
1659
1660 S626_SET_STD_ENCMODE(S626_ENCMODE_TIMER) |
1661
1662 S626_SET_STD_CLKPOL(S626_CNTDIR_DOWN) |
1663
1664 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
1665
1666 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
1667 uint16_t value_latchsrc = S626_LATCHSRC_A_INDXA;
1668
1669
1670 s626_set_mode(dev, chan, setup, false);
1671
1672
1673 s626_preload(dev, chan, tick);
1674
1675
1676
1677
1678
1679 s626_set_load_trig(dev, chan, 0);
1680 s626_pulse_index(dev, chan);
1681
1682
1683 s626_set_load_trig(dev, chan, 1);
1684
1685
1686 s626_set_int_src(dev, chan, S626_INTSRC_OVER);
1687
1688 s626_set_latch_source(dev, chan, value_latchsrc);
1689
1690}
1691
1692
1693static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1694{
1695 struct s626_private *devpriv = dev->private;
1696 uint8_t ppl[16];
1697 struct comedi_cmd *cmd = &s->async->cmd;
1698 int tick;
1699
1700 if (devpriv->ai_cmd_running) {
1701 dev_err(dev->class_dev,
1702 "s626_ai_cmd: Another ai_cmd is running\n");
1703 return -EBUSY;
1704 }
1705
1706 writel(0, dev->mmio + S626_P_IER);
1707
1708
1709 writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, dev->mmio + S626_P_ISR);
1710
1711
1712 s626_dio_clear_irq(dev);
1713
1714
1715
1716 devpriv->ai_cmd_running = 0;
1717
1718 s626_ai_load_polllist(ppl, cmd);
1719 devpriv->ai_cmd_running = 1;
1720 devpriv->ai_convert_count = 0;
1721
1722 switch (cmd->scan_begin_src) {
1723 case TRIG_FOLLOW:
1724 break;
1725 case TRIG_TIMER:
1726
1727
1728
1729
1730 tick = s626_ns_to_timer(&cmd->scan_begin_arg, cmd->flags);
1731
1732
1733 s626_timer_load(dev, 5, tick);
1734 s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS);
1735 break;
1736 case TRIG_EXT:
1737
1738 if (cmd->start_src != TRIG_EXT)
1739 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1740 break;
1741 }
1742
1743 switch (cmd->convert_src) {
1744 case TRIG_NOW:
1745 break;
1746 case TRIG_TIMER:
1747
1748
1749
1750
1751 tick = s626_ns_to_timer(&cmd->convert_arg, cmd->flags);
1752
1753
1754 s626_timer_load(dev, 4, tick);
1755 s626_set_enable(dev, 4, S626_CLKENAB_INDEX);
1756 break;
1757 case TRIG_EXT:
1758
1759 if (cmd->scan_begin_src != TRIG_EXT &&
1760 cmd->start_src == TRIG_EXT)
1761 s626_dio_set_irq(dev, cmd->convert_arg);
1762 break;
1763 }
1764
1765 s626_reset_adc(dev, ppl);
1766
1767 switch (cmd->start_src) {
1768 case TRIG_NOW:
1769
1770
1771
1772
1773 s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1774 s->async->inttrig = NULL;
1775 break;
1776 case TRIG_EXT:
1777
1778 s626_dio_set_irq(dev, cmd->start_arg);
1779 s->async->inttrig = NULL;
1780 break;
1781 case TRIG_INT:
1782 s->async->inttrig = s626_ai_inttrig;
1783 break;
1784 }
1785
1786
1787 writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, dev->mmio + S626_P_IER);
1788
1789 return 0;
1790}
1791
1792static int s626_ai_cmdtest(struct comedi_device *dev,
1793 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1794{
1795 int err = 0;
1796 unsigned int arg;
1797
1798
1799
1800 err |= comedi_check_trigger_src(&cmd->start_src,
1801 TRIG_NOW | TRIG_INT | TRIG_EXT);
1802 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
1803 TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW);
1804 err |= comedi_check_trigger_src(&cmd->convert_src,
1805 TRIG_TIMER | TRIG_EXT | TRIG_NOW);
1806 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
1807 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
1808
1809 if (err)
1810 return 1;
1811
1812
1813
1814 err |= comedi_check_trigger_is_unique(cmd->start_src);
1815 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
1816 err |= comedi_check_trigger_is_unique(cmd->convert_src);
1817 err |= comedi_check_trigger_is_unique(cmd->stop_src);
1818
1819
1820
1821 if (err)
1822 return 2;
1823
1824
1825
1826 switch (cmd->start_src) {
1827 case TRIG_NOW:
1828 case TRIG_INT:
1829 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
1830 break;
1831 case TRIG_EXT:
1832 err |= comedi_check_trigger_arg_max(&cmd->start_arg, 39);
1833 break;
1834 }
1835
1836 if (cmd->scan_begin_src == TRIG_EXT)
1837 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 39);
1838 if (cmd->convert_src == TRIG_EXT)
1839 err |= comedi_check_trigger_arg_max(&cmd->convert_arg, 39);
1840
1841#define S626_MAX_SPEED 200000
1842#define S626_MIN_SPEED 2000000000
1843
1844 if (cmd->scan_begin_src == TRIG_TIMER) {
1845 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
1846 S626_MAX_SPEED);
1847 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
1848 S626_MIN_SPEED);
1849 } else {
1850
1851
1852
1853
1854
1855
1856 }
1857 if (cmd->convert_src == TRIG_TIMER) {
1858 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
1859 S626_MAX_SPEED);
1860 err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
1861 S626_MIN_SPEED);
1862 } else {
1863
1864
1865
1866
1867 }
1868
1869 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
1870 cmd->chanlist_len);
1871
1872 if (cmd->stop_src == TRIG_COUNT)
1873 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
1874 else
1875 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
1876
1877 if (err)
1878 return 3;
1879
1880
1881
1882 if (cmd->scan_begin_src == TRIG_TIMER) {
1883 arg = cmd->scan_begin_arg;
1884 s626_ns_to_timer(&arg, cmd->flags);
1885 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
1886 }
1887
1888 if (cmd->convert_src == TRIG_TIMER) {
1889 arg = cmd->convert_arg;
1890 s626_ns_to_timer(&arg, cmd->flags);
1891 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, arg);
1892
1893 if (cmd->scan_begin_src == TRIG_TIMER) {
1894 arg = cmd->convert_arg * cmd->scan_end_arg;
1895 err |= comedi_check_trigger_arg_min(&cmd->
1896 scan_begin_arg,
1897 arg);
1898 }
1899 }
1900
1901 if (err)
1902 return 4;
1903
1904 return 0;
1905}
1906
1907static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1908{
1909 struct s626_private *devpriv = dev->private;
1910
1911
1912 s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1913
1914
1915 writel(0, dev->mmio + S626_P_IER);
1916
1917 devpriv->ai_cmd_running = 0;
1918
1919 return 0;
1920}
1921
1922static int s626_ao_insn_write(struct comedi_device *dev,
1923 struct comedi_subdevice *s,
1924 struct comedi_insn *insn,
1925 unsigned int *data)
1926{
1927 unsigned int chan = CR_CHAN(insn->chanspec);
1928 int i;
1929
1930 for (i = 0; i < insn->n; i++) {
1931 int16_t dacdata = (int16_t)data[i];
1932 int ret;
1933
1934 dacdata -= (0x1fff);
1935
1936 ret = s626_set_dac(dev, chan, dacdata);
1937 if (ret)
1938 return ret;
1939
1940 s->readback[chan] = data[i];
1941 }
1942
1943 return insn->n;
1944}
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954static void s626_dio_init(struct comedi_device *dev)
1955{
1956 uint16_t group;
1957
1958
1959 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1960
1961
1962 for (group = 0; group < S626_DIO_BANKS; group++) {
1963
1964 s626_debi_write(dev, S626_LP_WRINTSEL(group), 0);
1965
1966 s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
1967
1968 s626_debi_write(dev, S626_LP_WREDGSEL(group), 0);
1969
1970 s626_debi_write(dev, S626_LP_WRDOUT(group), 0);
1971 }
1972}
1973
1974static int s626_dio_insn_bits(struct comedi_device *dev,
1975 struct comedi_subdevice *s,
1976 struct comedi_insn *insn,
1977 unsigned int *data)
1978{
1979 unsigned long group = (unsigned long)s->private;
1980
1981 if (comedi_dio_update_state(s, data))
1982 s626_debi_write(dev, S626_LP_WRDOUT(group), s->state);
1983
1984 data[1] = s626_debi_read(dev, S626_LP_RDDIN(group));
1985
1986 return insn->n;
1987}
1988
1989static int s626_dio_insn_config(struct comedi_device *dev,
1990 struct comedi_subdevice *s,
1991 struct comedi_insn *insn,
1992 unsigned int *data)
1993{
1994 unsigned long group = (unsigned long)s->private;
1995 int ret;
1996
1997 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
1998 if (ret)
1999 return ret;
2000
2001 s626_debi_write(dev, S626_LP_WRDOUT(group), s->io_bits);
2002
2003 return insn->n;
2004}
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015static int s626_enc_insn_config(struct comedi_device *dev,
2016 struct comedi_subdevice *s,
2017 struct comedi_insn *insn, unsigned int *data)
2018{
2019 unsigned int chan = CR_CHAN(insn->chanspec);
2020 uint16_t setup =
2021
2022 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2023
2024 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2025
2026 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2027
2028 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2029
2030 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2031
2032 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2033
2034
2035 uint16_t value_latchsrc = S626_LATCHSRC_AB_READ;
2036 uint16_t enab = S626_CLKENAB_ALWAYS;
2037
2038
2039
2040 s626_set_mode(dev, chan, setup, true);
2041 s626_preload(dev, chan, data[0]);
2042 s626_pulse_index(dev, chan);
2043 s626_set_latch_source(dev, chan, value_latchsrc);
2044 s626_set_enable(dev, chan, (enab != 0));
2045
2046 return insn->n;
2047}
2048
2049static int s626_enc_insn_read(struct comedi_device *dev,
2050 struct comedi_subdevice *s,
2051 struct comedi_insn *insn,
2052 unsigned int *data)
2053{
2054 unsigned int chan = CR_CHAN(insn->chanspec);
2055 uint16_t cntr_latch_reg = S626_LP_CNTR(chan);
2056 int i;
2057
2058 for (i = 0; i < insn->n; i++) {
2059 unsigned int val;
2060
2061
2062
2063
2064
2065 val = s626_debi_read(dev, cntr_latch_reg);
2066 val |= (s626_debi_read(dev, cntr_latch_reg + 2) << 16);
2067 data[i] = val;
2068 }
2069
2070 return insn->n;
2071}
2072
2073static int s626_enc_insn_write(struct comedi_device *dev,
2074 struct comedi_subdevice *s,
2075 struct comedi_insn *insn, unsigned int *data)
2076{
2077 unsigned int chan = CR_CHAN(insn->chanspec);
2078
2079
2080 s626_preload(dev, chan, data[0]);
2081
2082
2083
2084
2085
2086 s626_set_load_trig(dev, chan, 0);
2087 s626_pulse_index(dev, chan);
2088 s626_set_load_trig(dev, chan, 2);
2089
2090 return 1;
2091}
2092
2093static void s626_write_misc2(struct comedi_device *dev, uint16_t new_image)
2094{
2095 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WENABLE);
2096 s626_debi_write(dev, S626_LP_WRMISC2, new_image);
2097 s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WDISABLE);
2098}
2099
2100static void s626_counters_init(struct comedi_device *dev)
2101{
2102 int chan;
2103 uint16_t setup =
2104
2105 S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2106
2107 S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2108
2109 S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2110
2111 S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2112
2113 S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2114
2115 S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2116
2117
2118
2119
2120 for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
2121 s626_set_mode(dev, chan, setup, true);
2122 s626_set_int_src(dev, chan, 0);
2123 s626_reset_cap_flags(dev, chan);
2124 s626_set_enable(dev, chan, S626_CLKENAB_ALWAYS);
2125 }
2126}
2127
2128static int s626_allocate_dma_buffers(struct comedi_device *dev)
2129{
2130 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2131 struct s626_private *devpriv = dev->private;
2132 void *addr;
2133 dma_addr_t appdma;
2134
2135 addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2136 if (!addr)
2137 return -ENOMEM;
2138 devpriv->ana_buf.logical_base = addr;
2139 devpriv->ana_buf.physical_base = appdma;
2140
2141 addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2142 if (!addr)
2143 return -ENOMEM;
2144 devpriv->rps_buf.logical_base = addr;
2145 devpriv->rps_buf.physical_base = appdma;
2146
2147 return 0;
2148}
2149
2150static void s626_free_dma_buffers(struct comedi_device *dev)
2151{
2152 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2153 struct s626_private *devpriv = dev->private;
2154
2155 if (!devpriv)
2156 return;
2157
2158 if (devpriv->rps_buf.logical_base)
2159 pci_free_consistent(pcidev, S626_DMABUF_SIZE,
2160 devpriv->rps_buf.logical_base,
2161 devpriv->rps_buf.physical_base);
2162 if (devpriv->ana_buf.logical_base)
2163 pci_free_consistent(pcidev, S626_DMABUF_SIZE,
2164 devpriv->ana_buf.logical_base,
2165 devpriv->ana_buf.physical_base);
2166}
2167
2168static int s626_initialize(struct comedi_device *dev)
2169{
2170 struct s626_private *devpriv = dev->private;
2171 dma_addr_t phys_buf;
2172 uint16_t chan;
2173 int i;
2174 int ret;
2175
2176
2177 s626_mc_enable(dev, S626_MC1_DEBI | S626_MC1_AUDIO | S626_MC1_I2C,
2178 S626_P_MC1);
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188 writel(S626_DEBI_CFG_SLAVE16 |
2189 (S626_DEBI_TOUT << S626_DEBI_CFG_TOUT_BIT) | S626_DEBI_SWAP |
2190 S626_DEBI_CFG_INTEL, dev->mmio + S626_P_DEBICFG);
2191
2192
2193 writel(S626_DEBI_PAGE_DISABLE, dev->mmio + S626_P_DEBIPAGE);
2194
2195
2196 writel(S626_GPIO_BASE | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
2197
2198
2199 devpriv->i2c_adrs = 0xA0;
2200
2201
2202
2203
2204
2205 writel(S626_I2C_CLKSEL | S626_I2C_ABORT,
2206 dev->mmio + S626_P_I2CSTAT);
2207 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2208 ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
2209 if (ret)
2210 return ret;
2211
2212
2213
2214
2215
2216 for (i = 0; i < 2; i++) {
2217 writel(S626_I2C_CLKSEL, dev->mmio + S626_P_I2CSTAT);
2218 s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2219 ret = comedi_timeout(dev, NULL,
2220 NULL, s626_i2c_handshake_eoc, 0);
2221 if (ret)
2222 return ret;
2223 }
2224
2225
2226
2227
2228
2229
2230
2231 writel(S626_ACON2_INIT, dev->mmio + S626_P_ACON2);
2232
2233
2234
2235
2236
2237
2238
2239 writel(S626_RSD1 | S626_SIB_A1, dev->mmio + S626_P_TSL1);
2240 writel(S626_RSD1 | S626_SIB_A1 | S626_EOS,
2241 dev->mmio + S626_P_TSL1 + 4);
2242
2243
2244 writel(S626_ACON1_ADCSTART, dev->mmio + S626_P_ACON1);
2245
2246
2247
2248
2249
2250
2251 writel((uint32_t)devpriv->rps_buf.physical_base,
2252 dev->mmio + S626_P_RPSADDR1);
2253
2254 writel(0, dev->mmio + S626_P_RPSPAGE1);
2255
2256 writel(0, dev->mmio + S626_P_RPS1_TOUT);
2257
2258#if 0
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268 {
2269 struct comedi_subdevice *s = dev->read_subdev;
2270 uint8_t poll_list;
2271 uint16_t adc_data;
2272 uint16_t start_val;
2273 uint16_t index;
2274 unsigned int data[16];
2275
2276
2277 poll_list = S626_EOPL;
2278 s626_reset_adc(dev, &poll_list);
2279
2280
2281 s626_ai_rinsn(dev, s, NULL, data);
2282 start_val = data[0];
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294 for (index = 0; index < 500; index++) {
2295 s626_ai_rinsn(dev, s, NULL, data);
2296 adc_data = data[0];
2297 if (adc_data != start_val)
2298 break;
2299 }
2300 }
2301#endif
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312 writel(0, dev->mmio + S626_P_PCI_BT_A);
2313
2314
2315
2316
2317
2318
2319
2320 phys_buf = devpriv->ana_buf.physical_base +
2321 (S626_DAC_WDMABUF_OS * sizeof(uint32_t));
2322 writel((uint32_t)phys_buf, dev->mmio + S626_P_BASEA2_OUT);
2323 writel((uint32_t)(phys_buf + sizeof(uint32_t)),
2324 dev->mmio + S626_P_PROTA2_OUT);
2325
2326
2327
2328
2329
2330 devpriv->dac_wbuf = (uint32_t *)devpriv->ana_buf.logical_base +
2331 S626_DAC_WDMABUF_OS;
2332
2333
2334
2335
2336
2337
2338
2339 writel(8, dev->mmio + S626_P_PAGEA2_OUT);
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354 writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS,
2355 dev->mmio + S626_VECTPORT(0));
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367 writel(S626_LF_A2, dev->mmio + S626_VECTPORT(1));
2368
2369
2370 writel(S626_ACON1_DACSTART, dev->mmio + S626_P_ACON1);
2371
2372
2373
2374
2375
2376
2377 s626_load_trim_dacs(dev);
2378 ret = s626_load_trim_dacs(dev);
2379 if (ret)
2380 return ret;
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394 for (chan = 0; chan < S626_DAC_CHANNELS; chan++) {
2395 ret = s626_set_dac(dev, chan, 0);
2396 if (ret)
2397 return ret;
2398 }
2399
2400
2401 s626_counters_init(dev);
2402
2403
2404
2405
2406
2407
2408
2409 s626_write_misc2(dev, (s626_debi_read(dev, S626_LP_RDMISC2) &
2410 S626_MISC2_BATT_ENABLE));
2411
2412
2413 s626_dio_init(dev);
2414
2415 return 0;
2416}
2417
2418static int s626_auto_attach(struct comedi_device *dev,
2419 unsigned long context_unused)
2420{
2421 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2422 struct s626_private *devpriv;
2423 struct comedi_subdevice *s;
2424 int ret;
2425
2426 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
2427 if (!devpriv)
2428 return -ENOMEM;
2429
2430 ret = comedi_pci_enable(dev);
2431 if (ret)
2432 return ret;
2433
2434 dev->mmio = pci_ioremap_bar(pcidev, 0);
2435 if (!dev->mmio)
2436 return -ENOMEM;
2437
2438
2439 writel(0, dev->mmio + S626_P_IER);
2440
2441
2442 writel(S626_MC1_SOFT_RESET, dev->mmio + S626_P_MC1);
2443
2444
2445
2446 ret = s626_allocate_dma_buffers(dev);
2447 if (ret)
2448 return ret;
2449
2450 if (pcidev->irq) {
2451 ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED,
2452 dev->board_name, dev);
2453
2454 if (ret == 0)
2455 dev->irq = pcidev->irq;
2456 }
2457
2458 ret = comedi_alloc_subdevices(dev, 6);
2459 if (ret)
2460 return ret;
2461
2462 s = &dev->subdevices[0];
2463
2464 s->type = COMEDI_SUBD_AI;
2465 s->subdev_flags = SDF_READABLE | SDF_DIFF;
2466 s->n_chan = S626_ADC_CHANNELS;
2467 s->maxdata = 0x3fff;
2468 s->range_table = &s626_range_table;
2469 s->len_chanlist = S626_ADC_CHANNELS;
2470 s->insn_read = s626_ai_insn_read;
2471 if (dev->irq) {
2472 dev->read_subdev = s;
2473 s->subdev_flags |= SDF_CMD_READ;
2474 s->do_cmd = s626_ai_cmd;
2475 s->do_cmdtest = s626_ai_cmdtest;
2476 s->cancel = s626_ai_cancel;
2477 }
2478
2479 s = &dev->subdevices[1];
2480
2481 s->type = COMEDI_SUBD_AO;
2482 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2483 s->n_chan = S626_DAC_CHANNELS;
2484 s->maxdata = 0x3fff;
2485 s->range_table = &range_bipolar10;
2486 s->insn_write = s626_ao_insn_write;
2487
2488 ret = comedi_alloc_subdev_readback(s);
2489 if (ret)
2490 return ret;
2491
2492 s = &dev->subdevices[2];
2493
2494 s->type = COMEDI_SUBD_DIO;
2495 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2496 s->n_chan = 16;
2497 s->maxdata = 1;
2498 s->io_bits = 0xffff;
2499 s->private = (void *)0;
2500 s->range_table = &range_digital;
2501 s->insn_config = s626_dio_insn_config;
2502 s->insn_bits = s626_dio_insn_bits;
2503
2504 s = &dev->subdevices[3];
2505
2506 s->type = COMEDI_SUBD_DIO;
2507 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2508 s->n_chan = 16;
2509 s->maxdata = 1;
2510 s->io_bits = 0xffff;
2511 s->private = (void *)1;
2512 s->range_table = &range_digital;
2513 s->insn_config = s626_dio_insn_config;
2514 s->insn_bits = s626_dio_insn_bits;
2515
2516 s = &dev->subdevices[4];
2517
2518 s->type = COMEDI_SUBD_DIO;
2519 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2520 s->n_chan = 16;
2521 s->maxdata = 1;
2522 s->io_bits = 0xffff;
2523 s->private = (void *)2;
2524 s->range_table = &range_digital;
2525 s->insn_config = s626_dio_insn_config;
2526 s->insn_bits = s626_dio_insn_bits;
2527
2528 s = &dev->subdevices[5];
2529
2530 s->type = COMEDI_SUBD_COUNTER;
2531 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
2532 s->n_chan = S626_ENCODER_CHANNELS;
2533 s->maxdata = 0xffffff;
2534 s->range_table = &range_unknown;
2535 s->insn_config = s626_enc_insn_config;
2536 s->insn_read = s626_enc_insn_read;
2537 s->insn_write = s626_enc_insn_write;
2538
2539 return s626_initialize(dev);
2540}
2541
2542static void s626_detach(struct comedi_device *dev)
2543{
2544 struct s626_private *devpriv = dev->private;
2545
2546 if (devpriv) {
2547
2548 devpriv->ai_cmd_running = 0;
2549
2550 if (dev->mmio) {
2551
2552
2553 writel(0, dev->mmio + S626_P_IER);
2554
2555 writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1,
2556 dev->mmio + S626_P_ISR);
2557
2558
2559 s626_write_misc2(dev, 0);
2560
2561
2562 writel(S626_MC1_SHUTDOWN, dev->mmio + S626_P_MC1);
2563 writel(S626_ACON1_BASE, dev->mmio + S626_P_ACON1);
2564 }
2565 }
2566 comedi_pci_detach(dev);
2567 s626_free_dma_buffers(dev);
2568}
2569
2570static struct comedi_driver s626_driver = {
2571 .driver_name = "s626",
2572 .module = THIS_MODULE,
2573 .auto_attach = s626_auto_attach,
2574 .detach = s626_detach,
2575};
2576
2577static int s626_pci_probe(struct pci_dev *dev,
2578 const struct pci_device_id *id)
2579{
2580 return comedi_pci_auto_config(dev, &s626_driver, id->driver_data);
2581}
2582
2583
2584
2585
2586
2587
2588static const struct pci_device_id s626_pci_table[] = {
2589 { PCI_DEVICE_SUB(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA7146,
2590 0x6000, 0x0272) },
2591 { 0 }
2592};
2593MODULE_DEVICE_TABLE(pci, s626_pci_table);
2594
2595static struct pci_driver s626_pci_driver = {
2596 .name = "s626",
2597 .id_table = s626_pci_table,
2598 .probe = s626_pci_probe,
2599 .remove = comedi_pci_auto_unconfig,
2600};
2601module_comedi_pci_driver(s626_driver, s626_pci_driver);
2602
2603MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
2604MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
2605MODULE_LICENSE("GPL");
2606