1/* 2 * Copyright (C) 2014 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10#ifndef __LINUX_MTD_SPI_NOR_H 11#define __LINUX_MTD_SPI_NOR_H 12 13#include <linux/bitops.h> 14#include <linux/mtd/cfi.h> 15#include <linux/mtd/mtd.h> 16 17/* 18 * Manufacturer IDs 19 * 20 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID. 21 * Sometimes these are the same as CFI IDs, but sometimes they aren't. 22 */ 23#define SNOR_MFR_ATMEL CFI_MFR_ATMEL 24#define SNOR_MFR_GIGADEVICE 0xc8 25#define SNOR_MFR_INTEL CFI_MFR_INTEL 26#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */ 27#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX 28#define SNOR_MFR_SPANSION CFI_MFR_AMD 29#define SNOR_MFR_SST CFI_MFR_SST 30#define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ 31 32/* 33 * Note on opcode nomenclature: some opcodes have a format like 34 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number 35 * of I/O lines used for the opcode, address, and data (respectively). The 36 * FUNCTION has an optional suffix of '4', to represent an opcode which 37 * requires a 4-byte (32-bit) address. 38 */ 39 40/* Flash opcodes. */ 41#define SPINOR_OP_WREN 0x06 /* Write enable */ 42#define SPINOR_OP_RDSR 0x05 /* Read status register */ 43#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */ 44#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */ 45#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ 46#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */ 47#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */ 48#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */ 49#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ 50#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ 51#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ 52#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ 53#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ 54#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ 55#define SPINOR_OP_RDCR 0x35 /* Read configuration register */ 56#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ 57#define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */ 58#define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */ 59 60/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ 61#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */ 62#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */ 63#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */ 64#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */ 65#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */ 66#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ 67 68/* Used for SST flashes only. */ 69#define SPINOR_OP_BP 0x02 /* Byte program */ 70#define SPINOR_OP_WRDI 0x04 /* Write disable */ 71#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ 72 73#define GLOBAL_BLKPROT_UNLK 0x98 /* Clear global write protection bits */ 74 75/* Used for Macronix and Winbond flashes. */ 76#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ 77#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ 78 79/* Used for Spansion flashes only. */ 80#define SPINOR_OP_BRWR 0x17 /* Bank register write */ 81#define SPINOR_OP_BRRD 0x16 /* Bank register read */ 82 83/* Used for Micron flashes only. */ 84#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ 85#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ 86 87/* Status Register bits. */ 88#define SR_WIP BIT(0) /* Write in progress */ 89#define SR_WEL BIT(1) /* Write enable latch */ 90/* meaning of other SR_* bits may differ between vendors */ 91#define SR_BP0 BIT(2) /* Block protect 0 */ 92#define SR_BP1 BIT(3) /* Block protect 1 */ 93#define SR_BP2 BIT(4) /* Block protect 2 */ 94#define SR_BP_BIT_OFFSET 2 /* Offset to Block protect 0 */ 95#define SR_BP_BIT_MASK (SR_BP2 | SR_BP1 | SR_BP0) 96 97#define SR_TB BIT(5) /* Top/Bottom protect */ 98#define SR_SRWD BIT(7) /* SR write protect */ 99#define SR_BP3 0x40 100/* Bit to determine whether protection starts from top or bottom */ 101#define SR_BP_TB 0x20 102#define BP_BITS_FROM_SR(sr) (((sr) & SR_BP_BIT_MASK) >> SR_BP_BIT_OFFSET) 103#define M25P_MAX_LOCKABLE_SECTORS 64 104 105#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ 106 107/* Enhanced Volatile Configuration Register bits */ 108#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ 109 110/* Flag Status Register bits */ 111#define FSR_READY BIT(7) 112 113/* Configuration Register bits. */ 114#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ 115 116/* Extended/Bank Address Register bits */ 117#define EAR_SEGMENT_MASK 0x7 /* 128 Mb segment mask */ 118 119enum read_mode { 120 SPI_NOR_NORMAL = 0, 121 SPI_NOR_FAST, 122 SPI_NOR_DUAL, 123 SPI_NOR_QUAD, 124}; 125 126#define SPI_NOR_MAX_CMD_SIZE 8 127enum spi_nor_ops { 128 SPI_NOR_OPS_READ = 0, 129 SPI_NOR_OPS_WRITE, 130 SPI_NOR_OPS_ERASE, 131 SPI_NOR_OPS_LOCK, 132 SPI_NOR_OPS_UNLOCK, 133}; 134 135enum spi_nor_option_flags { 136 SNOR_F_USE_FSR = BIT(0), 137 SNOR_F_HAS_SR_TB = BIT(1), 138}; 139 140/** 141 * struct spi_nor - Structure for defining a the SPI NOR layer 142 * @mtd: point to a mtd_info structure 143 * @lock: the lock for the read/write/erase/lock/unlock operations 144 * @dev: point to a spi device, or a spi nor controller device. 145 * @page_size: the page size of the SPI NOR 146 * @addr_width: number of address bytes 147 * @erase_opcode: the opcode for erasing a sector 148 * @read_opcode: the read opcode 149 * @read_dummy: the dummy needed by the read operation 150 * @program_opcode: the program opcode 151 * @flash_read: the mode of the read 152 * @sst_write_second: used by the SST write operation 153 * @flags: flag options for the current SPI-NOR (SNOR_F_*) 154 * @cmd_buf: used by the write_reg 155 * @prepare: [OPTIONAL] do some preparations for the 156 * read/write/erase/lock/unlock operations 157 * @unprepare: [OPTIONAL] do some post work after the 158 * read/write/erase/lock/unlock operations 159 * @read_reg: [DRIVER-SPECIFIC] read out the register 160 * @write_reg: [DRIVER-SPECIFIC] write data to the register 161 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR 162 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR 163 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR 164 * at the offset @offs; if not provided by the driver, 165 * spi-nor will send the erase opcode via write_reg() 166 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR 167 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR 168 * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is 169 * completely locked 170 * @priv: the private data 171 */ 172struct spi_nor { 173 struct mtd_info mtd; 174 struct mutex lock; 175 struct device *dev; 176 struct spi_device *spi; 177 u32 page_size; 178 u8 addr_width; 179 u8 erase_opcode; 180 u8 read_opcode; 181 u8 read_dummy; 182 u8 program_opcode; 183 enum read_mode flash_read; 184 u32 jedec_id; 185 u16 curbank; 186 u16 n_sectors; 187 u32 sector_size; 188 bool sst_write_second; 189 bool shift; 190 bool isparallel; 191 bool isstacked; 192 u32 flags; 193 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; 194 195 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); 196 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); 197 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); 198 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); 199 200 ssize_t (*read)(struct spi_nor *nor, loff_t from, 201 size_t len, u_char *read_buf); 202 ssize_t (*write)(struct spi_nor *nor, loff_t to, 203 size_t len, const u_char *write_buf); 204 int (*erase)(struct spi_nor *nor, loff_t offs); 205 206 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 207 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 208 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); 209 210 void *priv; 211}; 212 213static inline void spi_nor_set_flash_node(struct spi_nor *nor, 214 struct device_node *np) 215{ 216 mtd_set_of_node(&nor->mtd, np); 217} 218 219static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor) 220{ 221 return mtd_get_of_node(&nor->mtd); 222} 223 224/** 225 * spi_nor_scan() - scan the SPI NOR 226 * @nor: the spi_nor structure 227 * @name: the chip type name 228 * @mode: the read mode supported by the driver 229 * 230 * The drivers can use this fuction to scan the SPI NOR. 231 * In the scanning, it will try to get all the necessary information to 232 * fill the mtd_info{} and the spi_nor{}. 233 * 234 * The chip type name can be provided through the @name parameter. 235 * 236 * Return: 0 for success, others for failure. 237 */ 238int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode); 239 240#endif 241