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33#ifndef MLX5_ABI_USER_H
34#define MLX5_ABI_USER_H
35
36#include <linux/types.h>
37
38enum {
39 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
40 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
41};
42
43enum {
44 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
45};
46
47enum {
48 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
49};
50
51
52
53
54#define MLX5_IB_UVERBS_ABI_VERSION 1
55
56
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61
62
63struct mlx5_ib_alloc_ucontext_req {
64 __u32 total_num_uuars;
65 __u32 num_low_latency_uuars;
66};
67
68struct mlx5_ib_alloc_ucontext_req_v2 {
69 __u32 total_num_uuars;
70 __u32 num_low_latency_uuars;
71 __u32 flags;
72 __u32 comp_mask;
73 __u8 max_cqe_version;
74 __u8 reserved0;
75 __u16 reserved1;
76 __u32 reserved2;
77};
78
79enum mlx5_ib_alloc_ucontext_resp_mask {
80 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
81};
82
83enum mlx5_user_cmds_supp_uhw {
84 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
85};
86
87struct mlx5_ib_alloc_ucontext_resp {
88 __u32 qp_tab_size;
89 __u32 bf_reg_size;
90 __u32 tot_uuars;
91 __u32 cache_line_size;
92 __u16 max_sq_desc_sz;
93 __u16 max_rq_desc_sz;
94 __u32 max_send_wqebb;
95 __u32 max_recv_wr;
96 __u32 max_srq_recv_wr;
97 __u16 num_ports;
98 __u16 reserved1;
99 __u32 comp_mask;
100 __u32 response_length;
101 __u8 cqe_version;
102 __u8 cmds_supp_uhw;
103 __u16 reserved2;
104 __u64 hca_core_clock_offset;
105};
106
107struct mlx5_ib_alloc_pd_resp {
108 __u32 pdn;
109};
110
111struct mlx5_ib_tso_caps {
112 __u32 max_tso;
113
114
115
116
117
118 __u32 supported_qpts;
119};
120
121struct mlx5_ib_rss_caps {
122 __u64 rx_hash_fields_mask;
123 __u8 rx_hash_function;
124 __u8 reserved[7];
125};
126
127struct mlx5_ib_query_device_resp {
128 __u32 comp_mask;
129 __u32 response_length;
130 struct mlx5_ib_tso_caps tso_caps;
131 struct mlx5_ib_rss_caps rss_caps;
132};
133
134struct mlx5_ib_create_cq {
135 __u64 buf_addr;
136 __u64 db_addr;
137 __u32 cqe_size;
138 __u32 reserved;
139};
140
141struct mlx5_ib_create_cq_resp {
142 __u32 cqn;
143 __u32 reserved;
144};
145
146struct mlx5_ib_resize_cq {
147 __u64 buf_addr;
148 __u16 cqe_size;
149 __u16 reserved0;
150 __u32 reserved1;
151};
152
153struct mlx5_ib_create_srq {
154 __u64 buf_addr;
155 __u64 db_addr;
156 __u32 flags;
157 __u32 reserved0;
158 __u32 uidx;
159 __u32 reserved1;
160};
161
162struct mlx5_ib_create_srq_resp {
163 __u32 srqn;
164 __u32 reserved;
165};
166
167struct mlx5_ib_create_qp {
168 __u64 buf_addr;
169 __u64 db_addr;
170 __u32 sq_wqe_count;
171 __u32 rq_wqe_count;
172 __u32 rq_wqe_shift;
173 __u32 flags;
174 __u32 uidx;
175 __u32 reserved0;
176 __u64 sq_buf_addr;
177};
178
179
180enum mlx5_rx_hash_function_flags {
181 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
182};
183
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190
191
192enum mlx5_rx_hash_fields {
193 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
194 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
195 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
196 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
197 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
198 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
199 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
200 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7
201};
202
203struct mlx5_ib_create_qp_rss {
204 __u64 rx_hash_fields_mask;
205 __u8 rx_hash_function;
206 __u8 rx_key_len;
207 __u8 reserved[6];
208 __u8 rx_hash_key[128];
209 __u32 comp_mask;
210 __u32 reserved1;
211};
212
213struct mlx5_ib_create_qp_resp {
214 __u32 uuar_index;
215};
216
217struct mlx5_ib_alloc_mw {
218 __u32 comp_mask;
219 __u8 num_klms;
220 __u8 reserved1;
221 __u16 reserved2;
222};
223
224struct mlx5_ib_create_wq {
225 __u64 buf_addr;
226 __u64 db_addr;
227 __u32 rq_wqe_count;
228 __u32 rq_wqe_shift;
229 __u32 user_index;
230 __u32 flags;
231 __u32 comp_mask;
232 __u32 reserved;
233};
234
235struct mlx5_ib_create_wq_resp {
236 __u32 response_length;
237 __u32 reserved;
238};
239
240struct mlx5_ib_create_rwq_ind_tbl_resp {
241 __u32 response_length;
242 __u32 reserved;
243};
244
245struct mlx5_ib_modify_wq {
246 __u32 comp_mask;
247 __u32 reserved;
248};
249#endif
250