LXR linux/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in

   1#ifndef __iop_scrc_in_defs_h
   2#define __iop_scrc_in_defs_h
   3
   4/*
   5 * This file is autogenerated from
   6 *   file:           ../../inst/io_proc/rtl/iop_scrc_in.r
   7 *     id:           iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
   8 *     last modfied: Mon Apr 11 16:08:46 2005
   9 *
  10 *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r
  11 *      id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
  12 * Any changes here will be lost.
  13 *
  14 * -*- buffer-read-only: t -*-
  15 */
  16/* Main access macros */
  17#ifndef REG_RD
  18#define REG_RD( scope, inst, reg ) \
  19  REG_READ( reg_##scope##_##reg, \
  20            (inst) + REG_RD_ADDR_##scope##_##reg )
  21#endif
  22
  23#ifndef REG_WR
  24#define REG_WR( scope, inst, reg, val ) \
  25  REG_WRITE( reg_##scope##_##reg, \
  26             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  27#endif
  28
  29#ifndef REG_RD_VECT
  30#define REG_RD_VECT( scope, inst, reg, index ) \
  31  REG_READ( reg_##scope##_##reg, \
  32            (inst) + REG_RD_ADDR_##scope##_##reg + \
  33            (index) * STRIDE_##scope##_##reg )
  34#endif
  35
  36#ifndef REG_WR_VECT
  37#define REG_WR_VECT( scope, inst, reg, index, val ) \
  38  REG_WRITE( reg_##scope##_##reg, \
  39             (inst) + REG_WR_ADDR_##scope##_##reg + \
  40             (index) * STRIDE_##scope##_##reg, (val) )
  41#endif
  42
  43#ifndef REG_RD_INT
  44#define REG_RD_INT( scope, inst, reg ) \
  45  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  46#endif
  47
  48#ifndef REG_WR_INT
  49#define REG_WR_INT( scope, inst, reg, val ) \
  50  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  51#endif
  52
  53#ifndef REG_RD_INT_VECT
  54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  55  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  56            (index) * STRIDE_##scope##_##reg )
  57#endif
  58
  59#ifndef REG_WR_INT_VECT
  60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  61  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  62             (index) * STRIDE_##scope##_##reg, (val) )
  63#endif
  64
  65#ifndef REG_TYPE_CONV
  66#define REG_TYPE_CONV( type, orgtype, val ) \
  67  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  68#endif
  69
  70#ifndef reg_page_size
  71#define reg_page_size 8192
  72#endif
  73
  74#ifndef REG_ADDR
  75#define REG_ADDR( scope, inst, reg ) \
  76  ( (inst) + REG_RD_ADDR_##scope##_##reg )
  77#endif
  78
  79#ifndef REG_ADDR_VECT
  80#define REG_ADDR_VECT( scope, inst, reg, index ) \
  81  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  82    (index) * STRIDE_##scope##_##reg )
  83#endif
  84
  85/* C-code for register scope iop_scrc_in */
  86
  87/* Register rw_cfg, scope iop_scrc_in, type rw */
  88typedef struct {
  89  unsigned int trig : 2;
  90  unsigned int dummy1 : 30;
  91} reg_iop_scrc_in_rw_cfg;
  92#define REG_RD_ADDR_iop_scrc_in_rw_cfg 0
  93#define REG_WR_ADDR_iop_scrc_in_rw_cfg 0
  94
  95/* Register rw_ctrl, scope iop_scrc_in, type rw */
  96typedef struct {
  97  unsigned int dif_in_en : 1;
  98  unsigned int dummy1    : 31;
  99} reg_iop_scrc_in_rw_ctrl;
 100#define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4
 101#define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4
 102
 103/* Register r_stat, scope iop_scrc_in, type r */
 104typedef struct {
 105  unsigned int err : 1;
 106  unsigned int dummy1 : 31;
 107} reg_iop_scrc_in_r_stat;
 108#define REG_RD_ADDR_iop_scrc_in_r_stat 8
 109
 110/* Register rw_init_crc, scope iop_scrc_in, type rw */
 111typedef unsigned int reg_iop_scrc_in_rw_init_crc;
 112#define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12
 113#define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12
 114
 115/* Register rs_computed_crc, scope iop_scrc_in, type rs */
 116typedef unsigned int reg_iop_scrc_in_rs_computed_crc;
 117#define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16
 118
 119/* Register r_computed_crc, scope iop_scrc_in, type r */
 120typedef unsigned int reg_iop_scrc_in_r_computed_crc;
 121#define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20
 122
 123/* Register rw_crc, scope iop_scrc_in, type rw */
 124typedef unsigned int reg_iop_scrc_in_rw_crc;
 125#define REG_RD_ADDR_iop_scrc_in_rw_crc 24
 126#define REG_WR_ADDR_iop_scrc_in_rw_crc 24
 127
 128/* Register rw_correct_crc, scope iop_scrc_in, type rw */
 129typedef unsigned int reg_iop_scrc_in_rw_correct_crc;
 130#define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28
 131#define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28
 132
 133/* Register rw_wr1bit, scope iop_scrc_in, type rw */
 134typedef struct {
 135  unsigned int data : 2;
 136  unsigned int last : 2;
 137  unsigned int dummy1 : 28;
 138} reg_iop_scrc_in_rw_wr1bit;
 139#define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32
 140#define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32
 141
 142
 143/* Constants */
 144enum {
 145  regk_iop_scrc_in_dif_in                  = 0x00000002,
 146  regk_iop_scrc_in_hi                      = 0x00000000,
 147  regk_iop_scrc_in_neg                     = 0x00000002,
 148  regk_iop_scrc_in_no                      = 0x00000000,
 149  regk_iop_scrc_in_pos                     = 0x00000001,
 150  regk_iop_scrc_in_pos_neg                 = 0x00000003,
 151  regk_iop_scrc_in_r_computed_crc_default  = 0x00000000,
 152  regk_iop_scrc_in_rs_computed_crc_default = 0x00000000,
 153  regk_iop_scrc_in_rw_cfg_default          = 0x00000000,
 154  regk_iop_scrc_in_rw_ctrl_default         = 0x00000000,
 155  regk_iop_scrc_in_rw_init_crc_default     = 0x00000000,
 156  regk_iop_scrc_in_set0                    = 0x00000000,
 157  regk_iop_scrc_in_set1                    = 0x00000001,
 158  regk_iop_scrc_in_yes                     = 0x00000001
 159};
 160#endif /* __iop_scrc_in_defs_h */
 161