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21#include <linux/clk.h>
22#include <linux/dma-mapping.h>
23#include <linux/gpio.h>
24#include <linux/i2c.h>
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/leds.h>
30#include <linux/mmc/host.h>
31#include <linux/mtd/mtd.h>
32#include <linux/mtd/nand.h>
33#include <linux/mtd/partitions.h>
34#include <linux/platform_device.h>
35#include <linux/serial_8250.h>
36#include <linux/spi/spi.h>
37#include <linux/spi/flash.h>
38#include <linux/smc91x.h>
39#include <linux/ata_platform.h>
40#include <asm/mach-au1x00/au1000.h>
41#include <asm/mach-au1x00/au1100_mmc.h>
42#include <asm/mach-au1x00/au1xxx_dbdma.h>
43#include <asm/mach-au1x00/au1xxx_psc.h>
44#include <asm/mach-au1x00/au1200fb.h>
45#include <asm/mach-au1x00/au1550_spi.h>
46#include <asm/mach-db1x00/bcsr.h>
47
48#include "platform.h"
49
50#define BCSR_INT_IDE 0x0001
51#define BCSR_INT_ETH 0x0002
52#define BCSR_INT_PC0 0x0004
53#define BCSR_INT_PC0STSCHG 0x0008
54#define BCSR_INT_PC1 0x0010
55#define BCSR_INT_PC1STSCHG 0x0020
56#define BCSR_INT_DC 0x0040
57#define BCSR_INT_FLASHBUSY 0x0080
58#define BCSR_INT_PC0INSERT 0x0100
59#define BCSR_INT_PC0EJECT 0x0200
60#define BCSR_INT_PC1INSERT 0x0400
61#define BCSR_INT_PC1EJECT 0x0800
62#define BCSR_INT_SD0INSERT 0x1000
63#define BCSR_INT_SD0EJECT 0x2000
64#define BCSR_INT_SD1INSERT 0x4000
65#define BCSR_INT_SD1EJECT 0x8000
66
67#define DB1200_IDE_PHYS_ADDR 0x18800000
68#define DB1200_IDE_REG_SHIFT 5
69#define DB1200_IDE_PHYS_LEN (16 << DB1200_IDE_REG_SHIFT)
70#define DB1200_ETH_PHYS_ADDR 0x19000300
71#define DB1200_NAND_PHYS_ADDR 0x20000000
72
73#define PB1200_IDE_PHYS_ADDR 0x0C800000
74#define PB1200_ETH_PHYS_ADDR 0x0D000300
75#define PB1200_NAND_PHYS_ADDR 0x1C000000
76
77#define DB1200_INT_BEGIN (AU1000_MAX_INTR + 1)
78#define DB1200_IDE_INT (DB1200_INT_BEGIN + 0)
79#define DB1200_ETH_INT (DB1200_INT_BEGIN + 1)
80#define DB1200_PC0_INT (DB1200_INT_BEGIN + 2)
81#define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3)
82#define DB1200_PC1_INT (DB1200_INT_BEGIN + 4)
83#define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5)
84#define DB1200_DC_INT (DB1200_INT_BEGIN + 6)
85#define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7)
86#define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8)
87#define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9)
88#define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10)
89#define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11)
90#define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12)
91#define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13)
92#define PB1200_SD1_INSERT_INT (DB1200_INT_BEGIN + 14)
93#define PB1200_SD1_EJECT_INT (DB1200_INT_BEGIN + 15)
94#define DB1200_INT_END (DB1200_INT_BEGIN + 15)
95
96const char *get_system_type(void);
97
98static int __init db1200_detect_board(void)
99{
100 int bid;
101
102
103 bcsr_init(DB1200_BCSR_PHYS_ADDR,
104 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
105 if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
106 unsigned short t = bcsr_read(BCSR_HEXLEDS);
107 bcsr_write(BCSR_HEXLEDS, ~t);
108 if (bcsr_read(BCSR_HEXLEDS) != t) {
109 bcsr_write(BCSR_HEXLEDS, t);
110 return 0;
111 }
112 }
113
114
115 bcsr_init(PB1200_BCSR_PHYS_ADDR,
116 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
117 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
118 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
119 (bid == BCSR_WHOAMI_PB1200_DDR2)) {
120 unsigned short t = bcsr_read(BCSR_HEXLEDS);
121 bcsr_write(BCSR_HEXLEDS, ~t);
122 if (bcsr_read(BCSR_HEXLEDS) != t) {
123 bcsr_write(BCSR_HEXLEDS, t);
124 return 0;
125 }
126 }
127
128 return 1;
129}
130
131int __init db1200_board_setup(void)
132{
133 unsigned short whoami;
134
135 if (db1200_detect_board())
136 return -ENODEV;
137
138 whoami = bcsr_read(BCSR_WHOAMI);
139 switch (BCSR_WHOAMI_BOARD(whoami)) {
140 case BCSR_WHOAMI_PB1200_DDR1:
141 case BCSR_WHOAMI_PB1200_DDR2:
142 case BCSR_WHOAMI_DB1200:
143 break;
144 default:
145 return -ENODEV;
146 }
147
148 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
149 " Board-ID %d Daughtercard ID %d\n", get_system_type(),
150 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
151
152 return 0;
153}
154
155
156
157static struct mtd_partition db1200_spiflash_parts[] = {
158 {
159 .name = "spi_flash",
160 .offset = 0,
161 .size = MTDPART_SIZ_FULL,
162 },
163};
164
165static struct flash_platform_data db1200_spiflash_data = {
166 .name = "s25fl001",
167 .parts = db1200_spiflash_parts,
168 .nr_parts = ARRAY_SIZE(db1200_spiflash_parts),
169 .type = "m25p10",
170};
171
172static struct spi_board_info db1200_spi_devs[] __initdata = {
173 {
174
175 .modalias = "tmp121",
176 .max_speed_hz = 2000000,
177 .bus_num = 0,
178 .chip_select = 0,
179 .mode = 0,
180 },
181 {
182
183 .modalias = "m25p80",
184 .max_speed_hz = 50000000,
185 .bus_num = 0,
186 .chip_select = 1,
187 .mode = 0,
188 .platform_data = &db1200_spiflash_data,
189 },
190};
191
192static struct i2c_board_info db1200_i2c_devs[] __initdata = {
193 { I2C_BOARD_INFO("24c04", 0x52), },
194 { I2C_BOARD_INFO("ne1619", 0x2d), },
195 { I2C_BOARD_INFO("wm8731", 0x1b), },
196};
197
198
199
200static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
201 unsigned int ctrl)
202{
203 struct nand_chip *this = mtd_to_nand(mtd);
204 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
205
206 ioaddr &= 0xffffff00;
207
208 if (ctrl & NAND_CLE) {
209 ioaddr += MEM_STNAND_CMD;
210 } else if (ctrl & NAND_ALE) {
211 ioaddr += MEM_STNAND_ADDR;
212 } else {
213
214 ioaddr += MEM_STNAND_DATA;
215 }
216 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
217 if (cmd != NAND_CMD_NONE) {
218 __raw_writeb(cmd, this->IO_ADDR_W);
219 wmb();
220 }
221}
222
223static int au1200_nand_device_ready(struct mtd_info *mtd)
224{
225 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
226}
227
228static struct mtd_partition db1200_nand_parts[] = {
229 {
230 .name = "NAND FS 0",
231 .offset = 0,
232 .size = 8 * 1024 * 1024,
233 },
234 {
235 .name = "NAND FS 1",
236 .offset = MTDPART_OFS_APPEND,
237 .size = MTDPART_SIZ_FULL
238 },
239};
240
241struct platform_nand_data db1200_nand_platdata = {
242 .chip = {
243 .nr_chips = 1,
244 .chip_offset = 0,
245 .nr_partitions = ARRAY_SIZE(db1200_nand_parts),
246 .partitions = db1200_nand_parts,
247 .chip_delay = 20,
248 },
249 .ctrl = {
250 .dev_ready = au1200_nand_device_ready,
251 .cmd_ctrl = au1200_nand_cmd_ctrl,
252 },
253};
254
255static struct resource db1200_nand_res[] = {
256 [0] = {
257 .start = DB1200_NAND_PHYS_ADDR,
258 .end = DB1200_NAND_PHYS_ADDR + 0xff,
259 .flags = IORESOURCE_MEM,
260 },
261};
262
263static struct platform_device db1200_nand_dev = {
264 .name = "gen_nand",
265 .num_resources = ARRAY_SIZE(db1200_nand_res),
266 .resource = db1200_nand_res,
267 .id = -1,
268 .dev = {
269 .platform_data = &db1200_nand_platdata,
270 }
271};
272
273
274
275static struct smc91x_platdata db1200_eth_data = {
276 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
277 .leda = RPC_LED_100_10,
278 .ledb = RPC_LED_TX_RX,
279};
280
281static struct resource db1200_eth_res[] = {
282 [0] = {
283 .start = DB1200_ETH_PHYS_ADDR,
284 .end = DB1200_ETH_PHYS_ADDR + 0xf,
285 .flags = IORESOURCE_MEM,
286 },
287 [1] = {
288 .start = DB1200_ETH_INT,
289 .end = DB1200_ETH_INT,
290 .flags = IORESOURCE_IRQ,
291 },
292};
293
294static struct platform_device db1200_eth_dev = {
295 .dev = {
296 .platform_data = &db1200_eth_data,
297 },
298 .name = "smc91x",
299 .id = -1,
300 .num_resources = ARRAY_SIZE(db1200_eth_res),
301 .resource = db1200_eth_res,
302};
303
304
305
306static struct pata_platform_info db1200_ide_info = {
307 .ioport_shift = DB1200_IDE_REG_SHIFT,
308};
309
310#define IDE_ALT_START (14 << DB1200_IDE_REG_SHIFT)
311static struct resource db1200_ide_res[] = {
312 [0] = {
313 .start = DB1200_IDE_PHYS_ADDR,
314 .end = DB1200_IDE_PHYS_ADDR + IDE_ALT_START - 1,
315 .flags = IORESOURCE_MEM,
316 },
317 [1] = {
318 .start = DB1200_IDE_PHYS_ADDR + IDE_ALT_START,
319 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
320 .flags = IORESOURCE_MEM,
321 },
322 [2] = {
323 .start = DB1200_IDE_INT,
324 .end = DB1200_IDE_INT,
325 .flags = IORESOURCE_IRQ,
326 },
327};
328
329static u64 au1200_ide_dmamask = DMA_BIT_MASK(32);
330
331static struct platform_device db1200_ide_dev = {
332 .name = "pata_platform",
333 .id = 0,
334 .dev = {
335 .dma_mask = &au1200_ide_dmamask,
336 .coherent_dma_mask = DMA_BIT_MASK(32),
337 .platform_data = &db1200_ide_info,
338 },
339 .num_resources = ARRAY_SIZE(db1200_ide_res),
340 .resource = db1200_ide_res,
341};
342
343
344
345
346
347
348
349
350static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
351{
352 void(*mmc_cd)(struct mmc_host *, unsigned long);
353
354 if (irq == DB1200_SD0_INSERT_INT) {
355 disable_irq_nosync(DB1200_SD0_INSERT_INT);
356 enable_irq(DB1200_SD0_EJECT_INT);
357 } else {
358 disable_irq_nosync(DB1200_SD0_EJECT_INT);
359 enable_irq(DB1200_SD0_INSERT_INT);
360 }
361
362
363 mmc_cd = symbol_get(mmc_detect_change);
364 if (mmc_cd) {
365 mmc_cd(ptr, msecs_to_jiffies(500));
366 symbol_put(mmc_detect_change);
367 }
368
369 return IRQ_HANDLED;
370}
371
372static int db1200_mmc_cd_setup(void *mmc_host, int en)
373{
374 int ret;
375
376 if (en) {
377 ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
378 0, "sd_insert", mmc_host);
379 if (ret)
380 goto out;
381
382 ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
383 0, "sd_eject", mmc_host);
384 if (ret) {
385 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
386 goto out;
387 }
388
389 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
390 enable_irq(DB1200_SD0_EJECT_INT);
391 else
392 enable_irq(DB1200_SD0_INSERT_INT);
393
394 } else {
395 free_irq(DB1200_SD0_INSERT_INT, mmc_host);
396 free_irq(DB1200_SD0_EJECT_INT, mmc_host);
397 }
398 ret = 0;
399out:
400 return ret;
401}
402
403static void db1200_mmc_set_power(void *mmc_host, int state)
404{
405 if (state) {
406 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
407 msleep(400);
408 } else
409 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
410}
411
412static int db1200_mmc_card_readonly(void *mmc_host)
413{
414 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
415}
416
417static int db1200_mmc_card_inserted(void *mmc_host)
418{
419 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
420}
421
422static void db1200_mmcled_set(struct led_classdev *led,
423 enum led_brightness brightness)
424{
425 if (brightness != LED_OFF)
426 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
427 else
428 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
429}
430
431static struct led_classdev db1200_mmc_led = {
432 .brightness_set = db1200_mmcled_set,
433};
434
435
436
437static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
438{
439 void(*mmc_cd)(struct mmc_host *, unsigned long);
440
441 if (irq == PB1200_SD1_INSERT_INT) {
442 disable_irq_nosync(PB1200_SD1_INSERT_INT);
443 enable_irq(PB1200_SD1_EJECT_INT);
444 } else {
445 disable_irq_nosync(PB1200_SD1_EJECT_INT);
446 enable_irq(PB1200_SD1_INSERT_INT);
447 }
448
449
450 mmc_cd = symbol_get(mmc_detect_change);
451 if (mmc_cd) {
452 mmc_cd(ptr, msecs_to_jiffies(500));
453 symbol_put(mmc_detect_change);
454 }
455
456 return IRQ_HANDLED;
457}
458
459static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
460{
461 int ret;
462
463 if (en) {
464 ret = request_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 0,
465 "sd1_insert", mmc_host);
466 if (ret)
467 goto out;
468
469 ret = request_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 0,
470 "sd1_eject", mmc_host);
471 if (ret) {
472 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
473 goto out;
474 }
475
476 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT)
477 enable_irq(PB1200_SD1_EJECT_INT);
478 else
479 enable_irq(PB1200_SD1_INSERT_INT);
480
481 } else {
482 free_irq(PB1200_SD1_INSERT_INT, mmc_host);
483 free_irq(PB1200_SD1_EJECT_INT, mmc_host);
484 }
485 ret = 0;
486out:
487 return ret;
488}
489
490static void pb1200_mmc1led_set(struct led_classdev *led,
491 enum led_brightness brightness)
492{
493 if (brightness != LED_OFF)
494 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
495 else
496 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
497}
498
499static struct led_classdev pb1200_mmc1_led = {
500 .brightness_set = pb1200_mmc1led_set,
501};
502
503static void pb1200_mmc1_set_power(void *mmc_host, int state)
504{
505 if (state) {
506 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
507 msleep(400);
508 } else
509 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
510}
511
512static int pb1200_mmc1_card_readonly(void *mmc_host)
513{
514 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
515}
516
517static int pb1200_mmc1_card_inserted(void *mmc_host)
518{
519 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
520}
521
522
523static struct au1xmmc_platform_data db1200_mmc_platdata[2] = {
524 [0] = {
525 .cd_setup = db1200_mmc_cd_setup,
526 .set_power = db1200_mmc_set_power,
527 .card_inserted = db1200_mmc_card_inserted,
528 .card_readonly = db1200_mmc_card_readonly,
529 .led = &db1200_mmc_led,
530 },
531 [1] = {
532 .cd_setup = pb1200_mmc1_cd_setup,
533 .set_power = pb1200_mmc1_set_power,
534 .card_inserted = pb1200_mmc1_card_inserted,
535 .card_readonly = pb1200_mmc1_card_readonly,
536 .led = &pb1200_mmc1_led,
537 },
538};
539
540static struct resource au1200_mmc0_resources[] = {
541 [0] = {
542 .start = AU1100_SD0_PHYS_ADDR,
543 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
544 .flags = IORESOURCE_MEM,
545 },
546 [1] = {
547 .start = AU1200_SD_INT,
548 .end = AU1200_SD_INT,
549 .flags = IORESOURCE_IRQ,
550 },
551 [2] = {
552 .start = AU1200_DSCR_CMD0_SDMS_TX0,
553 .end = AU1200_DSCR_CMD0_SDMS_TX0,
554 .flags = IORESOURCE_DMA,
555 },
556 [3] = {
557 .start = AU1200_DSCR_CMD0_SDMS_RX0,
558 .end = AU1200_DSCR_CMD0_SDMS_RX0,
559 .flags = IORESOURCE_DMA,
560 }
561};
562
563static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
564
565static struct platform_device db1200_mmc0_dev = {
566 .name = "au1xxx-mmc",
567 .id = 0,
568 .dev = {
569 .dma_mask = &au1xxx_mmc_dmamask,
570 .coherent_dma_mask = DMA_BIT_MASK(32),
571 .platform_data = &db1200_mmc_platdata[0],
572 },
573 .num_resources = ARRAY_SIZE(au1200_mmc0_resources),
574 .resource = au1200_mmc0_resources,
575};
576
577static struct resource au1200_mmc1_res[] = {
578 [0] = {
579 .start = AU1100_SD1_PHYS_ADDR,
580 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
581 .flags = IORESOURCE_MEM,
582 },
583 [1] = {
584 .start = AU1200_SD_INT,
585 .end = AU1200_SD_INT,
586 .flags = IORESOURCE_IRQ,
587 },
588 [2] = {
589 .start = AU1200_DSCR_CMD0_SDMS_TX1,
590 .end = AU1200_DSCR_CMD0_SDMS_TX1,
591 .flags = IORESOURCE_DMA,
592 },
593 [3] = {
594 .start = AU1200_DSCR_CMD0_SDMS_RX1,
595 .end = AU1200_DSCR_CMD0_SDMS_RX1,
596 .flags = IORESOURCE_DMA,
597 }
598};
599
600static struct platform_device pb1200_mmc1_dev = {
601 .name = "au1xxx-mmc",
602 .id = 1,
603 .dev = {
604 .dma_mask = &au1xxx_mmc_dmamask,
605 .coherent_dma_mask = DMA_BIT_MASK(32),
606 .platform_data = &db1200_mmc_platdata[1],
607 },
608 .num_resources = ARRAY_SIZE(au1200_mmc1_res),
609 .resource = au1200_mmc1_res,
610};
611
612
613
614static int db1200fb_panel_index(void)
615{
616 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
617}
618
619static int db1200fb_panel_init(void)
620{
621
622 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
623 BCSR_BOARD_LCDBL);
624 return 0;
625}
626
627static int db1200fb_panel_shutdown(void)
628{
629
630 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
631 BCSR_BOARD_LCDBL, 0);
632 return 0;
633}
634
635static struct au1200fb_platdata db1200fb_pd = {
636 .panel_index = db1200fb_panel_index,
637 .panel_init = db1200fb_panel_init,
638 .panel_shutdown = db1200fb_panel_shutdown,
639};
640
641static struct resource au1200_lcd_res[] = {
642 [0] = {
643 .start = AU1200_LCD_PHYS_ADDR,
644 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
645 .flags = IORESOURCE_MEM,
646 },
647 [1] = {
648 .start = AU1200_LCD_INT,
649 .end = AU1200_LCD_INT,
650 .flags = IORESOURCE_IRQ,
651 }
652};
653
654static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
655
656static struct platform_device au1200_lcd_dev = {
657 .name = "au1200-lcd",
658 .id = 0,
659 .dev = {
660 .dma_mask = &au1200_lcd_dmamask,
661 .coherent_dma_mask = DMA_BIT_MASK(32),
662 .platform_data = &db1200fb_pd,
663 },
664 .num_resources = ARRAY_SIZE(au1200_lcd_res),
665 .resource = au1200_lcd_res,
666};
667
668
669
670static struct resource au1200_psc0_res[] = {
671 [0] = {
672 .start = AU1550_PSC0_PHYS_ADDR,
673 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
674 .flags = IORESOURCE_MEM,
675 },
676 [1] = {
677 .start = AU1200_PSC0_INT,
678 .end = AU1200_PSC0_INT,
679 .flags = IORESOURCE_IRQ,
680 },
681 [2] = {
682 .start = AU1200_DSCR_CMD0_PSC0_TX,
683 .end = AU1200_DSCR_CMD0_PSC0_TX,
684 .flags = IORESOURCE_DMA,
685 },
686 [3] = {
687 .start = AU1200_DSCR_CMD0_PSC0_RX,
688 .end = AU1200_DSCR_CMD0_PSC0_RX,
689 .flags = IORESOURCE_DMA,
690 },
691};
692
693static struct platform_device db1200_i2c_dev = {
694 .name = "au1xpsc_smbus",
695 .id = 0,
696 .num_resources = ARRAY_SIZE(au1200_psc0_res),
697 .resource = au1200_psc0_res,
698};
699
700static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
701{
702 if (cs)
703 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
704 else
705 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
706}
707
708static struct au1550_spi_info db1200_spi_platdata = {
709 .mainclk_hz = 50000000,
710 .num_chipselect = 2,
711 .activate_cs = db1200_spi_cs_en,
712};
713
714static u64 spi_dmamask = DMA_BIT_MASK(32);
715
716static struct platform_device db1200_spi_dev = {
717 .dev = {
718 .dma_mask = &spi_dmamask,
719 .coherent_dma_mask = DMA_BIT_MASK(32),
720 .platform_data = &db1200_spi_platdata,
721 },
722 .name = "au1550-spi",
723 .id = 0,
724 .num_resources = ARRAY_SIZE(au1200_psc0_res),
725 .resource = au1200_psc0_res,
726};
727
728static struct resource au1200_psc1_res[] = {
729 [0] = {
730 .start = AU1550_PSC1_PHYS_ADDR,
731 .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
732 .flags = IORESOURCE_MEM,
733 },
734 [1] = {
735 .start = AU1200_PSC1_INT,
736 .end = AU1200_PSC1_INT,
737 .flags = IORESOURCE_IRQ,
738 },
739 [2] = {
740 .start = AU1200_DSCR_CMD0_PSC1_TX,
741 .end = AU1200_DSCR_CMD0_PSC1_TX,
742 .flags = IORESOURCE_DMA,
743 },
744 [3] = {
745 .start = AU1200_DSCR_CMD0_PSC1_RX,
746 .end = AU1200_DSCR_CMD0_PSC1_RX,
747 .flags = IORESOURCE_DMA,
748 },
749};
750
751
752static struct platform_device db1200_audio_dev = {
753
754 .id = 1,
755 .num_resources = ARRAY_SIZE(au1200_psc1_res),
756 .resource = au1200_psc1_res,
757};
758
759
760static struct platform_device db1200_sound_dev = {
761
762 .id = 1,
763};
764
765static struct platform_device db1200_stac_dev = {
766 .name = "ac97-codec",
767 .id = 1,
768};
769
770static struct platform_device db1200_audiodma_dev = {
771 .name = "au1xpsc-pcm",
772 .id = 1,
773};
774
775static struct platform_device *db1200_devs[] __initdata = {
776 NULL,
777 &db1200_ide_dev,
778 &db1200_mmc0_dev,
779 &au1200_lcd_dev,
780 &db1200_eth_dev,
781 &db1200_nand_dev,
782 &db1200_audiodma_dev,
783 &db1200_audio_dev,
784 &db1200_stac_dev,
785 &db1200_sound_dev,
786};
787
788static struct platform_device *pb1200_devs[] __initdata = {
789 &pb1200_mmc1_dev,
790};
791
792
793static int __init pb1200_res_fixup(void)
794{
795
796 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
797 printk(KERN_ERR "WARNING!!!\n");
798 printk(KERN_ERR "WARNING!!!\n");
799 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n");
800 printk(KERN_ERR "the board updated to latest revisions.\n");
801 printk(KERN_ERR "This software will not work reliably\n");
802 printk(KERN_ERR "on anything older than CPLD rev 4.!\n");
803 printk(KERN_ERR "WARNING!!!\n");
804 printk(KERN_ERR "WARNING!!!\n");
805 return 1;
806 }
807
808 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
809 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff;
810 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
811 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
812 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
813 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff;
814 return 0;
815}
816
817int __init db1200_dev_setup(void)
818{
819 unsigned long pfc;
820 unsigned short sw;
821 int swapped, bid;
822 struct clk *c;
823
824 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
825 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
826 (bid == BCSR_WHOAMI_PB1200_DDR2)) {
827 if (pb1200_res_fixup())
828 return -ENODEV;
829 }
830
831
832 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
833 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
834
835
836 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
837 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
838 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
839 pfc |= SYS_PINFUNC_P1C;
840 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
841
842
843 c = clk_get(NULL, "psc0_intclk");
844 if (!IS_ERR(c)) {
845 pfc = clk_round_rate(c, 50000000);
846 if ((pfc < 1) || (abs(50000000 - pfc) > 2500000))
847 pr_warn("DB1200: cant get I2C close to 50MHz\n");
848 else
849 clk_set_rate(c, pfc);
850 clk_prepare_enable(c);
851 clk_put(c);
852 }
853
854
855
856
857
858 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
859 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
860 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
861 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
862 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
863 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
864
865 i2c_register_board_info(0, db1200_i2c_devs,
866 ARRAY_SIZE(db1200_i2c_devs));
867 spi_register_board_info(db1200_spi_devs,
868 ARRAY_SIZE(db1200_i2c_devs));
869
870
871
872
873
874
875
876
877
878
879
880
881 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
882
883
884 gpio_request(215, "otg-vbus");
885 gpio_direction_output(215, 1);
886
887 printk(KERN_INFO "%s device configuration:\n", get_system_type());
888
889 sw = bcsr_read(BCSR_SWITCHES);
890 if (sw & BCSR_SWITCHES_DIP_8) {
891 db1200_devs[0] = &db1200_i2c_dev;
892 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
893
894 pfc |= (2 << 17);
895
896 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
897 printk(KERN_INFO " OTG port VBUS supply available!\n");
898 } else {
899 db1200_devs[0] = &db1200_spi_dev;
900 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
901
902 pfc |= (1 << 17);
903
904 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
905 printk(KERN_INFO " OTG port VBUS supply disabled\n");
906 }
907 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
908
909
910
911
912 sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7;
913 if (sw == BCSR_SWITCHES_DIP_8) {
914 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);
915 db1200_audio_dev.name = "au1xpsc_i2s";
916 db1200_sound_dev.name = "db1200-i2s";
917 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n");
918 } else {
919 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);
920 db1200_audio_dev.name = "au1xpsc_ac97";
921 db1200_sound_dev.name = "db1200-ac97";
922 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n");
923 }
924
925
926 __raw_writel(PSC_SEL_CLK_SERCLK,
927 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
928 wmb();
929
930 db1x_register_pcmcia_socket(
931 AU1000_PCMCIA_ATTR_PHYS_ADDR,
932 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
933 AU1000_PCMCIA_MEM_PHYS_ADDR,
934 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
935 AU1000_PCMCIA_IO_PHYS_ADDR,
936 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
937 DB1200_PC0_INT, DB1200_PC0_INSERT_INT,
938 0, DB1200_PC0_EJECT_INT, 0);
939
940 db1x_register_pcmcia_socket(
941 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
942 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
943 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
944 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
945 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
946 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
947 DB1200_PC1_INT, DB1200_PC1_INSERT_INT,
948 0, DB1200_PC1_EJECT_INT, 1);
949
950 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
951 db1x_register_norflash(64 << 20, 2, swapped);
952
953 platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
954
955
956 if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
957 (bid == BCSR_WHOAMI_PB1200_DDR2))
958 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs));
959
960 return 0;
961}
962
