LXR linux/drivers/fpga/zynq-fpga.c

   1/*
   2 * Copyright (c) 2011-2015 Xilinx Inc.
   3 * Copyright (c) 2015, National Instruments Corp.
   4 *
   5 * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
   6 * in their vendor tree.
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; version 2 of the License.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 * GNU General Public License for more details.
  16 */
  17
  18#include <linux/clk.h>
  19#include <linux/completion.h>
  20#include <linux/delay.h>
  21#include <linux/dma-mapping.h>
  22#include <linux/fpga/fpga-mgr.h>
  23#include <linux/interrupt.h>
  24#include <linux/io.h>
  25#include <linux/iopoll.h>
  26#include <linux/module.h>
  27#include <linux/mfd/syscon.h>
  28#include <linux/of_address.h>
  29#include <linux/of_irq.h>
  30#include <linux/pm.h>
  31#include <linux/regmap.h>
  32#include <linux/string.h>
  33
  34/* Offsets into SLCR regmap */
  35
  36/* FPGA Software Reset Control */
  37#define SLCR_FPGA_RST_CTRL_OFFSET       0x240
  38/* Level Shifters Enable */
  39#define SLCR_LVL_SHFTR_EN_OFFSET        0x900
  40
  41/* Constant Definitions */
  42
  43/* Control Register */
  44#define CTRL_OFFSET                     0x00
  45/* Lock Register */
  46#define LOCK_OFFSET                     0x04
  47/* Interrupt Status Register */
  48#define INT_STS_OFFSET                  0x0c
  49/* Interrupt Mask Register */
  50#define INT_MASK_OFFSET                 0x10
  51/* Status Register */
  52#define STATUS_OFFSET                   0x14
  53/* DMA Source Address Register */
  54#define DMA_SRC_ADDR_OFFSET             0x18
  55/* DMA Destination Address Reg */
  56#define DMA_DST_ADDR_OFFSET             0x1c
  57/* DMA Source Transfer Length */
  58#define DMA_SRC_LEN_OFFSET              0x20
  59/* DMA Destination Transfer */
  60#define DMA_DEST_LEN_OFFSET             0x24
  61/* Unlock Register */
  62#define UNLOCK_OFFSET                   0x34
  63/* Misc. Control Register */
  64#define MCTRL_OFFSET                    0x80
  65
  66/* Control Register Bit definitions */
  67
  68/* Signal to reset FPGA */
  69#define CTRL_PCFG_PROG_B_MASK           BIT(30)
  70/* Enable PCAP for PR */
  71#define CTRL_PCAP_PR_MASK               BIT(27)
  72/* Enable PCAP */
  73#define CTRL_PCAP_MODE_MASK             BIT(26)
  74
  75/* Miscellaneous Control Register bit definitions */
  76/* Internal PCAP loopback */
  77#define MCTRL_PCAP_LPBK_MASK            BIT(4)
  78
  79/* Status register bit definitions */
  80
  81/* FPGA init status */
  82#define STATUS_DMA_Q_F                  BIT(31)
  83#define STATUS_PCFG_INIT_MASK           BIT(4)
  84
  85/* Interrupt Status/Mask Register Bit definitions */
  86/* DMA command done */
  87#define IXR_DMA_DONE_MASK               BIT(13)
  88/* DMA and PCAP cmd done */
  89#define IXR_D_P_DONE_MASK               BIT(12)
  90 /* FPGA programmed */
  91#define IXR_PCFG_DONE_MASK              BIT(2)
  92#define IXR_ERROR_FLAGS_MASK            0x00F0F860
  93#define IXR_ALL_MASK                    0xF8F7F87F
  94
  95/* Miscellaneous constant values */
  96
  97/* Invalid DMA addr */
  98#define DMA_INVALID_ADDRESS             GENMASK(31, 0)
  99/* Used to unlock the dev */
 100#define UNLOCK_MASK                     0x757bdf0d
 101/* Timeout for DMA to complete */
 102#define DMA_DONE_TIMEOUT                msecs_to_jiffies(1000)
 103/* Timeout for polling reset bits */
 104#define INIT_POLL_TIMEOUT               2500000
 105/* Delay for polling reset bits */
 106#define INIT_POLL_DELAY                 20
 107
 108/* Masks for controlling stuff in SLCR */
 109/* Disable all Level shifters */
 110#define LVL_SHFTR_DISABLE_ALL_MASK      0x0
 111/* Enable Level shifters from PS to PL */
 112#define LVL_SHFTR_ENABLE_PS_TO_PL       0xa
 113/* Enable Level shifters from PL to PS */
 114#define LVL_SHFTR_ENABLE_PL_TO_PS       0xf
 115/* Enable global resets */
 116#define FPGA_RST_ALL_MASK               0xf
 117/* Disable global resets */
 118#define FPGA_RST_NONE_MASK              0x0
 119
 120struct zynq_fpga_priv {
 121        int irq;
 122        struct clk *clk;
 123
 124        void __iomem *io_base;
 125        struct regmap *slcr;
 126
 127        struct completion dma_done;
 128};
 129
 130static inline void zynq_fpga_write(struct zynq_fpga_priv *priv, u32 offset,
 131                                   u32 val)
 132{
 133        writel(val, priv->io_base + offset);
 134}
 135
 136static inline u32 zynq_fpga_read(const struct zynq_fpga_priv *priv,
 137                                 u32 offset)
 138{
 139        return readl(priv->io_base + offset);
 140}
 141
 142#define zynq_fpga_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
 143        readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
 144                           timeout_us)
 145
 146static void zynq_fpga_mask_irqs(struct zynq_fpga_priv *priv)
 147{
 148        u32 intr_mask;
 149
 150        intr_mask = zynq_fpga_read(priv, INT_MASK_OFFSET);
 151        zynq_fpga_write(priv, INT_MASK_OFFSET,
 152                        intr_mask | IXR_DMA_DONE_MASK | IXR_ERROR_FLAGS_MASK);
 153}
 154
 155static void zynq_fpga_unmask_irqs(struct zynq_fpga_priv *priv)
 156{
 157        u32 intr_mask;
 158
 159        intr_mask = zynq_fpga_read(priv, INT_MASK_OFFSET);
 160        zynq_fpga_write(priv, INT_MASK_OFFSET,
 161                        intr_mask
 162                        & ~(IXR_D_P_DONE_MASK | IXR_ERROR_FLAGS_MASK));
 163}
 164
 165static irqreturn_t zynq_fpga_isr(int irq, void *data)
 166{
 167        struct zynq_fpga_priv *priv = data;
 168
 169        /* disable DMA and error IRQs */
 170        zynq_fpga_mask_irqs(priv);
 171
 172        complete(&priv->dma_done);
 173
 174        return IRQ_HANDLED;
 175}
 176
 177static int zynq_fpga_ops_write_init(struct fpga_manager *mgr,
 178                                    struct fpga_image_info *info,
 179                                    const char *buf, size_t count)
 180{
 181        struct zynq_fpga_priv *priv;
 182        u32 ctrl, status;
 183        int err;
 184
 185        priv = mgr->priv;
 186
 187        err = clk_enable(priv->clk);
 188        if (err)
 189                return err;
 190
 191        /* don't globally reset PL if we're doing partial reconfig */
 192        if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
 193                /* assert AXI interface resets */
 194                regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
 195                             FPGA_RST_ALL_MASK);
 196
 197                /* disable all level shifters */
 198                regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
 199                             LVL_SHFTR_DISABLE_ALL_MASK);
 200                /* enable level shifters from PS to PL */
 201                regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
 202                             LVL_SHFTR_ENABLE_PS_TO_PL);
 203
 204                /* create a rising edge on PCFG_INIT. PCFG_INIT follows
 205                 * PCFG_PROG_B, so we need to poll it after setting PCFG_PROG_B
 206                 * to make sure the rising edge actually happens.
 207                 * Note: PCFG_PROG_B is low active, sequence as described in
 208                 * UG585 v1.10 page 211
 209                 */
 210                ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
 211                ctrl |= CTRL_PCFG_PROG_B_MASK;
 212
 213                zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
 214
 215                err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
 216                                             status & STATUS_PCFG_INIT_MASK,
 217                                             INIT_POLL_DELAY,
 218                                             INIT_POLL_TIMEOUT);
 219                if (err) {
 220                        dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
 221                        goto out_err;
 222                }
 223
 224                ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
 225                ctrl &= ~CTRL_PCFG_PROG_B_MASK;
 226
 227                zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
 228
 229                err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
 230                                             !(status & STATUS_PCFG_INIT_MASK),
 231                                             INIT_POLL_DELAY,
 232                                             INIT_POLL_TIMEOUT);
 233                if (err) {
 234                        dev_err(&mgr->dev, "Timeout waiting for !PCFG_INIT\n");
 235                        goto out_err;
 236                }
 237
 238                ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
 239                ctrl |= CTRL_PCFG_PROG_B_MASK;
 240
 241                zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
 242
 243                err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
 244                                             status & STATUS_PCFG_INIT_MASK,
 245                                             INIT_POLL_DELAY,
 246                                             INIT_POLL_TIMEOUT);
 247                if (err) {
 248                        dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
 249                        goto out_err;
 250                }
 251        }
 252
 253        /* set configuration register with following options:
 254         * - enable PCAP interface
 255         * - set throughput for maximum speed
 256         * - set CPU in user mode
 257         */
 258        ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
 259        zynq_fpga_write(priv, CTRL_OFFSET,
 260                        (CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK | ctrl));
 261
 262        /* check that we have room in the command queue */
 263        status = zynq_fpga_read(priv, STATUS_OFFSET);
 264        if (status & STATUS_DMA_Q_F) {
 265                dev_err(&mgr->dev, "DMA command queue full\n");
 266                err = -EBUSY;
 267                goto out_err;
 268        }
 269
 270        /* ensure internal PCAP loopback is disabled */
 271        ctrl = zynq_fpga_read(priv, MCTRL_OFFSET);
 272        zynq_fpga_write(priv, MCTRL_OFFSET, (~MCTRL_PCAP_LPBK_MASK & ctrl));
 273
 274        clk_disable(priv->clk);
 275
 276        return 0;
 277
 278out_err:
 279        clk_disable(priv->clk);
 280
 281        return err;
 282}
 283
 284static int zynq_fpga_ops_write(struct fpga_manager *mgr,
 285                               const char *buf, size_t count)
 286{
 287        struct zynq_fpga_priv *priv;
 288        int err;
 289        char *kbuf;
 290        size_t in_count;
 291        dma_addr_t dma_addr;
 292        u32 transfer_length;
 293        u32 intr_status;
 294
 295        in_count = count;
 296        priv = mgr->priv;
 297
 298        kbuf =
 299            dma_alloc_coherent(mgr->dev.parent, count, &dma_addr, GFP_KERNEL);
 300        if (!kbuf)
 301                return -ENOMEM;
 302
 303        memcpy(kbuf, buf, count);
 304
 305        /* enable clock */
 306        err = clk_enable(priv->clk);
 307        if (err)
 308                goto out_free;
 309
 310        zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
 311
 312        reinit_completion(&priv->dma_done);
 313
 314        /* enable DMA and error IRQs */
 315        zynq_fpga_unmask_irqs(priv);
 316
 317        /* the +1 in the src addr is used to hold off on DMA_DONE IRQ
 318         * until both AXI and PCAP are done ...
 319         */
 320        zynq_fpga_write(priv, DMA_SRC_ADDR_OFFSET, (u32)(dma_addr) + 1);
 321        zynq_fpga_write(priv, DMA_DST_ADDR_OFFSET, (u32)DMA_INVALID_ADDRESS);
 322
 323        /* convert #bytes to #words */
 324        transfer_length = (count + 3) / 4;
 325
 326        zynq_fpga_write(priv, DMA_SRC_LEN_OFFSET, transfer_length);
 327        zynq_fpga_write(priv, DMA_DEST_LEN_OFFSET, 0);
 328
 329        wait_for_completion(&priv->dma_done);
 330
 331        intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
 332        zynq_fpga_write(priv, INT_STS_OFFSET, intr_status);
 333
 334        if (!((intr_status & IXR_D_P_DONE_MASK) == IXR_D_P_DONE_MASK)) {
 335                dev_err(&mgr->dev, "Error configuring FPGA\n");
 336                err = -EFAULT;
 337        }
 338
 339        clk_disable(priv->clk);
 340
 341out_free:
 342        dma_free_coherent(mgr->dev.parent, count, kbuf, dma_addr);
 343        return err;
 344}
 345
 346static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
 347                                        struct fpga_image_info *info)
 348{
 349        struct zynq_fpga_priv *priv = mgr->priv;
 350        int err;
 351        u32 intr_status;
 352
 353        err = clk_enable(priv->clk);
 354        if (err)
 355                return err;
 356
 357        err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status,
 358                                     intr_status & IXR_PCFG_DONE_MASK,
 359                                     INIT_POLL_DELAY,
 360                                     INIT_POLL_TIMEOUT);
 361
 362        clk_disable(priv->clk);
 363
 364        if (err)
 365                return err;
 366
 367        /* for the partial reconfig case we didn't touch the level shifters */
 368        if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
 369                /* enable level shifters from PL to PS */
 370                regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
 371                             LVL_SHFTR_ENABLE_PL_TO_PS);
 372
 373                /* deassert AXI interface resets */
 374                regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
 375                             FPGA_RST_NONE_MASK);
 376        }
 377
 378        return 0;
 379}
 380
 381static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr)
 382{
 383        int err;
 384        u32 intr_status;
 385        struct zynq_fpga_priv *priv;
 386
 387        priv = mgr->priv;
 388
 389        err = clk_enable(priv->clk);
 390        if (err)
 391                return FPGA_MGR_STATE_UNKNOWN;
 392
 393        intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
 394        clk_disable(priv->clk);
 395
 396        if (intr_status & IXR_PCFG_DONE_MASK)
 397                return FPGA_MGR_STATE_OPERATING;
 398
 399        return FPGA_MGR_STATE_UNKNOWN;
 400}
 401
 402static const struct fpga_manager_ops zynq_fpga_ops = {
 403        .state = zynq_fpga_ops_state,
 404        .write_init = zynq_fpga_ops_write_init,
 405        .write = zynq_fpga_ops_write,
 406        .write_complete = zynq_fpga_ops_write_complete,
 407};
 408
 409static int zynq_fpga_probe(struct platform_device *pdev)
 410{
 411        struct device *dev = &pdev->dev;
 412        struct zynq_fpga_priv *priv;
 413        struct resource *res;
 414        int err;
 415
 416        priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 417        if (!priv)
 418                return -ENOMEM;
 419
 420        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 421        priv->io_base = devm_ioremap_resource(dev, res);
 422        if (IS_ERR(priv->io_base))
 423                return PTR_ERR(priv->io_base);
 424
 425        priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node,
 426                "syscon");
 427        if (IS_ERR(priv->slcr)) {
 428                dev_err(dev, "unable to get zynq-slcr regmap\n");
 429                return PTR_ERR(priv->slcr);
 430        }
 431
 432        init_completion(&priv->dma_done);
 433
 434        priv->irq = platform_get_irq(pdev, 0);
 435        if (priv->irq < 0) {
 436                dev_err(dev, "No IRQ available\n");
 437                return priv->irq;
 438        }
 439
 440        priv->clk = devm_clk_get(dev, "ref_clk");
 441        if (IS_ERR(priv->clk)) {
 442                dev_err(dev, "input clock not found\n");
 443                return PTR_ERR(priv->clk);
 444        }
 445
 446        err = clk_prepare_enable(priv->clk);
 447        if (err) {
 448                dev_err(dev, "unable to enable clock\n");
 449                return err;
 450        }
 451
 452        /* unlock the device */
 453        zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK);
 454
 455        zynq_fpga_write(priv, INT_MASK_OFFSET, 0xFFFFFFFF);
 456        zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
 457        err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, dev_name(dev),
 458                               priv);
 459        if (err) {
 460                dev_err(dev, "unable to request IRQ\n");
 461                clk_disable_unprepare(priv->clk);
 462                return err;
 463        }
 464
 465        clk_disable(priv->clk);
 466
 467        err = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager",
 468                                &zynq_fpga_ops, priv);
 469        if (err) {
 470                dev_err(dev, "unable to register FPGA manager\n");
 471                clk_unprepare(priv->clk);
 472                return err;
 473        }
 474
 475        return 0;
 476}
 477
 478static int zynq_fpga_remove(struct platform_device *pdev)
 479{
 480        struct zynq_fpga_priv *priv;
 481        struct fpga_manager *mgr;
 482
 483        mgr = platform_get_drvdata(pdev);
 484        priv = mgr->priv;
 485
 486        fpga_mgr_unregister(&pdev->dev);
 487
 488        clk_unprepare(priv->clk);
 489
 490        return 0;
 491}
 492
 493#ifdef CONFIG_OF
 494static const struct of_device_id zynq_fpga_of_match[] = {
 495        { .compatible = "xlnx,zynq-devcfg-1.0", },
 496        {},
 497};
 498
 499MODULE_DEVICE_TABLE(of, zynq_fpga_of_match);
 500#endif
 501
 502static struct platform_driver zynq_fpga_driver = {
 503        .probe = zynq_fpga_probe,
 504        .remove = zynq_fpga_remove,
 505        .driver = {
 506                .name = "zynq_fpga_manager",
 507                .of_match_table = of_match_ptr(zynq_fpga_of_match),
 508        },
 509};
 510
 511module_platform_driver(zynq_fpga_driver);
 512
 513MODULE_AUTHOR("Moritz Fischer <moritz.fischer@ettus.com>");
 514MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
 515MODULE_DESCRIPTION("Xilinx Zynq FPGA Manager");
 516MODULE_LICENSE("GPL v2");
 517