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10#include <linux/clk.h>
11#include <linux/io.h>
12#include <drm/drmP.h>
13#include <drm/drm_crtc_helper.h>
14#include "armada_crtc.h"
15#include "armada_drm.h"
16#include "armada_hw.h"
17
18static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev)
19{
20 struct clk *clk;
21
22 clk = devm_clk_get(dev, "ext_ref_clk1");
23 if (IS_ERR(clk))
24 return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER : PTR_ERR(clk);
25
26 dcrtc->extclk[0] = clk;
27
28
29 armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);
30
31 return 0;
32}
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43
44static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc,
45 const struct drm_display_mode *mode, uint32_t *sclk)
46{
47 struct clk *clk = dcrtc->extclk[0];
48 int ret;
49
50 if (dcrtc->num == 1)
51 return -EINVAL;
52
53 if (IS_ERR(clk))
54 return PTR_ERR(clk);
55
56 if (dcrtc->clk != clk) {
57 ret = clk_prepare_enable(clk);
58 if (ret)
59 return ret;
60 dcrtc->clk = clk;
61 }
62
63 if (sclk) {
64 uint32_t rate, ref, div;
65
66 rate = mode->clock * 1000;
67 ref = clk_round_rate(clk, rate);
68 div = DIV_ROUND_UP(ref, rate);
69 if (div < 1)
70 div = 1;
71
72 clk_set_rate(clk, ref);
73 *sclk = div | SCLK_510_EXTCLK1;
74 }
75
76 return 0;
77}
78
79const struct armada_variant armada510_ops = {
80 .has_spu_adv_reg = true,
81 .spu_adv_reg = ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
82 .init = armada510_crtc_init,
83 .compute_clock = armada510_crtc_compute_clock,
84};
85