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27#include <drm/drmP.h>
28#include "radeon.h"
29#include <drm/radeon_drm.h>
30
31#if IS_ENABLED(CONFIG_AGP)
32
33struct radeon_agpmode_quirk {
34 u32 hostbridge_vendor;
35 u32 hostbridge_device;
36 u32 chip_vendor;
37 u32 chip_device;
38 u32 subsys_vendor;
39 u32 subsys_device;
40 u32 default_mode;
41};
42
43static struct radeon_agpmode_quirk radeon_agpmode_quirk_list[] = {
44
45 { PCI_VENDOR_ID_INTEL, 0x2550, PCI_VENDOR_ID_ATI, 0x4152, 0x1458, 0x4038, 4},
46
47 { PCI_VENDOR_ID_INTEL, 0x2570, PCI_VENDOR_ID_ATI, 0x4a4e, PCI_VENDOR_ID_DELL, 0x5106, 4},
48
49 { PCI_VENDOR_ID_INTEL, 0x2570, PCI_VENDOR_ID_ATI, 0x5964,
50 0x148c, 0x2073, 4},
51
52 { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c59,
53 PCI_VENDOR_ID_IBM, 0x052f, 1},
54
55 { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e50,
56 PCI_VENDOR_ID_IBM, 0x0550, 1},
57
58 { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c66,
59 PCI_VENDOR_ID_IBM, 0x054d, 1},
60
61 { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c57,
62 PCI_VENDOR_ID_IBM, 0x0530, 1},
63
64 { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e54,
65 PCI_VENDOR_ID_IBM, 0x054f, 2},
66
67 { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x5c61,
68 PCI_VENDOR_ID_SONY, 0x816b, 2},
69
70 { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x5c61,
71 PCI_VENDOR_ID_SONY, 0x8195, 8},
72
73 { PCI_VENDOR_ID_INTEL, 0x3575, PCI_VENDOR_ID_ATI, 0x4c59,
74 PCI_VENDOR_ID_DELL, 0x00e3, 2},
75
76 { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4c66,
77 PCI_VENDOR_ID_DELL, 0x0149, 1},
78
79 { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c66,
80 PCI_VENDOR_ID_IBM, 0x0531, 1},
81
82 { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
83 0x1025, 0x0061, 1},
84
85 { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
86 0x1025, 0x0064, 1},
87
88 { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
89 PCI_VENDOR_ID_ASUSTEK, 0x1942, 1},
90
91 { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
92 0x10cf, 0x127f, 1},
93
94 { 0x1849, 0x3189, PCI_VENDOR_ID_ATI, 0x5960,
95 0x1787, 0x5960, 4},
96
97 { PCI_VENDOR_ID_VIA, 0x0204, PCI_VENDOR_ID_ATI, 0x5960,
98 0x17af, 0x2020, 4},
99
100 { PCI_VENDOR_ID_VIA, 0x0269, PCI_VENDOR_ID_ATI, 0x4153,
101 PCI_VENDOR_ID_ASUSTEK, 0x003c, 4},
102
103 { PCI_VENDOR_ID_VIA, 0x0305, PCI_VENDOR_ID_ATI, 0x514c,
104 PCI_VENDOR_ID_ATI, 0x013a, 2},
105
106 { PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_ATI, 0x5960,
107 PCI_VENDOR_ID_ASUSTEK, 0x004c, 2},
108
109 { PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_ATI, 0x5960,
110 PCI_VENDOR_ID_ASUSTEK, 0x0054, 2},
111
112 { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x514d,
113 0x174b, 0x7149, 4},
114
115 { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x5960,
116 0x1462, 0x0380, 4},
117
118 { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x5964,
119 0x148c, 0x2073, 4},
120
121 { PCI_VENDOR_ID_ATI, 0xcbb2, PCI_VENDOR_ID_ATI, 0x5c61,
122 PCI_VENDOR_ID_SONY, 0x8175, 1},
123 { 0, 0, 0, 0, 0, 0, 0 },
124};
125#endif
126
127int radeon_agp_init(struct radeon_device *rdev)
128{
129#if IS_ENABLED(CONFIG_AGP)
130 struct radeon_agpmode_quirk *p = radeon_agpmode_quirk_list;
131 struct drm_agp_mode mode;
132 struct drm_agp_info info;
133 uint32_t agp_status;
134 int default_mode;
135 bool is_v3;
136 int ret;
137
138
139 ret = drm_agp_acquire(rdev->ddev);
140 if (ret) {
141 DRM_ERROR("Unable to acquire AGP: %d\n", ret);
142 return ret;
143 }
144
145 ret = drm_agp_info(rdev->ddev, &info);
146 if (ret) {
147 drm_agp_release(rdev->ddev);
148 DRM_ERROR("Unable to get AGP info: %d\n", ret);
149 return ret;
150 }
151
152 if (rdev->ddev->agp->agp_info.aper_size < 32) {
153 drm_agp_release(rdev->ddev);
154 dev_warn(rdev->dev, "AGP aperture too small (%zuM) "
155 "need at least 32M, disabling AGP\n",
156 rdev->ddev->agp->agp_info.aper_size);
157 return -EINVAL;
158 }
159
160 mode.mode = info.mode;
161
162
163
164 if (rdev->family <= CHIP_RV350)
165 agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
166 else
167 agp_status = mode.mode;
168 is_v3 = !!(agp_status & RADEON_AGPv3_MODE);
169
170 if (is_v3) {
171 default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
172 } else {
173 if (agp_status & RADEON_AGP_4X_MODE) {
174 default_mode = 4;
175 } else if (agp_status & RADEON_AGP_2X_MODE) {
176 default_mode = 2;
177 } else {
178 default_mode = 1;
179 }
180 }
181
182
183 while (p && p->chip_device != 0) {
184 if (info.id_vendor == p->hostbridge_vendor &&
185 info.id_device == p->hostbridge_device &&
186 rdev->pdev->vendor == p->chip_vendor &&
187 rdev->pdev->device == p->chip_device &&
188 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
189 rdev->pdev->subsystem_device == p->subsys_device) {
190 default_mode = p->default_mode;
191 }
192 ++p;
193 }
194
195 if (radeon_agpmode > 0) {
196 if ((radeon_agpmode < (is_v3 ? 4 : 1)) ||
197 (radeon_agpmode > (is_v3 ? 8 : 4)) ||
198 (radeon_agpmode & (radeon_agpmode - 1))) {
199 DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n",
200 radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4",
201 default_mode);
202 radeon_agpmode = default_mode;
203 } else {
204 DRM_INFO("AGP mode requested: %d\n", radeon_agpmode);
205 }
206 } else {
207 radeon_agpmode = default_mode;
208 }
209
210 mode.mode &= ~RADEON_AGP_MODE_MASK;
211 if (is_v3) {
212 switch (radeon_agpmode) {
213 case 8:
214 mode.mode |= RADEON_AGPv3_8X_MODE;
215 break;
216 case 4:
217 default:
218 mode.mode |= RADEON_AGPv3_4X_MODE;
219 break;
220 }
221 } else {
222 switch (radeon_agpmode) {
223 case 4:
224 mode.mode |= RADEON_AGP_4X_MODE;
225 break;
226 case 2:
227 mode.mode |= RADEON_AGP_2X_MODE;
228 break;
229 case 1:
230 default:
231 mode.mode |= RADEON_AGP_1X_MODE;
232 break;
233 }
234 }
235
236 mode.mode &= ~RADEON_AGP_FW_MODE;
237 ret = drm_agp_enable(rdev->ddev, mode);
238 if (ret) {
239 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
240 drm_agp_release(rdev->ddev);
241 return ret;
242 }
243
244 rdev->mc.agp_base = rdev->ddev->agp->agp_info.aper_base;
245 rdev->mc.gtt_size = rdev->ddev->agp->agp_info.aper_size << 20;
246 rdev->mc.gtt_start = rdev->mc.agp_base;
247 rdev->mc.gtt_end = rdev->mc.gtt_start + rdev->mc.gtt_size - 1;
248 dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
249 rdev->mc.gtt_size >> 20, rdev->mc.gtt_start, rdev->mc.gtt_end);
250
251
252 if (rdev->family < CHIP_R200) {
253 WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000);
254 }
255 return 0;
256#else
257 return 0;
258#endif
259}
260
261void radeon_agp_resume(struct radeon_device *rdev)
262{
263#if IS_ENABLED(CONFIG_AGP)
264 int r;
265 if (rdev->flags & RADEON_IS_AGP) {
266 r = radeon_agp_init(rdev);
267 if (r)
268 dev_warn(rdev->dev, "radeon AGP reinit failed\n");
269 }
270#endif
271}
272
273void radeon_agp_fini(struct radeon_device *rdev)
274{
275#if IS_ENABLED(CONFIG_AGP)
276 if (rdev->ddev->agp && rdev->ddev->agp->acquired) {
277 drm_agp_release(rdev->ddev);
278 }
279#endif
280}
281
282void radeon_agp_suspend(struct radeon_device *rdev)
283{
284 radeon_agp_fini(rdev);
285}
286