1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <rdma/ib_umem.h>
36#include <linux/atomic.h>
37#include <rdma/ib_user_verbs.h>
38
39#include "iw_cxgb4.h"
40
41int use_dsgl = 0;
42module_param(use_dsgl, int, 0644);
43MODULE_PARM_DESC(use_dsgl, "Use DSGL for PBL/FastReg (default=0)");
44
45#define T4_ULPTX_MIN_IO 32
46#define C4IW_MAX_INLINE_SIZE 96
47#define T4_ULPTX_MAX_DMA 1024
48#define C4IW_INLINE_THRESHOLD 128
49
50static int inline_threshold = C4IW_INLINE_THRESHOLD;
51module_param(inline_threshold, int, 0644);
52MODULE_PARM_DESC(inline_threshold, "inline vs dsgl threshold (default=128)");
53
54static int mr_exceeds_hw_limits(struct c4iw_dev *dev, u64 length)
55{
56 return (is_t4(dev->rdev.lldi.adapter_type) ||
57 is_t5(dev->rdev.lldi.adapter_type)) &&
58 length >= 8*1024*1024*1024ULL;
59}
60
61static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr,
62 u32 len, dma_addr_t data,
63 int wait, struct sk_buff *skb)
64{
65 struct ulp_mem_io *req;
66 struct ulptx_sgl *sgl;
67 u8 wr_len;
68 int ret = 0;
69 struct c4iw_wr_wait wr_wait;
70
71 addr &= 0x7FFFFFF;
72
73 if (wait)
74 c4iw_init_wr_wait(&wr_wait);
75 wr_len = roundup(sizeof(*req) + sizeof(*sgl), 16);
76
77 if (!skb) {
78 skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL);
79 if (!skb)
80 return -ENOMEM;
81 }
82 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
83
84 req = (struct ulp_mem_io *)__skb_put(skb, wr_len);
85 memset(req, 0, wr_len);
86 INIT_ULPTX_WR(req, wr_len, 0, 0);
87 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
88 (wait ? FW_WR_COMPL_F : 0));
89 req->wr.wr_lo = wait ? (__force __be64)(unsigned long) &wr_wait : 0L;
90 req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
91 req->cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE) |
92 T5_ULP_MEMIO_ORDER_V(1) |
93 T5_ULP_MEMIO_FID_V(rdev->lldi.rxq_ids[0]));
94 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(len>>5));
95 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 16));
96 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr));
97
98 sgl = (struct ulptx_sgl *)(req + 1);
99 sgl->cmd_nsge = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_DSGL) |
100 ULPTX_NSGE_V(1));
101 sgl->len0 = cpu_to_be32(len);
102 sgl->addr0 = cpu_to_be64(data);
103
104 ret = c4iw_ofld_send(rdev, skb);
105 if (ret)
106 return ret;
107 if (wait)
108 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
109 return ret;
110}
111
112static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len,
113 void *data, struct sk_buff *skb)
114{
115 struct ulp_mem_io *req;
116 struct ulptx_idata *sc;
117 u8 wr_len, *to_dp, *from_dp;
118 int copy_len, num_wqe, i, ret = 0;
119 struct c4iw_wr_wait wr_wait;
120 __be32 cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE));
121
122 if (is_t4(rdev->lldi.adapter_type))
123 cmd |= cpu_to_be32(ULP_MEMIO_ORDER_F);
124 else
125 cmd |= cpu_to_be32(T5_ULP_MEMIO_IMM_F);
126
127 addr &= 0x7FFFFFF;
128 PDBG("%s addr 0x%x len %u\n", __func__, addr, len);
129 num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE);
130 c4iw_init_wr_wait(&wr_wait);
131 for (i = 0; i < num_wqe; i++) {
132
133 copy_len = len > C4IW_MAX_INLINE_SIZE ? C4IW_MAX_INLINE_SIZE :
134 len;
135 wr_len = roundup(sizeof *req + sizeof *sc +
136 roundup(copy_len, T4_ULPTX_MIN_IO), 16);
137
138 if (!skb) {
139 skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL);
140 if (!skb)
141 return -ENOMEM;
142 }
143 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
144
145 req = (struct ulp_mem_io *)__skb_put(skb, wr_len);
146 memset(req, 0, wr_len);
147 INIT_ULPTX_WR(req, wr_len, 0, 0);
148
149 if (i == (num_wqe-1)) {
150 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
151 FW_WR_COMPL_F);
152 req->wr.wr_lo = (__force __be64)(unsigned long)&wr_wait;
153 } else
154 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR));
155 req->wr.wr_mid = cpu_to_be32(
156 FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
157
158 req->cmd = cmd;
159 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(
160 DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO)));
161 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr),
162 16));
163 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr + i * 3));
164
165 sc = (struct ulptx_idata *)(req + 1);
166 sc->cmd_more = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_IMM));
167 sc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO));
168
169 to_dp = (u8 *)(sc + 1);
170 from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE;
171 if (data)
172 memcpy(to_dp, from_dp, copy_len);
173 else
174 memset(to_dp, 0, copy_len);
175 if (copy_len % T4_ULPTX_MIN_IO)
176 memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO -
177 (copy_len % T4_ULPTX_MIN_IO));
178 ret = c4iw_ofld_send(rdev, skb);
179 skb = NULL;
180 if (ret)
181 return ret;
182 len -= C4IW_MAX_INLINE_SIZE;
183 }
184
185 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
186 return ret;
187}
188
189static int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len,
190 void *data, struct sk_buff *skb)
191{
192 u32 remain = len;
193 u32 dmalen;
194 int ret = 0;
195 dma_addr_t daddr;
196 dma_addr_t save;
197
198 daddr = dma_map_single(&rdev->lldi.pdev->dev, data, len, DMA_TO_DEVICE);
199 if (dma_mapping_error(&rdev->lldi.pdev->dev, daddr))
200 return -1;
201 save = daddr;
202
203 while (remain > inline_threshold) {
204 if (remain < T4_ULPTX_MAX_DMA) {
205 if (remain & ~T4_ULPTX_MIN_IO)
206 dmalen = remain & ~(T4_ULPTX_MIN_IO-1);
207 else
208 dmalen = remain;
209 } else
210 dmalen = T4_ULPTX_MAX_DMA;
211 remain -= dmalen;
212 ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, daddr,
213 !remain, skb);
214 if (ret)
215 goto out;
216 addr += dmalen >> 5;
217 data += dmalen;
218 daddr += dmalen;
219 }
220 if (remain)
221 ret = _c4iw_write_mem_inline(rdev, addr, remain, data, skb);
222out:
223 dma_unmap_single(&rdev->lldi.pdev->dev, save, len, DMA_TO_DEVICE);
224 return ret;
225}
226
227
228
229
230
231static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len,
232 void *data, struct sk_buff *skb)
233{
234 if (is_t5(rdev->lldi.adapter_type) && use_dsgl) {
235 if (len > inline_threshold) {
236 if (_c4iw_write_mem_dma(rdev, addr, len, data, skb)) {
237 printk_ratelimited(KERN_WARNING
238 "%s: dma map"
239 " failure (non fatal)\n",
240 pci_name(rdev->lldi.pdev));
241 return _c4iw_write_mem_inline(rdev, addr, len,
242 data, skb);
243 } else {
244 return 0;
245 }
246 } else
247 return _c4iw_write_mem_inline(rdev, addr,
248 len, data, skb);
249 } else
250 return _c4iw_write_mem_inline(rdev, addr, len, data, skb);
251}
252
253
254
255
256
257
258
259static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry,
260 u32 *stag, u8 stag_state, u32 pdid,
261 enum fw_ri_stag_type type, enum fw_ri_mem_perms perm,
262 int bind_enabled, u32 zbva, u64 to,
263 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr,
264 struct sk_buff *skb)
265{
266 int err;
267 struct fw_ri_tpte tpt;
268 u32 stag_idx;
269 static atomic_t key;
270
271 if (c4iw_fatal_error(rdev))
272 return -EIO;
273
274 stag_state = stag_state > 0;
275 stag_idx = (*stag) >> 8;
276
277 if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) {
278 stag_idx = c4iw_get_resource(&rdev->resource.tpt_table);
279 if (!stag_idx) {
280 mutex_lock(&rdev->stats.lock);
281 rdev->stats.stag.fail++;
282 mutex_unlock(&rdev->stats.lock);
283 return -ENOMEM;
284 }
285 mutex_lock(&rdev->stats.lock);
286 rdev->stats.stag.cur += 32;
287 if (rdev->stats.stag.cur > rdev->stats.stag.max)
288 rdev->stats.stag.max = rdev->stats.stag.cur;
289 mutex_unlock(&rdev->stats.lock);
290 *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff);
291 }
292 PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
293 __func__, stag_state, type, pdid, stag_idx);
294
295
296 if (reset_tpt_entry)
297 memset(&tpt, 0, sizeof(tpt));
298 else {
299 tpt.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F |
300 FW_RI_TPTE_STAGKEY_V((*stag & FW_RI_TPTE_STAGKEY_M)) |
301 FW_RI_TPTE_STAGSTATE_V(stag_state) |
302 FW_RI_TPTE_STAGTYPE_V(type) | FW_RI_TPTE_PDID_V(pdid));
303 tpt.locread_to_qpid = cpu_to_be32(FW_RI_TPTE_PERM_V(perm) |
304 (bind_enabled ? FW_RI_TPTE_MWBINDEN_F : 0) |
305 FW_RI_TPTE_ADDRTYPE_V((zbva ? FW_RI_ZERO_BASED_TO :
306 FW_RI_VA_BASED_TO))|
307 FW_RI_TPTE_PS_V(page_size));
308 tpt.nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32(
309 FW_RI_TPTE_PBLADDR_V(PBL_OFF(rdev, pbl_addr)>>3));
310 tpt.len_lo = cpu_to_be32((u32)(len & 0xffffffffUL));
311 tpt.va_hi = cpu_to_be32((u32)(to >> 32));
312 tpt.va_lo_fbo = cpu_to_be32((u32)(to & 0xffffffffUL));
313 tpt.dca_mwbcnt_pstag = cpu_to_be32(0);
314 tpt.len_hi = cpu_to_be32((u32)(len >> 32));
315 }
316 err = write_adapter_mem(rdev, stag_idx +
317 (rdev->lldi.vr->stag.start >> 5),
318 sizeof(tpt), &tpt, skb);
319
320 if (reset_tpt_entry) {
321 c4iw_put_resource(&rdev->resource.tpt_table, stag_idx);
322 mutex_lock(&rdev->stats.lock);
323 rdev->stats.stag.cur -= 32;
324 mutex_unlock(&rdev->stats.lock);
325 }
326 return err;
327}
328
329static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl,
330 u32 pbl_addr, u32 pbl_size)
331{
332 int err;
333
334 PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
335 __func__, pbl_addr, rdev->lldi.vr->pbl.start,
336 pbl_size);
337
338 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl, NULL);
339 return err;
340}
341
342static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size,
343 u32 pbl_addr, struct sk_buff *skb)
344{
345 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0,
346 pbl_size, pbl_addr, skb);
347}
348
349static int allocate_window(struct c4iw_rdev *rdev, u32 * stag, u32 pdid)
350{
351 *stag = T4_STAG_UNSET;
352 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0,
353 0UL, 0, 0, 0, 0, NULL);
354}
355
356static int deallocate_window(struct c4iw_rdev *rdev, u32 stag,
357 struct sk_buff *skb)
358{
359 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0,
360 0, skb);
361}
362
363static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid,
364 u32 pbl_size, u32 pbl_addr)
365{
366 *stag = T4_STAG_UNSET;
367 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0,
368 0UL, 0, 0, pbl_size, pbl_addr, NULL);
369}
370
371static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag)
372{
373 u32 mmid;
374
375 mhp->attr.state = 1;
376 mhp->attr.stag = stag;
377 mmid = stag >> 8;
378 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
379 PDBG("%s mmid 0x%x mhp %p\n", __func__, mmid, mhp);
380 return insert_handle(mhp->rhp, &mhp->rhp->mmidr, mhp, mmid);
381}
382
383static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php,
384 struct c4iw_mr *mhp, int shift)
385{
386 u32 stag = T4_STAG_UNSET;
387 int ret;
388
389 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid,
390 FW_RI_STAG_NSMR, mhp->attr.len ?
391 mhp->attr.perms : 0,
392 mhp->attr.mw_bind_enable, mhp->attr.zbva,
393 mhp->attr.va_fbo, mhp->attr.len ?
394 mhp->attr.len : -1, shift - 12,
395 mhp->attr.pbl_size, mhp->attr.pbl_addr, NULL);
396 if (ret)
397 return ret;
398
399 ret = finish_mem_reg(mhp, stag);
400 if (ret) {
401 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
402 mhp->attr.pbl_addr, mhp->dereg_skb);
403 mhp->dereg_skb = NULL;
404 }
405 return ret;
406}
407
408static int alloc_pbl(struct c4iw_mr *mhp, int npages)
409{
410 mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev,
411 npages << 3);
412
413 if (!mhp->attr.pbl_addr)
414 return -ENOMEM;
415
416 mhp->attr.pbl_size = npages;
417
418 return 0;
419}
420
421struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc)
422{
423 struct c4iw_dev *rhp;
424 struct c4iw_pd *php;
425 struct c4iw_mr *mhp;
426 int ret;
427 u32 stag = T4_STAG_UNSET;
428
429 PDBG("%s ib_pd %p\n", __func__, pd);
430 php = to_c4iw_pd(pd);
431 rhp = php->rhp;
432
433 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
434 if (!mhp)
435 return ERR_PTR(-ENOMEM);
436
437 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
438 if (!mhp->dereg_skb) {
439 ret = -ENOMEM;
440 goto err0;
441 }
442
443 mhp->rhp = rhp;
444 mhp->attr.pdid = php->pdid;
445 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
446 mhp->attr.mw_bind_enable = (acc&IB_ACCESS_MW_BIND) == IB_ACCESS_MW_BIND;
447 mhp->attr.zbva = 0;
448 mhp->attr.va_fbo = 0;
449 mhp->attr.page_size = 0;
450 mhp->attr.len = ~0ULL;
451 mhp->attr.pbl_size = 0;
452
453 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid,
454 FW_RI_STAG_NSMR, mhp->attr.perms,
455 mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0,
456 NULL);
457 if (ret)
458 goto err1;
459
460 ret = finish_mem_reg(mhp, stag);
461 if (ret)
462 goto err2;
463 return &mhp->ibmr;
464err2:
465 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
466 mhp->attr.pbl_addr, mhp->dereg_skb);
467err1:
468 kfree_skb(mhp->dereg_skb);
469err0:
470 kfree(mhp);
471 return ERR_PTR(ret);
472}
473
474struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
475 u64 virt, int acc, struct ib_udata *udata)
476{
477 __be64 *pages;
478 int shift, n, len;
479 int i, k, entry;
480 int err = 0;
481 struct scatterlist *sg;
482 struct c4iw_dev *rhp;
483 struct c4iw_pd *php;
484 struct c4iw_mr *mhp;
485
486 PDBG("%s ib_pd %p\n", __func__, pd);
487
488 if (length == ~0ULL)
489 return ERR_PTR(-EINVAL);
490
491 if ((length + start) < start)
492 return ERR_PTR(-EINVAL);
493
494 php = to_c4iw_pd(pd);
495 rhp = php->rhp;
496
497 if (mr_exceeds_hw_limits(rhp, length))
498 return ERR_PTR(-EINVAL);
499
500 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
501 if (!mhp)
502 return ERR_PTR(-ENOMEM);
503
504 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
505 if (!mhp->dereg_skb) {
506 kfree(mhp);
507 return ERR_PTR(-ENOMEM);
508 }
509
510 mhp->rhp = rhp;
511
512 mhp->umem = ib_umem_get(pd->uobject->context, start, length, acc, 0);
513 if (IS_ERR(mhp->umem)) {
514 err = PTR_ERR(mhp->umem);
515 kfree_skb(mhp->dereg_skb);
516 kfree(mhp);
517 return ERR_PTR(err);
518 }
519
520 shift = ffs(mhp->umem->page_size) - 1;
521
522 n = mhp->umem->nmap;
523 err = alloc_pbl(mhp, n);
524 if (err)
525 goto err;
526
527 pages = (__be64 *) __get_free_page(GFP_KERNEL);
528 if (!pages) {
529 err = -ENOMEM;
530 goto err_pbl;
531 }
532
533 i = n = 0;
534
535 for_each_sg(mhp->umem->sg_head.sgl, sg, mhp->umem->nmap, entry) {
536 len = sg_dma_len(sg) >> shift;
537 for (k = 0; k < len; ++k) {
538 pages[i++] = cpu_to_be64(sg_dma_address(sg) +
539 mhp->umem->page_size * k);
540 if (i == PAGE_SIZE / sizeof *pages) {
541 err = write_pbl(&mhp->rhp->rdev,
542 pages,
543 mhp->attr.pbl_addr + (n << 3), i);
544 if (err)
545 goto pbl_done;
546 n += i;
547 i = 0;
548 }
549 }
550 }
551
552 if (i)
553 err = write_pbl(&mhp->rhp->rdev, pages,
554 mhp->attr.pbl_addr + (n << 3), i);
555
556pbl_done:
557 free_page((unsigned long) pages);
558 if (err)
559 goto err_pbl;
560
561 mhp->attr.pdid = php->pdid;
562 mhp->attr.zbva = 0;
563 mhp->attr.perms = c4iw_ib_to_tpt_access(acc);
564 mhp->attr.va_fbo = virt;
565 mhp->attr.page_size = shift - 12;
566 mhp->attr.len = length;
567
568 err = register_mem(rhp, php, mhp, shift);
569 if (err)
570 goto err_pbl;
571
572 return &mhp->ibmr;
573
574err_pbl:
575 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
576 mhp->attr.pbl_size << 3);
577
578err:
579 ib_umem_release(mhp->umem);
580 kfree_skb(mhp->dereg_skb);
581 kfree(mhp);
582 return ERR_PTR(err);
583}
584
585struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
586 struct ib_udata *udata)
587{
588 struct c4iw_dev *rhp;
589 struct c4iw_pd *php;
590 struct c4iw_mw *mhp;
591 u32 mmid;
592 u32 stag = 0;
593 int ret;
594
595 if (type != IB_MW_TYPE_1)
596 return ERR_PTR(-EINVAL);
597
598 php = to_c4iw_pd(pd);
599 rhp = php->rhp;
600 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
601 if (!mhp)
602 return ERR_PTR(-ENOMEM);
603
604 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL);
605 if (!mhp->dereg_skb) {
606 ret = -ENOMEM;
607 goto free_mhp;
608 }
609
610 ret = allocate_window(&rhp->rdev, &stag, php->pdid);
611 if (ret)
612 goto free_skb;
613 mhp->rhp = rhp;
614 mhp->attr.pdid = php->pdid;
615 mhp->attr.type = FW_RI_STAG_MW;
616 mhp->attr.stag = stag;
617 mmid = (stag) >> 8;
618 mhp->ibmw.rkey = stag;
619 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) {
620 ret = -ENOMEM;
621 goto dealloc_win;
622 }
623 PDBG("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag);
624 return &(mhp->ibmw);
625
626dealloc_win:
627 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb);
628free_skb:
629 kfree_skb(mhp->dereg_skb);
630free_mhp:
631 kfree(mhp);
632 return ERR_PTR(ret);
633}
634
635int c4iw_dealloc_mw(struct ib_mw *mw)
636{
637 struct c4iw_dev *rhp;
638 struct c4iw_mw *mhp;
639 u32 mmid;
640
641 mhp = to_c4iw_mw(mw);
642 rhp = mhp->rhp;
643 mmid = (mw->rkey) >> 8;
644 remove_handle(rhp, &rhp->mmidr, mmid);
645 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb);
646 kfree_skb(mhp->dereg_skb);
647 kfree(mhp);
648 PDBG("%s ib_mw %p mmid 0x%x ptr %p\n", __func__, mw, mmid, mhp);
649 return 0;
650}
651
652struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
653 enum ib_mr_type mr_type,
654 u32 max_num_sg)
655{
656 struct c4iw_dev *rhp;
657 struct c4iw_pd *php;
658 struct c4iw_mr *mhp;
659 u32 mmid;
660 u32 stag = 0;
661 int ret = 0;
662 int length = roundup(max_num_sg * sizeof(u64), 32);
663
664 php = to_c4iw_pd(pd);
665 rhp = php->rhp;
666
667 if (mr_type != IB_MR_TYPE_MEM_REG ||
668 max_num_sg > t4_max_fr_depth(&rhp->rdev.lldi.ulptx_memwrite_dsgl &&
669 use_dsgl))
670 return ERR_PTR(-EINVAL);
671
672 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
673 if (!mhp) {
674 ret = -ENOMEM;
675 goto err;
676 }
677
678 mhp->mpl = dma_alloc_coherent(&rhp->rdev.lldi.pdev->dev,
679 length, &mhp->mpl_addr, GFP_KERNEL);
680 if (!mhp->mpl) {
681 ret = -ENOMEM;
682 goto err_mpl;
683 }
684 mhp->max_mpl_len = length;
685
686 mhp->rhp = rhp;
687 ret = alloc_pbl(mhp, max_num_sg);
688 if (ret)
689 goto err1;
690 mhp->attr.pbl_size = max_num_sg;
691 ret = allocate_stag(&rhp->rdev, &stag, php->pdid,
692 mhp->attr.pbl_size, mhp->attr.pbl_addr);
693 if (ret)
694 goto err2;
695 mhp->attr.pdid = php->pdid;
696 mhp->attr.type = FW_RI_STAG_NSMR;
697 mhp->attr.stag = stag;
698 mhp->attr.state = 0;
699 mmid = (stag) >> 8;
700 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
701 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) {
702 ret = -ENOMEM;
703 goto err3;
704 }
705
706 PDBG("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag);
707 return &(mhp->ibmr);
708err3:
709 dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size,
710 mhp->attr.pbl_addr, mhp->dereg_skb);
711err2:
712 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
713 mhp->attr.pbl_size << 3);
714err1:
715 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
716 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
717err_mpl:
718 kfree(mhp);
719err:
720 return ERR_PTR(ret);
721}
722
723static int c4iw_set_page(struct ib_mr *ibmr, u64 addr)
724{
725 struct c4iw_mr *mhp = to_c4iw_mr(ibmr);
726
727 if (unlikely(mhp->mpl_len == mhp->max_mpl_len))
728 return -ENOMEM;
729
730 mhp->mpl[mhp->mpl_len++] = addr;
731
732 return 0;
733}
734
735int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
736 unsigned int *sg_offset)
737{
738 struct c4iw_mr *mhp = to_c4iw_mr(ibmr);
739
740 mhp->mpl_len = 0;
741
742 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, c4iw_set_page);
743}
744
745int c4iw_dereg_mr(struct ib_mr *ib_mr)
746{
747 struct c4iw_dev *rhp;
748 struct c4iw_mr *mhp;
749 u32 mmid;
750
751 PDBG("%s ib_mr %p\n", __func__, ib_mr);
752
753 mhp = to_c4iw_mr(ib_mr);
754 rhp = mhp->rhp;
755 mmid = mhp->attr.stag >> 8;
756 remove_handle(rhp, &rhp->mmidr, mmid);
757 if (mhp->mpl)
758 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev,
759 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr);
760 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
761 mhp->attr.pbl_addr, mhp->dereg_skb);
762 if (mhp->attr.pbl_size)
763 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
764 mhp->attr.pbl_size << 3);
765 if (mhp->kva)
766 kfree((void *) (unsigned long) mhp->kva);
767 if (mhp->umem)
768 ib_umem_release(mhp->umem);
769 PDBG("%s mmid 0x%x ptr %p\n", __func__, mmid, mhp);
770 kfree(mhp);
771 return 0;
772}
773
774void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey)
775{
776 struct c4iw_mr *mhp;
777 unsigned long flags;
778
779 spin_lock_irqsave(&rhp->lock, flags);
780 mhp = get_mhp(rhp, rkey >> 8);
781 if (mhp)
782 mhp->attr.state = 0;
783 spin_unlock_irqrestore(&rhp->lock, flags);
784}
785
