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31#ifndef __DRXDRIVER_H__
32#define __DRXDRIVER_H__
33
34#include <linux/kernel.h>
35#include <linux/errno.h>
36#include <linux/firmware.h>
37#include <linux/i2c.h>
38
39
40
41
42
43struct i2c_device_addr {
44 u16 i2c_addr;
45 u16 i2c_dev_id;
46 void *user_data;
47};
48
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55
56
57#define IS_I2C_10BIT(addr) \
58 (((addr) & 0xF8) == 0xF0)
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69
70
71int drxbsp_i2c_init(void);
72
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78
79
80int drxbsp_i2c_term(void);
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111
112int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
113 u16 w_count,
114 u8 *wData,
115 struct i2c_device_addr *r_dev_addr,
116 u16 r_count, u8 *r_data);
117
118
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122
123
124
125char *drxbsp_i2c_error_text(void);
126
127
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129
130
131extern int drx_i2c_error_g;
132
133#define TUNER_MODE_SUB0 0x0001
134#define TUNER_MODE_SUB1 0x0002
135#define TUNER_MODE_SUB2 0x0004
136#define TUNER_MODE_SUB3 0x0008
137#define TUNER_MODE_SUB4 0x0010
138#define TUNER_MODE_SUB5 0x0020
139#define TUNER_MODE_SUB6 0x0040
140#define TUNER_MODE_SUB7 0x0080
141
142#define TUNER_MODE_DIGITAL 0x0100
143#define TUNER_MODE_ANALOG 0x0200
144#define TUNER_MODE_SWITCH 0x0400
145#define TUNER_MODE_LOCK 0x0800
146#define TUNER_MODE_6MHZ 0x1000
147#define TUNER_MODE_7MHZ 0x2000
148#define TUNER_MODE_8MHZ 0x4000
149
150#define TUNER_MODE_SUB_MAX 8
151#define TUNER_MODE_SUBALL (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \
152 TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \
153 TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \
154 TUNER_MODE_SUB6 | TUNER_MODE_SUB7)
155
156
157enum tuner_lock_status {
158 TUNER_LOCKED,
159 TUNER_NOT_LOCKED
160};
161
162struct tuner_common {
163 char *name;
164 s32 min_freq_rf;
165 s32 max_freq_rf;
166
167 u8 sub_mode;
168 char ***sub_mode_descriptions;
169 u8 sub_modes;
170
171
172
173 void *self_check;
174 bool programmed;
175 s32 r_ffrequency;
176 s32 i_ffrequency;
177
178 void *my_user_data;
179 u16 my_capabilities;
180};
181
182struct tuner_instance;
183
184typedef int(*tuner_open_func_t) (struct tuner_instance *tuner);
185typedef int(*tuner_close_func_t) (struct tuner_instance *tuner);
186
187typedef int(*tuner_set_frequency_func_t) (struct tuner_instance *tuner,
188 u32 mode,
189 s32
190 frequency);
191
192typedef int(*tuner_get_frequency_func_t) (struct tuner_instance *tuner,
193 u32 mode,
194 s32 *
195 r_ffrequency,
196 s32 *
197 i_ffrequency);
198
199typedef int(*tuner_lock_status_func_t) (struct tuner_instance *tuner,
200 enum tuner_lock_status *
201 lock_stat);
202
203typedef int(*tune_ri2c_write_read_func_t) (struct tuner_instance *tuner,
204 struct i2c_device_addr *
205 w_dev_addr, u16 w_count,
206 u8 *wData,
207 struct i2c_device_addr *
208 r_dev_addr, u16 r_count,
209 u8 *r_data);
210
211struct tuner_ops {
212 tuner_open_func_t open_func;
213 tuner_close_func_t close_func;
214 tuner_set_frequency_func_t set_frequency_func;
215 tuner_get_frequency_func_t get_frequency_func;
216 tuner_lock_status_func_t lock_status_func;
217 tune_ri2c_write_read_func_t i2c_write_read_func;
218
219};
220
221struct tuner_instance {
222 struct i2c_device_addr my_i2c_dev_addr;
223 struct tuner_common *my_common_attr;
224 void *my_ext_attr;
225 struct tuner_ops *my_funct;
226};
227
228int drxbsp_tuner_set_frequency(struct tuner_instance *tuner,
229 u32 mode,
230 s32 frequency);
231
232int drxbsp_tuner_get_frequency(struct tuner_instance *tuner,
233 u32 mode,
234 s32 *r_ffrequency,
235 s32 *i_ffrequency);
236
237int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner,
238 struct i2c_device_addr *w_dev_addr,
239 u16 w_count,
240 u8 *wData,
241 struct i2c_device_addr *r_dev_addr,
242 u16 r_count, u8 *r_data);
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262#ifndef DRXDAP_SINGLE_MASTER
263#define DRXDAP_SINGLE_MASTER 1
264#endif
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282#ifndef DRXDAP_MAX_WCHUNKSIZE
283#define DRXDAP_MAX_WCHUNKSIZE 60
284#endif
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297
298#ifndef DRXDAP_MAX_RCHUNKSIZE
299#define DRXDAP_MAX_RCHUNKSIZE 60
300#endif
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313
314#ifndef DRX_UNKNOWN
315#define DRX_UNKNOWN (254)
316#endif
317
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323
324
325#ifndef DRX_AUTO
326#define DRX_AUTO (255)
327#endif
328
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340
341#define DRX_CAPABILITY_HAS_LNA (1UL << 0)
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346
347
348#define DRX_CAPABILITY_HAS_OOBRX (1UL << 1)
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354
355#define DRX_CAPABILITY_HAS_ATV (1UL << 2)
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361
362#define DRX_CAPABILITY_HAS_DVBT (1UL << 3)
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368
369#define DRX_CAPABILITY_HAS_ITUB (1UL << 4)
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375
376#define DRX_CAPABILITY_HAS_AUD (1UL << 5)
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382
383#define DRX_CAPABILITY_HAS_SAWSW (1UL << 6)
384
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388
389
390#define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7)
391
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395
396
397#define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8)
398
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403
404#define DRX_CAPABILITY_HAS_IRQN (1UL << 9)
405
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410
411#define DRX_CAPABILITY_HAS_8VSB (1UL << 10)
412
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416
417
418#define DRX_CAPABILITY_HAS_SMATX (1UL << 11)
419
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422
423
424
425#define DRX_CAPABILITY_HAS_SMARX (1UL << 12)
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431
432#define DRX_CAPABILITY_HAS_ITUAC (1UL << 13)
433
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437
438#define DRX_VERSIONSTRING(MAJOR, MINOR, PATCH) \
439 DRX_VERSIONSTRING_HELP(MAJOR)"." \
440 DRX_VERSIONSTRING_HELP(MINOR)"." \
441 DRX_VERSIONSTRING_HELP(PATCH)
442#define DRX_VERSIONSTRING_HELP(NUM) #NUM
443
444
445
446
447
448
449
450
451#define DRX_16TO8(x) ((u8) (((u16)x) & 0xFF)), \
452 ((u8)((((u16)x)>>8)&0xFF))
453
454
455
456
457#define DRX_S9TOS16(x) ((((u16)x)&0x100) ? ((s16)((u16)(x)|0xFF00)) : (x))
458
459
460
461
462#define DRX_S24TODRXFREQ(x) ((((u32) x) & 0x00800000UL) ? \
463 ((s32) \
464 (((u32) x) | 0xFF000000)) : \
465 ((s32) x))
466
467
468
469
470#define DRX_U16TODRXFREQ(x) ((x & 0x8000) ? \
471 ((s32) \
472 (((u32) x) | 0xFFFF0000)) : \
473 ((s32) x))
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482
483enum drx_standard {
484 DRX_STANDARD_DVBT = 0,
485 DRX_STANDARD_8VSB,
486 DRX_STANDARD_NTSC,
487 DRX_STANDARD_PAL_SECAM_BG,
488
489 DRX_STANDARD_PAL_SECAM_DK,
490
491 DRX_STANDARD_PAL_SECAM_I,
492
493 DRX_STANDARD_PAL_SECAM_L,
494
495
496 DRX_STANDARD_PAL_SECAM_LP,
497
498
499 DRX_STANDARD_ITU_A,
500 DRX_STANDARD_ITU_B,
501 DRX_STANDARD_ITU_C,
502 DRX_STANDARD_ITU_D,
503 DRX_STANDARD_FM,
504 DRX_STANDARD_DTMB,
505 DRX_STANDARD_UNKNOWN = DRX_UNKNOWN,
506
507 DRX_STANDARD_AUTO = DRX_AUTO
508
509};
510
511
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513
514
515enum drx_substandard {
516 DRX_SUBSTANDARD_MAIN = 0,
517 DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA,
518 DRX_SUBSTANDARD_ATV_DK_POLAND,
519 DRX_SUBSTANDARD_ATV_DK_CHINA,
520 DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN,
521
522 DRX_SUBSTANDARD_AUTO = DRX_AUTO
523
524};
525
526
527
528
529
530enum drx_bandwidth {
531 DRX_BANDWIDTH_8MHZ = 0,
532 DRX_BANDWIDTH_7MHZ,
533 DRX_BANDWIDTH_6MHZ,
534 DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN,
535
536 DRX_BANDWIDTH_AUTO = DRX_AUTO
537
538};
539
540
541
542
543
544enum drx_mirror {
545 DRX_MIRROR_NO = 0,
546 DRX_MIRROR_YES,
547 DRX_MIRROR_UNKNOWN = DRX_UNKNOWN,
548
549 DRX_MIRROR_AUTO = DRX_AUTO
550
551};
552
553
554
555
556
557enum drx_modulation {
558 DRX_CONSTELLATION_BPSK = 0,
559 DRX_CONSTELLATION_QPSK,
560 DRX_CONSTELLATION_PSK8,
561 DRX_CONSTELLATION_QAM16,
562 DRX_CONSTELLATION_QAM32,
563 DRX_CONSTELLATION_QAM64,
564 DRX_CONSTELLATION_QAM128,
565 DRX_CONSTELLATION_QAM256,
566 DRX_CONSTELLATION_QAM512,
567 DRX_CONSTELLATION_QAM1024,
568 DRX_CONSTELLATION_QPSK_NR,
569 DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
570
571 DRX_CONSTELLATION_AUTO = DRX_AUTO
572
573};
574
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577
578
579enum drx_hierarchy {
580 DRX_HIERARCHY_NONE = 0,
581 DRX_HIERARCHY_ALPHA1,
582 DRX_HIERARCHY_ALPHA2,
583 DRX_HIERARCHY_ALPHA4,
584 DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN,
585
586 DRX_HIERARCHY_AUTO = DRX_AUTO
587
588};
589
590
591
592
593
594enum drx_priority {
595 DRX_PRIORITY_LOW = 0,
596 DRX_PRIORITY_HIGH,
597 DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN
598
599};
600
601
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604
605enum drx_coderate {
606 DRX_CODERATE_1DIV2 = 0,
607 DRX_CODERATE_2DIV3,
608 DRX_CODERATE_3DIV4,
609 DRX_CODERATE_5DIV6,
610 DRX_CODERATE_7DIV8,
611 DRX_CODERATE_UNKNOWN = DRX_UNKNOWN,
612
613 DRX_CODERATE_AUTO = DRX_AUTO
614
615};
616
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619
620
621enum drx_guard {
622 DRX_GUARD_1DIV32 = 0,
623 DRX_GUARD_1DIV16,
624 DRX_GUARD_1DIV8,
625 DRX_GUARD_1DIV4,
626 DRX_GUARD_UNKNOWN = DRX_UNKNOWN,
627
628 DRX_GUARD_AUTO = DRX_AUTO
629
630};
631
632
633
634
635
636enum drx_fft_mode {
637 DRX_FFTMODE_2K = 0,
638 DRX_FFTMODE_4K,
639 DRX_FFTMODE_8K,
640 DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
641
642 DRX_FFTMODE_AUTO = DRX_AUTO
643
644};
645
646
647
648
649
650enum drx_classification {
651 DRX_CLASSIFICATION_GAUSS = 0,
652 DRX_CLASSIFICATION_HVY_GAUSS,
653 DRX_CLASSIFICATION_COCHANNEL,
654 DRX_CLASSIFICATION_STATIC,
655 DRX_CLASSIFICATION_MOVING,
656 DRX_CLASSIFICATION_ZERODB,
657 DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN,
658
659 DRX_CLASSIFICATION_AUTO = DRX_AUTO
660
661};
662
663
664
665
666
667enum drx_interleave_mode {
668 DRX_INTERLEAVEMODE_I128_J1 = 0,
669 DRX_INTERLEAVEMODE_I128_J1_V2,
670 DRX_INTERLEAVEMODE_I128_J2,
671 DRX_INTERLEAVEMODE_I64_J2,
672 DRX_INTERLEAVEMODE_I128_J3,
673 DRX_INTERLEAVEMODE_I32_J4,
674 DRX_INTERLEAVEMODE_I128_J4,
675 DRX_INTERLEAVEMODE_I16_J8,
676 DRX_INTERLEAVEMODE_I128_J5,
677 DRX_INTERLEAVEMODE_I8_J16,
678 DRX_INTERLEAVEMODE_I128_J6,
679 DRX_INTERLEAVEMODE_RESERVED_11,
680 DRX_INTERLEAVEMODE_I128_J7,
681 DRX_INTERLEAVEMODE_RESERVED_13,
682 DRX_INTERLEAVEMODE_I128_J8,
683 DRX_INTERLEAVEMODE_RESERVED_15,
684 DRX_INTERLEAVEMODE_I12_J17,
685 DRX_INTERLEAVEMODE_I5_J4,
686 DRX_INTERLEAVEMODE_B52_M240,
687 DRX_INTERLEAVEMODE_B52_M720,
688 DRX_INTERLEAVEMODE_B52_M48,
689 DRX_INTERLEAVEMODE_B52_M0,
690 DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN,
691
692 DRX_INTERLEAVEMODE_AUTO = DRX_AUTO
693
694};
695
696
697
698
699
700enum drx_carrier_mode {
701 DRX_CARRIER_MULTI = 0,
702 DRX_CARRIER_SINGLE,
703 DRX_CARRIER_UNKNOWN = DRX_UNKNOWN,
704
705 DRX_CARRIER_AUTO = DRX_AUTO
706};
707
708
709
710
711
712enum drx_frame_mode {
713 DRX_FRAMEMODE_420 = 0,
714 DRX_FRAMEMODE_595,
715 DRX_FRAMEMODE_945,
716 DRX_FRAMEMODE_420_FIXED_PN,
717
718 DRX_FRAMEMODE_945_FIXED_PN,
719
720 DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN,
721
722 DRX_FRAMEMODE_AUTO = DRX_AUTO
723
724};
725
726
727
728
729
730enum drx_tps_frame {
731 DRX_TPS_FRAME1 = 0,
732 DRX_TPS_FRAME2,
733 DRX_TPS_FRAME3,
734 DRX_TPS_FRAME4,
735 DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN
736
737};
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741
742
743enum drx_ldpc {
744 DRX_LDPC_0_4 = 0,
745 DRX_LDPC_0_6,
746 DRX_LDPC_0_8,
747 DRX_LDPC_UNKNOWN = DRX_UNKNOWN,
748
749 DRX_LDPC_AUTO = DRX_AUTO
750};
751
752
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754
755
756enum drx_pilot_mode {
757 DRX_PILOT_ON = 0,
758 DRX_PILOT_OFF,
759 DRX_PILOT_UNKNOWN = DRX_UNKNOWN,
760
761 DRX_PILOT_AUTO = DRX_AUTO
762};
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768
769enum drxu_code_action {
770 UCODE_UPLOAD,
771 UCODE_VERIFY
772};
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804enum drx_lock_status {
805 DRX_NEVER_LOCK = 0,
806 DRX_NOT_LOCKED,
807 DRX_LOCK_STATE_1,
808 DRX_LOCK_STATE_2,
809 DRX_LOCK_STATE_3,
810 DRX_LOCK_STATE_4,
811 DRX_LOCK_STATE_5,
812 DRX_LOCK_STATE_6,
813 DRX_LOCK_STATE_7,
814 DRX_LOCK_STATE_8,
815 DRX_LOCK_STATE_9,
816 DRX_LOCKED
817};
818
819
820
821
822enum drx_uio {
823 DRX_UIO1,
824 DRX_UIO2,
825 DRX_UIO3,
826 DRX_UIO4,
827 DRX_UIO5,
828 DRX_UIO6,
829 DRX_UIO7,
830 DRX_UIO8,
831 DRX_UIO9,
832 DRX_UIO10,
833 DRX_UIO11,
834 DRX_UIO12,
835 DRX_UIO13,
836 DRX_UIO14,
837 DRX_UIO15,
838 DRX_UIO16,
839 DRX_UIO17,
840 DRX_UIO18,
841 DRX_UIO19,
842 DRX_UIO20,
843 DRX_UIO21,
844 DRX_UIO22,
845 DRX_UIO23,
846 DRX_UIO24,
847 DRX_UIO25,
848 DRX_UIO26,
849 DRX_UIO27,
850 DRX_UIO28,
851 DRX_UIO29,
852 DRX_UIO30,
853 DRX_UIO31,
854 DRX_UIO32,
855 DRX_UIO_MAX = DRX_UIO32
856};
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858
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864
865
866enum drxuio_mode {
867 DRX_UIO_MODE_DISABLE = 0x01,
868
869 DRX_UIO_MODE_READWRITE = 0x02,
870
871 DRX_UIO_MODE_FIRMWARE = 0x04,
872
873 DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE,
874
875 DRX_UIO_MODE_FIRMWARE1 = 0x08,
876
877 DRX_UIO_MODE_FIRMWARE2 = 0x10,
878
879 DRX_UIO_MODE_FIRMWARE3 = 0x20,
880
881 DRX_UIO_MODE_FIRMWARE4 = 0x40,
882
883 DRX_UIO_MODE_FIRMWARE5 = 0x80
884
885};
886
887
888
889
890
891
892enum drxoob_downstream_standard {
893 DRX_OOB_MODE_A = 0,
894
895 DRX_OOB_MODE_B_GRADE_A,
896
897 DRX_OOB_MODE_B_GRADE_B
898
899};
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910
911#ifndef DRX_CFG_BASE
912#define DRX_CFG_BASE 0
913#endif
914
915#define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0)
916#define DRX_CFG_PKTERR (DRX_CFG_BASE + 1)
917#define DRX_CFG_SYMCLK_OFFS (DRX_CFG_BASE + 2)
918#define DRX_CFG_SMA (DRX_CFG_BASE + 3)
919#define DRX_CFG_PINSAFE (DRX_CFG_BASE + 4)
920#define DRX_CFG_SUBSTANDARD (DRX_CFG_BASE + 5)
921#define DRX_CFG_AUD_VOLUME (DRX_CFG_BASE + 6)
922#define DRX_CFG_AUD_RDS (DRX_CFG_BASE + 7)
923#define DRX_CFG_AUD_AUTOSOUND (DRX_CFG_BASE + 8)
924#define DRX_CFG_AUD_ASS_THRES (DRX_CFG_BASE + 9)
925#define DRX_CFG_AUD_DEVIATION (DRX_CFG_BASE + 10)
926#define DRX_CFG_AUD_PRESCALE (DRX_CFG_BASE + 11)
927#define DRX_CFG_AUD_MIXER (DRX_CFG_BASE + 12)
928#define DRX_CFG_AUD_AVSYNC (DRX_CFG_BASE + 13)
929#define DRX_CFG_AUD_CARRIER (DRX_CFG_BASE + 14)
930#define DRX_CFG_I2S_OUTPUT (DRX_CFG_BASE + 15)
931#define DRX_CFG_ATV_STANDARD (DRX_CFG_BASE + 16)
932#define DRX_CFG_SQI_SPEED (DRX_CFG_BASE + 17)
933#define DRX_CTRL_CFG_MAX (DRX_CFG_BASE + 18)
934
935#define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE
936
937
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948
949struct drxu_code_info {
950 char *mc_file;
951};
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969
970#define AUX_VER_RECORD 0x8000
971
972struct drx_mc_version_rec {
973 u16 aux_type;
974 u32 mc_dev_type;
975 u32 mc_version;
976 u32 mc_base_version;
977};
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986
987struct drx_filter_info {
988 u8 *data_re;
989
990 u8 *data_im;
991
992 u16 size_re;
993
994 u16 size_im;
995
996};
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1003
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1005
1006
1007struct drx_channel {
1008 s32 frequency;
1009
1010 enum drx_bandwidth bandwidth;
1011
1012 enum drx_mirror mirror;
1013 enum drx_modulation constellation;
1014
1015 enum drx_hierarchy hierarchy;
1016
1017 enum drx_priority priority;
1018 enum drx_coderate coderate;
1019 enum drx_guard guard;
1020 enum drx_fft_mode fftmode;
1021 enum drx_classification classification;
1022
1023 u32 symbolrate;
1024
1025 enum drx_interleave_mode interleavemode;
1026
1027 enum drx_ldpc ldpc;
1028 enum drx_carrier_mode carrier;
1029 enum drx_frame_mode framemode;
1030
1031 enum drx_pilot_mode pilot;
1032};
1033
1034
1035
1036enum drx_cfg_sqi_speed {
1037 DRX_SQI_SPEED_FAST = 0,
1038 DRX_SQI_SPEED_MEDIUM,
1039 DRX_SQI_SPEED_SLOW,
1040 DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
1041};
1042
1043
1044
1045
1046
1047
1048
1049
1050struct drx_complex {
1051 s16 im;
1052
1053 s16 re;
1054
1055};
1056
1057
1058
1059
1060
1061
1062
1063
1064struct drx_frequency_plan {
1065 s32 first;
1066
1067 s32 last;
1068
1069 s32 step;
1070
1071 enum drx_bandwidth bandwidth;
1072
1073 u16 ch_number;
1074
1075
1076 char **ch_names;
1077
1078
1079};
1080
1081
1082
1083
1084
1085
1086
1087
1088struct drx_scan_param {
1089 struct drx_frequency_plan *frequency_plan;
1090
1091 u16 frequency_plan_size;
1092 u32 num_tries;
1093 s32 skip;
1094
1095 void *ext_params;
1096};
1097
1098
1099
1100
1101
1102
1103
1104enum drx_scan_command {
1105 DRX_SCAN_COMMAND_INIT = 0,
1106 DRX_SCAN_COMMAND_NEXT,
1107 DRX_SCAN_COMMAND_STOP
1108};
1109
1110
1111
1112
1113
1114
1115typedef int(*drx_scan_func_t) (void *scan_context,
1116 enum drx_scan_command scan_command,
1117 struct drx_channel *scan_channel,
1118 bool *get_next_channel);
1119
1120
1121
1122
1123
1124
1125
1126
1127 struct drxtps_info {
1128 enum drx_fft_mode fftmode;
1129 enum drx_guard guard;
1130 enum drx_modulation constellation;
1131
1132 enum drx_hierarchy hierarchy;
1133
1134 enum drx_coderate high_coderate;
1135
1136 enum drx_coderate low_coderate;
1137
1138 enum drx_tps_frame frame;
1139 u8 length;
1140 u16 cell_id;
1141 };
1142
1143
1144
1145
1146
1147
1148
1149
1150 enum drx_power_mode {
1151 DRX_POWER_UP = 0,
1152
1153 DRX_POWER_MODE_1,
1154
1155 DRX_POWER_MODE_2,
1156
1157 DRX_POWER_MODE_3,
1158
1159 DRX_POWER_MODE_4,
1160
1161 DRX_POWER_MODE_5,
1162
1163 DRX_POWER_MODE_6,
1164
1165 DRX_POWER_MODE_7,
1166
1167 DRX_POWER_MODE_8,
1168
1169
1170 DRX_POWER_MODE_9,
1171
1172 DRX_POWER_MODE_10,
1173
1174 DRX_POWER_MODE_11,
1175
1176 DRX_POWER_MODE_12,
1177
1178 DRX_POWER_MODE_13,
1179
1180 DRX_POWER_MODE_14,
1181
1182 DRX_POWER_MODE_15,
1183
1184 DRX_POWER_MODE_16,
1185
1186 DRX_POWER_DOWN = 255
1187
1188 };
1189
1190
1191
1192
1193
1194
1195
1196
1197 enum drx_module {
1198 DRX_MODULE_DEVICE,
1199 DRX_MODULE_MICROCODE,
1200 DRX_MODULE_DRIVERCORE,
1201 DRX_MODULE_DEVICEDRIVER,
1202 DRX_MODULE_DAP,
1203 DRX_MODULE_BSP_I2C,
1204 DRX_MODULE_BSP_TUNER,
1205 DRX_MODULE_BSP_HOST,
1206 DRX_MODULE_UNKNOWN
1207 };
1208
1209
1210
1211
1212
1213
1214 struct drx_version {
1215 enum drx_module module_type;
1216
1217 char *module_name;
1218
1219 u16 v_major;
1220 u16 v_minor;
1221 u16 v_patch;
1222 char *v_string;
1223 };
1224
1225
1226
1227
1228
1229
1230struct drx_version_list {
1231 struct drx_version *version;
1232 struct drx_version_list *next;
1233
1234};
1235
1236
1237
1238
1239
1240
1241
1242
1243 struct drxuio_cfg {
1244 enum drx_uio uio;
1245
1246 enum drxuio_mode mode;
1247
1248 };
1249
1250
1251
1252
1253
1254
1255
1256
1257 struct drxuio_data {
1258 enum drx_uio uio;
1259
1260 bool value;
1261
1262 };
1263
1264
1265
1266
1267
1268
1269
1270
1271 struct drxoob {
1272 s32 frequency;
1273 enum drxoob_downstream_standard standard;
1274
1275 bool spectrum_inverted;
1276
1277 };
1278
1279
1280
1281
1282
1283
1284
1285
1286 struct drxoob_status {
1287 s32 frequency;
1288 enum drx_lock_status lock;
1289 u32 mer;
1290 s32 symbol_rate_offset;
1291 };
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301 struct drx_cfg {
1302 u32 cfg_type;
1303
1304 void *cfg_data;
1305
1306 };
1307
1308
1309
1310
1311
1312
1313
1314
1315 enum drxmpeg_str_width {
1316 DRX_MPEG_STR_WIDTH_1,
1317 DRX_MPEG_STR_WIDTH_8
1318 };
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328 struct drx_cfg_mpeg_output {
1329 bool enable_mpeg_output;
1330 bool insert_rs_byte;
1331 bool enable_parallel;
1332
1333 bool invert_data;
1334 bool invert_err;
1335 bool invert_str;
1336 bool invert_val;
1337 bool invert_clk;
1338 bool static_clk;
1339
1340
1341
1342 u32 bitrate;
1343
1344 enum drxmpeg_str_width width_str;
1345
1346 };
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358 struct drxi2c_data {
1359 u16 port_nr;
1360 struct i2c_device_addr *w_dev_addr;
1361
1362 u16 w_count;
1363 u8 *wData;
1364 struct i2c_device_addr *r_dev_addr;
1365
1366 u16 r_count;
1367 u8 *r_data;
1368 };
1369
1370
1371
1372
1373
1374
1375
1376
1377 enum drx_aud_standard {
1378 DRX_AUD_STANDARD_BTSC,
1379 DRX_AUD_STANDARD_A2,
1380 DRX_AUD_STANDARD_EIAJ,
1381 DRX_AUD_STANDARD_FM_STEREO,
1382 DRX_AUD_STANDARD_M_MONO,
1383 DRX_AUD_STANDARD_D_K_MONO,
1384 DRX_AUD_STANDARD_BG_FM,
1385 DRX_AUD_STANDARD_D_K1,
1386 DRX_AUD_STANDARD_D_K2,
1387 DRX_AUD_STANDARD_D_K3,
1388 DRX_AUD_STANDARD_BG_NICAM_FM,
1389
1390 DRX_AUD_STANDARD_L_NICAM_AM,
1391
1392 DRX_AUD_STANDARD_I_NICAM_FM,
1393
1394 DRX_AUD_STANDARD_D_K_NICAM_FM,
1395
1396 DRX_AUD_STANDARD_NOT_READY,
1397 DRX_AUD_STANDARD_AUTO = DRX_AUTO,
1398
1399 DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN
1400
1401 };
1402
1403
1404
1405
1406
1407 enum drx_aud_nicam_status {
1408 DRX_AUD_NICAM_DETECTED = 0,
1409
1410 DRX_AUD_NICAM_NOT_DETECTED,
1411
1412 DRX_AUD_NICAM_BAD
1413 };
1414
1415
1416
1417
1418 struct drx_aud_status {
1419 bool stereo;
1420 bool carrier_a;
1421 bool carrier_b;
1422 bool sap;
1423 bool rds;
1424 enum drx_aud_nicam_status nicam_status;
1425
1426 s8 fm_ident;
1427 };
1428
1429
1430
1431
1432
1433
1434
1435 struct drx_cfg_aud_rds {
1436 bool valid;
1437 u16 data[18];
1438 };
1439
1440
1441
1442
1443
1444
1445 enum drx_aud_avc_mode {
1446 DRX_AUD_AVC_OFF,
1447 DRX_AUD_AVC_DECAYTIME_8S,
1448 DRX_AUD_AVC_DECAYTIME_4S,
1449 DRX_AUD_AVC_DECAYTIME_2S,
1450 DRX_AUD_AVC_DECAYTIME_20MS
1451 };
1452
1453
1454
1455
1456
1457 enum drx_aud_avc_max_gain {
1458 DRX_AUD_AVC_MAX_GAIN_0DB,
1459 DRX_AUD_AVC_MAX_GAIN_6DB,
1460 DRX_AUD_AVC_MAX_GAIN_12DB
1461 };
1462
1463
1464
1465
1466
1467 enum drx_aud_avc_max_atten {
1468 DRX_AUD_AVC_MAX_ATTEN_12DB,
1469
1470 DRX_AUD_AVC_MAX_ATTEN_18DB,
1471
1472 DRX_AUD_AVC_MAX_ATTEN_24DB
1473 };
1474
1475
1476
1477 struct drx_cfg_aud_volume {
1478 bool mute;
1479 s16 volume;
1480 enum drx_aud_avc_mode avc_mode;
1481 u16 avc_ref_level;
1482 enum drx_aud_avc_max_gain avc_max_gain;
1483
1484 enum drx_aud_avc_max_atten avc_max_atten;
1485
1486 s16 strength_left;
1487 s16 strength_right;
1488 };
1489
1490
1491
1492
1493
1494 enum drxi2s_mode {
1495 DRX_I2S_MODE_MASTER,
1496 DRX_I2S_MODE_SLAVE
1497 };
1498
1499
1500
1501
1502 enum drxi2s_word_length {
1503 DRX_I2S_WORDLENGTH_32 = 0,
1504 DRX_I2S_WORDLENGTH_16 = 1
1505 };
1506
1507
1508
1509
1510 enum drxi2s_format {
1511 DRX_I2S_FORMAT_WS_WITH_DATA,
1512
1513 DRX_I2S_FORMAT_WS_ADVANCED
1514
1515 };
1516
1517
1518
1519
1520 enum drxi2s_polarity {
1521 DRX_I2S_POLARITY_RIGHT,
1522 DRX_I2S_POLARITY_LEFT
1523 };
1524
1525
1526
1527
1528 struct drx_cfg_i2s_output {
1529 bool output_enable;
1530 u32 frequency;
1531 enum drxi2s_mode mode;
1532 enum drxi2s_word_length word_length;
1533
1534 enum drxi2s_polarity polarity;
1535 enum drxi2s_format format;
1536 };
1537
1538
1539
1540
1541
1542
1543 enum drx_aud_fm_deemphasis {
1544 DRX_AUD_FM_DEEMPH_50US,
1545 DRX_AUD_FM_DEEMPH_75US,
1546 DRX_AUD_FM_DEEMPH_OFF
1547 };
1548
1549
1550
1551
1552
1553
1554 enum drx_cfg_aud_deviation {
1555 DRX_AUD_DEVIATION_NORMAL,
1556 DRX_AUD_DEVIATION_HIGH
1557 };
1558
1559
1560
1561
1562
1563 enum drx_no_carrier_option {
1564 DRX_NO_CARRIER_MUTE,
1565 DRX_NO_CARRIER_NOISE
1566 };
1567
1568
1569
1570
1571
1572 enum drx_cfg_aud_auto_sound {
1573 DRX_AUD_AUTO_SOUND_OFF = 0,
1574 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON,
1575 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF
1576 };
1577
1578
1579
1580
1581
1582 struct drx_cfg_aud_ass_thres {
1583 u16 a2;
1584 u16 btsc;
1585 u16 nicam;
1586 };
1587
1588
1589
1590
1591 struct drx_aud_carrier {
1592 u16 thres;
1593 enum drx_no_carrier_option opt;
1594 s32 shift;
1595 s32 dco;
1596 };
1597
1598
1599
1600
1601 struct drx_cfg_aud_carriers {
1602 struct drx_aud_carrier a;
1603 struct drx_aud_carrier b;
1604 };
1605
1606
1607
1608
1609 enum drx_aud_i2s_src {
1610 DRX_AUD_SRC_MONO,
1611 DRX_AUD_SRC_STEREO_OR_AB,
1612 DRX_AUD_SRC_STEREO_OR_A,
1613 DRX_AUD_SRC_STEREO_OR_B};
1614
1615
1616
1617
1618 enum drx_aud_i2s_matrix {
1619 DRX_AUD_I2S_MATRIX_A_MONO,
1620
1621 DRX_AUD_I2S_MATRIX_B_MONO,
1622
1623 DRX_AUD_I2S_MATRIX_STEREO,
1624
1625 DRX_AUD_I2S_MATRIX_MONO };
1626
1627
1628
1629
1630
1631 enum drx_aud_fm_matrix {
1632 DRX_AUD_FM_MATRIX_NO_MATRIX,
1633 DRX_AUD_FM_MATRIX_GERMAN,
1634 DRX_AUD_FM_MATRIX_KOREAN,
1635 DRX_AUD_FM_MATRIX_SOUND_A,
1636 DRX_AUD_FM_MATRIX_SOUND_B};
1637
1638
1639
1640
1641
1642struct drx_cfg_aud_mixer {
1643 enum drx_aud_i2s_src source_i2s;
1644 enum drx_aud_i2s_matrix matrix_i2s;
1645 enum drx_aud_fm_matrix matrix_fm;
1646};
1647
1648
1649
1650
1651
1652
1653
1654 enum drx_cfg_aud_av_sync {
1655 DRX_AUD_AVSYNC_OFF,
1656 DRX_AUD_AVSYNC_NTSC,
1657
1658 DRX_AUD_AVSYNC_MONOCHROME,
1659
1660 DRX_AUD_AVSYNC_PAL_SECAM
1661 };
1662
1663
1664
1665
1666struct drx_cfg_aud_prescale {
1667 u16 fm_deviation;
1668 s16 nicam_gain;
1669};
1670
1671
1672
1673
1674struct drx_aud_beep {
1675 s16 volume;
1676 u16 frequency;
1677 bool mute;
1678};
1679
1680
1681
1682
1683 enum drx_aud_btsc_detect {
1684 DRX_BTSC_STEREO,
1685 DRX_BTSC_MONO_AND_SAP};
1686
1687
1688
1689
1690struct drx_aud_data {
1691
1692 bool audio_is_active;
1693 enum drx_aud_standard audio_standard;
1694 struct drx_cfg_i2s_output i2sdata;
1695 struct drx_cfg_aud_volume volume;
1696 enum drx_cfg_aud_auto_sound auto_sound;
1697 struct drx_cfg_aud_ass_thres ass_thresholds;
1698 struct drx_cfg_aud_carriers carriers;
1699 struct drx_cfg_aud_mixer mixer;
1700 enum drx_cfg_aud_deviation deviation;
1701 enum drx_cfg_aud_av_sync av_sync;
1702 struct drx_cfg_aud_prescale prescale;
1703 enum drx_aud_fm_deemphasis deemph;
1704 enum drx_aud_btsc_detect btsc_detect;
1705
1706 u16 rds_data_counter;
1707 bool rds_data_present;
1708};
1709
1710
1711
1712
1713 enum drx_qam_lock_range {
1714 DRX_QAM_LOCKRANGE_NORMAL,
1715 DRX_QAM_LOCKRANGE_EXTENDED};
1716
1717
1718
1719
1720
1721
1722
1723
1724 typedef u32 dr_xaddr_t, *pdr_xaddr_t;
1725
1726
1727 typedef u32 dr_xflags_t, *pdr_xflags_t;
1728
1729
1730 typedef int(*drx_write_block_func_t) (struct i2c_device_addr *dev_addr,
1731 u32 addr,
1732 u16 datasize,
1733 u8 *data,
1734 u32 flags);
1735
1736
1737 typedef int(*drx_read_block_func_t) (struct i2c_device_addr *dev_addr,
1738 u32 addr,
1739 u16 datasize,
1740 u8 *data,
1741 u32 flags);
1742
1743
1744 typedef int(*drx_write_reg8func_t) (struct i2c_device_addr *dev_addr,
1745 u32 addr,
1746 u8 data,
1747 u32 flags);
1748
1749
1750 typedef int(*drx_read_reg8func_t) (struct i2c_device_addr *dev_addr,
1751 u32 addr,
1752 u8 *data,
1753 u32 flags);
1754
1755
1756 typedef int(*drx_read_modify_write_reg8func_t) (struct i2c_device_addr *dev_addr,
1757 u32 waddr,
1758 u32 raddr,
1759 u8 wdata,
1760 u8 *rdata);
1761
1762
1763 typedef int(*drx_write_reg16func_t) (struct i2c_device_addr *dev_addr,
1764 u32 addr,
1765 u16 data,
1766 u32 flags);
1767
1768
1769 typedef int(*drx_read_reg16func_t) (struct i2c_device_addr *dev_addr,
1770 u32 addr,
1771 u16 *data,
1772 u32 flags);
1773
1774
1775 typedef int(*drx_read_modify_write_reg16func_t) (struct i2c_device_addr *dev_addr,
1776 u32 waddr,
1777 u32 raddr,
1778 u16 wdata,
1779 u16 *rdata);
1780
1781
1782 typedef int(*drx_write_reg32func_t) (struct i2c_device_addr *dev_addr,
1783 u32 addr,
1784 u32 data,
1785 u32 flags);
1786
1787
1788 typedef int(*drx_read_reg32func_t) (struct i2c_device_addr *dev_addr,
1789 u32 addr,
1790 u32 *data,
1791 u32 flags);
1792
1793
1794 typedef int(*drx_read_modify_write_reg32func_t) (struct i2c_device_addr *dev_addr,
1795 u32 waddr,
1796 u32 raddr,
1797 u32 wdata,
1798 u32 *rdata);
1799
1800
1801
1802
1803struct drx_access_func {
1804 drx_write_block_func_t write_block_func;
1805 drx_read_block_func_t read_block_func;
1806 drx_write_reg8func_t write_reg8func;
1807 drx_read_reg8func_t read_reg8func;
1808 drx_read_modify_write_reg8func_t read_modify_write_reg8func;
1809 drx_write_reg16func_t write_reg16func;
1810 drx_read_reg16func_t read_reg16func;
1811 drx_read_modify_write_reg16func_t read_modify_write_reg16func;
1812 drx_write_reg32func_t write_reg32func;
1813 drx_read_reg32func_t read_reg32func;
1814 drx_read_modify_write_reg32func_t read_modify_write_reg32func;
1815};
1816
1817
1818struct drx_reg_dump {
1819 u32 address;
1820 u32 data;
1821};
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832 struct drx_common_attr {
1833
1834 char *microcode_file;
1835 bool verify_microcode;
1836
1837 struct drx_mc_version_rec mcversion;
1838
1839
1840
1841 s32 intermediate_freq;
1842
1843 s32 sys_clock_freq;
1844
1845 s32 osc_clock_freq;
1846
1847 s16 osc_clock_deviation;
1848
1849 bool mirror_freq_spect;
1850
1851
1852
1853 struct drx_cfg_mpeg_output mpeg_cfg;
1854
1855
1856 bool is_opened;
1857
1858
1859 struct drx_scan_param *scan_param;
1860
1861 u16 scan_freq_plan_index;
1862
1863 s32 scan_next_frequency;
1864
1865 bool scan_ready;
1866 u32 scan_max_channels;
1867 u32 scan_channels_scanned;
1868
1869
1870 drx_scan_func_t scan_function;
1871
1872
1873 void *scan_context;
1874
1875 u16 scan_demod_lock_timeout;
1876
1877 enum drx_lock_status scan_desired_lock;
1878
1879
1880
1881 bool scan_active;
1882
1883
1884 enum drx_power_mode current_power_mode;
1885
1886
1887
1888 u8 tuner_port_nr;
1889 s32 tuner_min_freq_rf;
1890
1891 s32 tuner_max_freq_rf;
1892
1893 bool tuner_rf_agc_pol;
1894 bool tuner_if_agc_pol;
1895 bool tuner_slow_mode;
1896
1897 struct drx_channel current_channel;
1898
1899 enum drx_standard current_standard;
1900
1901 enum drx_standard prev_standard;
1902
1903 enum drx_standard di_cache_standard;
1904
1905 bool use_bootloader;
1906 u32 capabilities;
1907 u32 product_id; };
1908
1909
1910
1911
1912
1913struct drx_demod_instance;
1914
1915
1916
1917
1918struct drx_demod_instance {
1919
1920 struct i2c_device_addr *my_i2c_dev_addr;
1921
1922 struct drx_common_attr *my_common_attr;
1923
1924 void *my_ext_attr;
1925
1926
1927 struct i2c_adapter *i2c;
1928 const struct firmware *firmware;
1929};
1930
1931
1932
1933
1934
1935
1936
1937
1938#define DRX_STR_STANDARD(x) ( \
1939 (x == DRX_STANDARD_DVBT) ? "DVB-T" : \
1940 (x == DRX_STANDARD_8VSB) ? "8VSB" : \
1941 (x == DRX_STANDARD_NTSC) ? "NTSC" : \
1942 (x == DRX_STANDARD_PAL_SECAM_BG) ? "PAL/SECAM B/G" : \
1943 (x == DRX_STANDARD_PAL_SECAM_DK) ? "PAL/SECAM D/K" : \
1944 (x == DRX_STANDARD_PAL_SECAM_I) ? "PAL/SECAM I" : \
1945 (x == DRX_STANDARD_PAL_SECAM_L) ? "PAL/SECAM L" : \
1946 (x == DRX_STANDARD_PAL_SECAM_LP) ? "PAL/SECAM LP" : \
1947 (x == DRX_STANDARD_ITU_A) ? "ITU-A" : \
1948 (x == DRX_STANDARD_ITU_B) ? "ITU-B" : \
1949 (x == DRX_STANDARD_ITU_C) ? "ITU-C" : \
1950 (x == DRX_STANDARD_ITU_D) ? "ITU-D" : \
1951 (x == DRX_STANDARD_FM) ? "FM" : \
1952 (x == DRX_STANDARD_DTMB) ? "DTMB" : \
1953 (x == DRX_STANDARD_AUTO) ? "Auto" : \
1954 (x == DRX_STANDARD_UNKNOWN) ? "Unknown" : \
1955 "(Invalid)")
1956
1957
1958
1959#define DRX_STR_BANDWIDTH(x) ( \
1960 (x == DRX_BANDWIDTH_8MHZ) ? "8 MHz" : \
1961 (x == DRX_BANDWIDTH_7MHZ) ? "7 MHz" : \
1962 (x == DRX_BANDWIDTH_6MHZ) ? "6 MHz" : \
1963 (x == DRX_BANDWIDTH_AUTO) ? "Auto" : \
1964 (x == DRX_BANDWIDTH_UNKNOWN) ? "Unknown" : \
1965 "(Invalid)")
1966#define DRX_STR_FFTMODE(x) ( \
1967 (x == DRX_FFTMODE_2K) ? "2k" : \
1968 (x == DRX_FFTMODE_4K) ? "4k" : \
1969 (x == DRX_FFTMODE_8K) ? "8k" : \
1970 (x == DRX_FFTMODE_AUTO) ? "Auto" : \
1971 (x == DRX_FFTMODE_UNKNOWN) ? "Unknown" : \
1972 "(Invalid)")
1973#define DRX_STR_GUARD(x) ( \
1974 (x == DRX_GUARD_1DIV32) ? "1/32nd" : \
1975 (x == DRX_GUARD_1DIV16) ? "1/16th" : \
1976 (x == DRX_GUARD_1DIV8) ? "1/8th" : \
1977 (x == DRX_GUARD_1DIV4) ? "1/4th" : \
1978 (x == DRX_GUARD_AUTO) ? "Auto" : \
1979 (x == DRX_GUARD_UNKNOWN) ? "Unknown" : \
1980 "(Invalid)")
1981#define DRX_STR_CONSTELLATION(x) ( \
1982 (x == DRX_CONSTELLATION_BPSK) ? "BPSK" : \
1983 (x == DRX_CONSTELLATION_QPSK) ? "QPSK" : \
1984 (x == DRX_CONSTELLATION_PSK8) ? "PSK8" : \
1985 (x == DRX_CONSTELLATION_QAM16) ? "QAM16" : \
1986 (x == DRX_CONSTELLATION_QAM32) ? "QAM32" : \
1987 (x == DRX_CONSTELLATION_QAM64) ? "QAM64" : \
1988 (x == DRX_CONSTELLATION_QAM128) ? "QAM128" : \
1989 (x == DRX_CONSTELLATION_QAM256) ? "QAM256" : \
1990 (x == DRX_CONSTELLATION_QAM512) ? "QAM512" : \
1991 (x == DRX_CONSTELLATION_QAM1024) ? "QAM1024" : \
1992 (x == DRX_CONSTELLATION_QPSK_NR) ? "QPSK_NR" : \
1993 (x == DRX_CONSTELLATION_AUTO) ? "Auto" : \
1994 (x == DRX_CONSTELLATION_UNKNOWN) ? "Unknown" : \
1995 "(Invalid)")
1996#define DRX_STR_CODERATE(x) ( \
1997 (x == DRX_CODERATE_1DIV2) ? "1/2nd" : \
1998 (x == DRX_CODERATE_2DIV3) ? "2/3rd" : \
1999 (x == DRX_CODERATE_3DIV4) ? "3/4th" : \
2000 (x == DRX_CODERATE_5DIV6) ? "5/6th" : \
2001 (x == DRX_CODERATE_7DIV8) ? "7/8th" : \
2002 (x == DRX_CODERATE_AUTO) ? "Auto" : \
2003 (x == DRX_CODERATE_UNKNOWN) ? "Unknown" : \
2004 "(Invalid)")
2005#define DRX_STR_HIERARCHY(x) ( \
2006 (x == DRX_HIERARCHY_NONE) ? "None" : \
2007 (x == DRX_HIERARCHY_ALPHA1) ? "Alpha=1" : \
2008 (x == DRX_HIERARCHY_ALPHA2) ? "Alpha=2" : \
2009 (x == DRX_HIERARCHY_ALPHA4) ? "Alpha=4" : \
2010 (x == DRX_HIERARCHY_AUTO) ? "Auto" : \
2011 (x == DRX_HIERARCHY_UNKNOWN) ? "Unknown" : \
2012 "(Invalid)")
2013#define DRX_STR_PRIORITY(x) ( \
2014 (x == DRX_PRIORITY_LOW) ? "Low" : \
2015 (x == DRX_PRIORITY_HIGH) ? "High" : \
2016 (x == DRX_PRIORITY_UNKNOWN) ? "Unknown" : \
2017 "(Invalid)")
2018#define DRX_STR_MIRROR(x) ( \
2019 (x == DRX_MIRROR_NO) ? "Normal" : \
2020 (x == DRX_MIRROR_YES) ? "Mirrored" : \
2021 (x == DRX_MIRROR_AUTO) ? "Auto" : \
2022 (x == DRX_MIRROR_UNKNOWN) ? "Unknown" : \
2023 "(Invalid)")
2024#define DRX_STR_CLASSIFICATION(x) ( \
2025 (x == DRX_CLASSIFICATION_GAUSS) ? "Gaussion" : \
2026 (x == DRX_CLASSIFICATION_HVY_GAUSS) ? "Heavy Gaussion" : \
2027 (x == DRX_CLASSIFICATION_COCHANNEL) ? "Co-channel" : \
2028 (x == DRX_CLASSIFICATION_STATIC) ? "Static echo" : \
2029 (x == DRX_CLASSIFICATION_MOVING) ? "Moving echo" : \
2030 (x == DRX_CLASSIFICATION_ZERODB) ? "Zero dB echo" : \
2031 (x == DRX_CLASSIFICATION_UNKNOWN) ? "Unknown" : \
2032 (x == DRX_CLASSIFICATION_AUTO) ? "Auto" : \
2033 "(Invalid)")
2034
2035#define DRX_STR_INTERLEAVEMODE(x) ( \
2036 (x == DRX_INTERLEAVEMODE_I128_J1) ? "I128_J1" : \
2037 (x == DRX_INTERLEAVEMODE_I128_J1_V2) ? "I128_J1_V2" : \
2038 (x == DRX_INTERLEAVEMODE_I128_J2) ? "I128_J2" : \
2039 (x == DRX_INTERLEAVEMODE_I64_J2) ? "I64_J2" : \
2040 (x == DRX_INTERLEAVEMODE_I128_J3) ? "I128_J3" : \
2041 (x == DRX_INTERLEAVEMODE_I32_J4) ? "I32_J4" : \
2042 (x == DRX_INTERLEAVEMODE_I128_J4) ? "I128_J4" : \
2043 (x == DRX_INTERLEAVEMODE_I16_J8) ? "I16_J8" : \
2044 (x == DRX_INTERLEAVEMODE_I128_J5) ? "I128_J5" : \
2045 (x == DRX_INTERLEAVEMODE_I8_J16) ? "I8_J16" : \
2046 (x == DRX_INTERLEAVEMODE_I128_J6) ? "I128_J6" : \
2047 (x == DRX_INTERLEAVEMODE_RESERVED_11) ? "Reserved 11" : \
2048 (x == DRX_INTERLEAVEMODE_I128_J7) ? "I128_J7" : \
2049 (x == DRX_INTERLEAVEMODE_RESERVED_13) ? "Reserved 13" : \
2050 (x == DRX_INTERLEAVEMODE_I128_J8) ? "I128_J8" : \
2051 (x == DRX_INTERLEAVEMODE_RESERVED_15) ? "Reserved 15" : \
2052 (x == DRX_INTERLEAVEMODE_I12_J17) ? "I12_J17" : \
2053 (x == DRX_INTERLEAVEMODE_I5_J4) ? "I5_J4" : \
2054 (x == DRX_INTERLEAVEMODE_B52_M240) ? "B52_M240" : \
2055 (x == DRX_INTERLEAVEMODE_B52_M720) ? "B52_M720" : \
2056 (x == DRX_INTERLEAVEMODE_B52_M48) ? "B52_M48" : \
2057 (x == DRX_INTERLEAVEMODE_B52_M0) ? "B52_M0" : \
2058 (x == DRX_INTERLEAVEMODE_UNKNOWN) ? "Unknown" : \
2059 (x == DRX_INTERLEAVEMODE_AUTO) ? "Auto" : \
2060 "(Invalid)")
2061
2062#define DRX_STR_LDPC(x) ( \
2063 (x == DRX_LDPC_0_4) ? "0.4" : \
2064 (x == DRX_LDPC_0_6) ? "0.6" : \
2065 (x == DRX_LDPC_0_8) ? "0.8" : \
2066 (x == DRX_LDPC_AUTO) ? "Auto" : \
2067 (x == DRX_LDPC_UNKNOWN) ? "Unknown" : \
2068 "(Invalid)")
2069
2070#define DRX_STR_CARRIER(x) ( \
2071 (x == DRX_CARRIER_MULTI) ? "Multi" : \
2072 (x == DRX_CARRIER_SINGLE) ? "Single" : \
2073 (x == DRX_CARRIER_AUTO) ? "Auto" : \
2074 (x == DRX_CARRIER_UNKNOWN) ? "Unknown" : \
2075 "(Invalid)")
2076
2077#define DRX_STR_FRAMEMODE(x) ( \
2078 (x == DRX_FRAMEMODE_420) ? "420" : \
2079 (x == DRX_FRAMEMODE_595) ? "595" : \
2080 (x == DRX_FRAMEMODE_945) ? "945" : \
2081 (x == DRX_FRAMEMODE_420_FIXED_PN) ? "420 with fixed PN" : \
2082 (x == DRX_FRAMEMODE_945_FIXED_PN) ? "945 with fixed PN" : \
2083 (x == DRX_FRAMEMODE_AUTO) ? "Auto" : \
2084 (x == DRX_FRAMEMODE_UNKNOWN) ? "Unknown" : \
2085 "(Invalid)")
2086
2087#define DRX_STR_PILOT(x) ( \
2088 (x == DRX_PILOT_ON) ? "On" : \
2089 (x == DRX_PILOT_OFF) ? "Off" : \
2090 (x == DRX_PILOT_AUTO) ? "Auto" : \
2091 (x == DRX_PILOT_UNKNOWN) ? "Unknown" : \
2092 "(Invalid)")
2093
2094
2095#define DRX_STR_TPS_FRAME(x) ( \
2096 (x == DRX_TPS_FRAME1) ? "Frame1" : \
2097 (x == DRX_TPS_FRAME2) ? "Frame2" : \
2098 (x == DRX_TPS_FRAME3) ? "Frame3" : \
2099 (x == DRX_TPS_FRAME4) ? "Frame4" : \
2100 (x == DRX_TPS_FRAME_UNKNOWN) ? "Unknown" : \
2101 "(Invalid)")
2102
2103
2104
2105#define DRX_STR_LOCKSTATUS(x) ( \
2106 (x == DRX_NEVER_LOCK) ? "Never" : \
2107 (x == DRX_NOT_LOCKED) ? "No" : \
2108 (x == DRX_LOCKED) ? "Locked" : \
2109 (x == DRX_LOCK_STATE_1) ? "Lock state 1" : \
2110 (x == DRX_LOCK_STATE_2) ? "Lock state 2" : \
2111 (x == DRX_LOCK_STATE_3) ? "Lock state 3" : \
2112 (x == DRX_LOCK_STATE_4) ? "Lock state 4" : \
2113 (x == DRX_LOCK_STATE_5) ? "Lock state 5" : \
2114 (x == DRX_LOCK_STATE_6) ? "Lock state 6" : \
2115 (x == DRX_LOCK_STATE_7) ? "Lock state 7" : \
2116 (x == DRX_LOCK_STATE_8) ? "Lock state 8" : \
2117 (x == DRX_LOCK_STATE_9) ? "Lock state 9" : \
2118 "(Invalid)")
2119
2120
2121#define DRX_STR_MODULE(x) ( \
2122 (x == DRX_MODULE_DEVICE) ? "Device" : \
2123 (x == DRX_MODULE_MICROCODE) ? "Microcode" : \
2124 (x == DRX_MODULE_DRIVERCORE) ? "CoreDriver" : \
2125 (x == DRX_MODULE_DEVICEDRIVER) ? "DeviceDriver" : \
2126 (x == DRX_MODULE_BSP_I2C) ? "BSP I2C" : \
2127 (x == DRX_MODULE_BSP_TUNER) ? "BSP Tuner" : \
2128 (x == DRX_MODULE_BSP_HOST) ? "BSP Host" : \
2129 (x == DRX_MODULE_DAP) ? "Data Access Protocol" : \
2130 (x == DRX_MODULE_UNKNOWN) ? "Unknown" : \
2131 "(Invalid)")
2132
2133#define DRX_STR_POWER_MODE(x) ( \
2134 (x == DRX_POWER_UP) ? "DRX_POWER_UP " : \
2135 (x == DRX_POWER_MODE_1) ? "DRX_POWER_MODE_1" : \
2136 (x == DRX_POWER_MODE_2) ? "DRX_POWER_MODE_2" : \
2137 (x == DRX_POWER_MODE_3) ? "DRX_POWER_MODE_3" : \
2138 (x == DRX_POWER_MODE_4) ? "DRX_POWER_MODE_4" : \
2139 (x == DRX_POWER_MODE_5) ? "DRX_POWER_MODE_5" : \
2140 (x == DRX_POWER_MODE_6) ? "DRX_POWER_MODE_6" : \
2141 (x == DRX_POWER_MODE_7) ? "DRX_POWER_MODE_7" : \
2142 (x == DRX_POWER_MODE_8) ? "DRX_POWER_MODE_8" : \
2143 (x == DRX_POWER_MODE_9) ? "DRX_POWER_MODE_9" : \
2144 (x == DRX_POWER_MODE_10) ? "DRX_POWER_MODE_10" : \
2145 (x == DRX_POWER_MODE_11) ? "DRX_POWER_MODE_11" : \
2146 (x == DRX_POWER_MODE_12) ? "DRX_POWER_MODE_12" : \
2147 (x == DRX_POWER_MODE_13) ? "DRX_POWER_MODE_13" : \
2148 (x == DRX_POWER_MODE_14) ? "DRX_POWER_MODE_14" : \
2149 (x == DRX_POWER_MODE_15) ? "DRX_POWER_MODE_15" : \
2150 (x == DRX_POWER_MODE_16) ? "DRX_POWER_MODE_16" : \
2151 (x == DRX_POWER_DOWN) ? "DRX_POWER_DOWN " : \
2152 "(Invalid)")
2153
2154#define DRX_STR_OOB_STANDARD(x) ( \
2155 (x == DRX_OOB_MODE_A) ? "ANSI 55-1 " : \
2156 (x == DRX_OOB_MODE_B_GRADE_A) ? "ANSI 55-2 A" : \
2157 (x == DRX_OOB_MODE_B_GRADE_B) ? "ANSI 55-2 B" : \
2158 "(Invalid)")
2159
2160#define DRX_STR_AUD_STANDARD(x) ( \
2161 (x == DRX_AUD_STANDARD_BTSC) ? "BTSC" : \
2162 (x == DRX_AUD_STANDARD_A2) ? "A2" : \
2163 (x == DRX_AUD_STANDARD_EIAJ) ? "EIAJ" : \
2164 (x == DRX_AUD_STANDARD_FM_STEREO) ? "FM Stereo" : \
2165 (x == DRX_AUD_STANDARD_AUTO) ? "Auto" : \
2166 (x == DRX_AUD_STANDARD_M_MONO) ? "M-Standard Mono" : \
2167 (x == DRX_AUD_STANDARD_D_K_MONO) ? "D/K Mono FM" : \
2168 (x == DRX_AUD_STANDARD_BG_FM) ? "B/G-Dual Carrier FM (A2)" : \
2169 (x == DRX_AUD_STANDARD_D_K1) ? "D/K1-Dual Carrier FM" : \
2170 (x == DRX_AUD_STANDARD_D_K2) ? "D/K2-Dual Carrier FM" : \
2171 (x == DRX_AUD_STANDARD_D_K3) ? "D/K3-Dual Carrier FM" : \
2172 (x == DRX_AUD_STANDARD_BG_NICAM_FM) ? "B/G-NICAM-FM" : \
2173 (x == DRX_AUD_STANDARD_L_NICAM_AM) ? "L-NICAM-AM" : \
2174 (x == DRX_AUD_STANDARD_I_NICAM_FM) ? "I-NICAM-FM" : \
2175 (x == DRX_AUD_STANDARD_D_K_NICAM_FM) ? "D/K-NICAM-FM" : \
2176 (x == DRX_AUD_STANDARD_UNKNOWN) ? "Unknown" : \
2177 "(Invalid)")
2178#define DRX_STR_AUD_STEREO(x) ( \
2179 (x == true) ? "Stereo" : \
2180 (x == false) ? "Mono" : \
2181 "(Invalid)")
2182
2183#define DRX_STR_AUD_SAP(x) ( \
2184 (x == true) ? "Present" : \
2185 (x == false) ? "Not present" : \
2186 "(Invalid)")
2187
2188#define DRX_STR_AUD_CARRIER(x) ( \
2189 (x == true) ? "Present" : \
2190 (x == false) ? "Not present" : \
2191 "(Invalid)")
2192
2193#define DRX_STR_AUD_RDS(x) ( \
2194 (x == true) ? "Available" : \
2195 (x == false) ? "Not Available" : \
2196 "(Invalid)")
2197
2198#define DRX_STR_AUD_NICAM_STATUS(x) ( \
2199 (x == DRX_AUD_NICAM_DETECTED) ? "Detected" : \
2200 (x == DRX_AUD_NICAM_NOT_DETECTED) ? "Not detected" : \
2201 (x == DRX_AUD_NICAM_BAD) ? "Bad" : \
2202 "(Invalid)")
2203
2204#define DRX_STR_RDS_VALID(x) ( \
2205 (x == true) ? "Valid" : \
2206 (x == false) ? "Not Valid" : \
2207 "(Invalid)")
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224#define DRX_ATTR_MCRECORD(d) ((d)->my_common_attr->mcversion)
2225#define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->my_common_attr->mirror_freq_spect)
2226#define DRX_ATTR_CURRENTPOWERMODE(d)((d)->my_common_attr->current_power_mode)
2227#define DRX_ATTR_ISOPENED(d) ((d)->my_common_attr->is_opened)
2228#define DRX_ATTR_USEBOOTLOADER(d) ((d)->my_common_attr->use_bootloader)
2229#define DRX_ATTR_CURRENTSTANDARD(d) ((d)->my_common_attr->current_standard)
2230#define DRX_ATTR_PREVSTANDARD(d) ((d)->my_common_attr->prev_standard)
2231#define DRX_ATTR_CACHESTANDARD(d) ((d)->my_common_attr->di_cache_standard)
2232#define DRX_ATTR_CURRENTCHANNEL(d) ((d)->my_common_attr->current_channel)
2233#define DRX_ATTR_MICROCODE(d) ((d)->my_common_attr->microcode)
2234#define DRX_ATTR_VERIFYMICROCODE(d) ((d)->my_common_attr->verify_microcode)
2235#define DRX_ATTR_CAPABILITIES(d) ((d)->my_common_attr->capabilities)
2236#define DRX_ATTR_PRODUCTID(d) ((d)->my_common_attr->product_id)
2237#define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->my_common_attr->intermediate_freq)
2238#define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->my_common_attr->sys_clock_freq)
2239#define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->my_common_attr->tuner_rf_agc_pol)
2240#define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->my_common_attr->tuner_if_agc_pol)
2241#define DRX_ATTR_TUNERSLOWMODE(d) ((d)->my_common_attr->tuner_slow_mode)
2242#define DRX_ATTR_TUNERSPORTNR(d) ((d)->my_common_attr->tuner_port_nr)
2243#define DRX_ATTR_I2CADDR(d) ((d)->my_i2c_dev_addr->i2c_addr)
2244#define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id)
2245#define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD)
2246
2247
2248
2249
2250
2251#define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type) \
2252 do { \
2253 struct drx_cfg config; \
2254 data_type cfg_data; \
2255 config.cfg_type = cfg_name; \
2256 config.cfg_data = &cfg_data; \
2257 cfg_data = value; \
2258 drx_ctrl(demod, DRX_CTRL_SET_CFG, &config); \
2259 } while (0)
2260
2261#define DRX_ACCESSMACRO_GET(demod, value, cfg_name, data_type, error_value) \
2262 do { \
2263 int cfg_status; \
2264 struct drx_cfg config; \
2265 data_type cfg_data; \
2266 config.cfg_type = cfg_name; \
2267 config.cfg_data = &cfg_data; \
2268 cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config); \
2269 if (cfg_status == 0) { \
2270 value = cfg_data; \
2271 } else { \
2272 value = (data_type)error_value; \
2273 } \
2274 } while (0)
2275
2276
2277
2278#ifndef DRX_XS_CFG_BASE
2279#define DRX_XS_CFG_BASE (500)
2280#endif
2281
2282#define DRX_XS_CFG_PRESET (DRX_XS_CFG_BASE + 0)
2283#define DRX_XS_CFG_AUD_BTSC_DETECT (DRX_XS_CFG_BASE + 1)
2284#define DRX_XS_CFG_QAM_LOCKRANGE (DRX_XS_CFG_BASE + 2)
2285
2286
2287
2288#define DRX_SET_PRESET(d, x) \
2289 DRX_ACCESSMACRO_SET((d), (x), DRX_XS_CFG_PRESET, char*)
2290#define DRX_GET_PRESET(d, x) \
2291 DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR")
2292
2293#define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET((d), (x), \
2294 DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect)
2295#define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET((d), (x), \
2296 DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect, DRX_UNKNOWN)
2297
2298#define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET((d), (x), \
2299 DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range)
2300#define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \
2301 DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range, DRX_UNKNOWN)
2302
2303
2304
2305
2306
2307
2308#define DRX_ISATVSTD(std) (((std) == DRX_STANDARD_PAL_SECAM_BG) || \
2309 ((std) == DRX_STANDARD_PAL_SECAM_DK) || \
2310 ((std) == DRX_STANDARD_PAL_SECAM_I) || \
2311 ((std) == DRX_STANDARD_PAL_SECAM_L) || \
2312 ((std) == DRX_STANDARD_PAL_SECAM_LP) || \
2313 ((std) == DRX_STANDARD_NTSC) || \
2314 ((std) == DRX_STANDARD_FM))
2315
2316
2317
2318
2319
2320
2321#define DRX_ISQAMSTD(std) (((std) == DRX_STANDARD_ITU_A) || \
2322 ((std) == DRX_STANDARD_ITU_B) || \
2323 ((std) == DRX_STANDARD_ITU_C) || \
2324 ((std) == DRX_STANDARD_ITU_D))
2325
2326
2327
2328
2329
2330
2331#define DRX_ISVSBSTD(std) ((std) == DRX_STANDARD_8VSB)
2332
2333
2334
2335
2336
2337
2338#define DRX_ISDVBTSTD(std) ((std) == DRX_STANDARD_DVBT)
2339
2340
2341
2342
2343#endif
2344