LXR linux/drivers/media/i2c/smiapp-pll.h

   1/*
   2 * drivers/media/i2c/smiapp-pll.h
   3 *
   4 * Generic driver for SMIA/SMIA++ compliant camera modules
   5 *
   6 * Copyright (C) 2012 Nokia Corporation
   7 * Contact: Sakari Ailus <sakari.ailus@iki.fi>
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License
  11 * version 2 as published by the Free Software Foundation.
  12 *
  13 * This program is distributed in the hope that it will be useful, but
  14 * WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16 * General Public License for more details.
  17 */
  18
  19#ifndef SMIAPP_PLL_H
  20#define SMIAPP_PLL_H
  21
  22/* CSI-2 or CCP-2 */
  23#define SMIAPP_PLL_BUS_TYPE_CSI2                                0x00
  24#define SMIAPP_PLL_BUS_TYPE_PARALLEL                            0x01
  25
  26/* op pix clock is for all lanes in total normally */
  27#define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE                   (1 << 0)
  28#define SMIAPP_PLL_FLAG_NO_OP_CLOCKS                            (1 << 1)
  29
  30struct smiapp_pll_branch {
  31        uint16_t sys_clk_div;
  32        uint16_t pix_clk_div;
  33        uint32_t sys_clk_freq_hz;
  34        uint32_t pix_clk_freq_hz;
  35};
  36
  37struct smiapp_pll {
  38        /* input values */
  39        uint8_t bus_type;
  40        union {
  41                struct {
  42                        uint8_t lanes;
  43                } csi2;
  44                struct {
  45                        uint8_t bus_width;
  46                } parallel;
  47        };
  48        unsigned long flags;
  49        uint8_t binning_horizontal;
  50        uint8_t binning_vertical;
  51        uint8_t scale_m;
  52        uint8_t scale_n;
  53        uint8_t bits_per_pixel;
  54        uint32_t link_freq;
  55        uint32_t ext_clk_freq_hz;
  56
  57        /* output values */
  58        uint16_t pre_pll_clk_div;
  59        uint16_t pll_multiplier;
  60        uint32_t pll_ip_clk_freq_hz;
  61        uint32_t pll_op_clk_freq_hz;
  62        struct smiapp_pll_branch vt;
  63        struct smiapp_pll_branch op;
  64
  65        uint32_t pixel_rate_csi;
  66        uint32_t pixel_rate_pixel_array;
  67};
  68
  69struct smiapp_pll_branch_limits {
  70        uint16_t min_sys_clk_div;
  71        uint16_t max_sys_clk_div;
  72        uint32_t min_sys_clk_freq_hz;
  73        uint32_t max_sys_clk_freq_hz;
  74        uint16_t min_pix_clk_div;
  75        uint16_t max_pix_clk_div;
  76        uint32_t min_pix_clk_freq_hz;
  77        uint32_t max_pix_clk_freq_hz;
  78};
  79
  80struct smiapp_pll_limits {
  81        /* Strict PLL limits */
  82        uint32_t min_ext_clk_freq_hz;
  83        uint32_t max_ext_clk_freq_hz;
  84        uint16_t min_pre_pll_clk_div;
  85        uint16_t max_pre_pll_clk_div;
  86        uint32_t min_pll_ip_freq_hz;
  87        uint32_t max_pll_ip_freq_hz;
  88        uint16_t min_pll_multiplier;
  89        uint16_t max_pll_multiplier;
  90        uint32_t min_pll_op_freq_hz;
  91        uint32_t max_pll_op_freq_hz;
  92
  93        struct smiapp_pll_branch_limits vt;
  94        struct smiapp_pll_branch_limits op;
  95
  96        /* Other relevant limits */
  97        uint32_t min_line_length_pck_bin;
  98        uint32_t min_line_length_pck;
  99};
 100
 101struct device;
 102
 103int smiapp_pll_calculate(struct device *dev,
 104                         const struct smiapp_pll_limits *limits,
 105                         struct smiapp_pll *pll);
 106
 107#endif /* SMIAPP_PLL_H */
 108