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21#include <linux/spinlock.h>
22
23
24
25#define ENE_STATUS 0
26#define ENE_ADDR_HI 1
27#define ENE_ADDR_LO 2
28#define ENE_IO 3
29#define ENE_IO_SIZE 4
30
31
32#define ENE_FW_SAMPLE_BUFFER 0xF8F0
33#define ENE_FW_SAMPLE_SPACE 0x80
34#define ENE_FW_PACKET_SIZE 4
35
36
37#define ENE_FW1 0xF8F8
38#define ENE_FW1_ENABLE 0x01
39#define ENE_FW1_TXIRQ 0x02
40#define ENE_FW1_HAS_EXTRA_BUF 0x04
41#define ENE_FW1_EXTRA_BUF_HND 0x08
42#define ENE_FW1_LED_ON 0x10
43
44#define ENE_FW1_WPATTERN 0x20
45#define ENE_FW1_WAKE 0x40
46#define ENE_FW1_IRQ 0x80
47
48
49#define ENE_FW2 0xF8F9
50#define ENE_FW2_BUF_WPTR 0x01
51#define ENE_FW2_RXIRQ 0x04
52#define ENE_FW2_GP0A 0x08
53#define ENE_FW2_EMMITER1_CONN 0x10
54#define ENE_FW2_EMMITER2_CONN 0x20
55
56#define ENE_FW2_FAN_INPUT 0x40
57#define ENE_FW2_LEARNING 0x80
58
59
60#define ENE_FW_RX_POINTER 0xF8FA
61
62
63#define ENE_FW_SMPL_BUF_FAN 0xF8FB
64#define ENE_FW_SMPL_BUF_FAN_PLS 0x8000
65#define ENE_FW_SMPL_BUF_FAN_MSK 0x0FFF
66#define ENE_FW_SAMPLE_PERIOD_FAN 61
67
68
69#define ENE_GPIOFS1 0xFC01
70#define ENE_GPIOFS1_GPIO0D 0x20
71#define ENE_GPIOFS8 0xFC08
72#define ENE_GPIOFS8_GPIO41 0x02
73
74
75#define ENEB_IRQ 0xFD09
76#define ENEB_IRQ_UNK1 0xFD17
77#define ENEB_IRQ_STATUS 0xFD80
78#define ENEB_IRQ_STATUS_IR 0x20
79
80
81#define ENE_FAN_AS_IN1 0xFE30
82#define ENE_FAN_AS_IN1_EN 0xCD
83#define ENE_FAN_AS_IN2 0xFE31
84#define ENE_FAN_AS_IN2_EN 0x03
85
86
87#define ENE_IRQ 0xFE9B
88#define ENE_IRQ_MASK 0x0F
89#define ENE_IRQ_UNK_EN 0x10
90#define ENE_IRQ_STATUS 0x20
91
92
93#define ENE_CIRCFG 0xFEC0
94#define ENE_CIRCFG_RX_EN 0x01
95#define ENE_CIRCFG_RX_IRQ 0x02
96#define ENE_CIRCFG_REV_POL 0x04
97#define ENE_CIRCFG_CARR_DEMOD 0x08
98
99#define ENE_CIRCFG_TX_EN 0x10
100#define ENE_CIRCFG_TX_IRQ 0x20
101#define ENE_CIRCFG_TX_POL_REV 0x40
102#define ENE_CIRCFG_TX_CARR 0x80
103
104
105#define ENE_CIRCFG2 0xFEC1
106#define ENE_CIRCFG2_RLC 0x00
107#define ENE_CIRCFG2_RC5 0x01
108#define ENE_CIRCFG2_RC6 0x02
109#define ENE_CIRCFG2_NEC 0x03
110#define ENE_CIRCFG2_CARR_DETECT 0x10
111#define ENE_CIRCFG2_GPIO0A 0x20
112#define ENE_CIRCFG2_FAST_SAMPL1 0x40
113#define ENE_CIRCFG2_FAST_SAMPL2 0x80
114
115
116#define ENE_CIRPF 0xFEC2
117#define ENE_CIRHIGH 0xFEC3
118#define ENE_CIRBIT 0xFEC4
119#define ENE_CIRSTART 0xFEC5
120#define ENE_CIRSTART2 0xFEC6
121
122
123#define ENE_CIRDAT_IN 0xFEC7
124
125
126
127#define ENE_CIRRLC_CFG 0xFEC8
128#define ENE_CIRRLC_CFG_OVERFLOW 0x80
129#define ENE_DEFAULT_SAMPLE_PERIOD 50
130
131
132#define ENE_CIRRLC_OUT0 0xFEC9
133#define ENE_CIRRLC_OUT1 0xFECA
134#define ENE_CIRRLC_OUT_PULSE 0x80
135#define ENE_CIRRLC_OUT_MASK 0x7F
136
137
138
139
140
141
142#define ENE_CIRCAR_PULS 0xFECB
143
144
145#define ENE_CIRCAR_PRD 0xFECC
146#define ENE_CIRCAR_PRD_VALID 0x80
147
148
149#define ENE_CIRCAR_HPRD 0xFECD
150
151
152#define ENE_CIRMOD_PRD 0xFECE
153#define ENE_CIRMOD_PRD_POL 0x80
154
155#define ENE_CIRMOD_PRD_MAX 0x7F
156#define ENE_CIRMOD_PRD_MIN 0x02
157
158
159#define ENE_CIRMOD_HPRD 0xFECF
160
161
162#define ENE_ECHV 0xFF00
163#define ENE_PLLFRH 0xFF16
164#define ENE_PLLFRL 0xFF17
165#define ENE_DEFAULT_PLL_FREQ 1000
166
167#define ENE_ECSTS 0xFF1D
168#define ENE_ECSTS_RSRVD 0x04
169
170#define ENE_ECVER_MAJOR 0xFF1E
171#define ENE_ECVER_MINOR 0xFF1F
172#define ENE_HW_VER_OLD 0xFD00
173
174
175
176#define ENE_DRIVER_NAME "ene_ir"
177
178#define ENE_IRQ_RX 1
179#define ENE_IRQ_TX 2
180
181#define ENE_HW_B 1
182#define ENE_HW_C 2
183#define ENE_HW_D 3
184
185#define __dbg(level, format, ...) \
186do { \
187 if (debug >= level) \
188 pr_info(format "\n", ## __VA_ARGS__); \
189} while (0)
190
191#define dbg(format, ...) __dbg(1, format, ## __VA_ARGS__)
192#define dbg_verbose(format, ...) __dbg(2, format, ## __VA_ARGS__)
193#define dbg_regs(format, ...) __dbg(3, format, ## __VA_ARGS__)
194
195struct ene_device {
196 struct pnp_dev *pnp_dev;
197 struct rc_dev *rdev;
198
199
200 long hw_io;
201 int irq;
202 spinlock_t hw_lock;
203
204
205 int hw_revision;
206 bool hw_use_gpio_0a;
207 bool hw_extra_buffer;
208 bool hw_fan_input;
209 bool hw_learning_and_tx_capable;
210 int pll_freq;
211 int buffer_len;
212
213
214 int extra_buf1_address;
215 int extra_buf1_len;
216 int extra_buf2_address;
217 int extra_buf2_len;
218
219
220 int r_pointer;
221 int w_pointer;
222 bool rx_fan_input_inuse;
223 int tx_reg;
224 u8 saved_conf1;
225 unsigned int tx_sample;
226 bool tx_sample_pulse;
227
228
229 unsigned *tx_buffer;
230 int tx_pos;
231 int tx_len;
232 int tx_done;
233
234 struct completion tx_complete;
235 struct timer_list tx_sim_timer;
236
237
238 int tx_period;
239 int tx_duty_cycle;
240 int transmitter_mask;
241
242
243 bool learning_mode_enabled;
244 bool carrier_detect_enabled;
245 int rx_period_adjust;
246 bool rx_enabled;
247};
248
249static int ene_irq_status(struct ene_device *dev);
250static void ene_rx_read_hw_pointer(struct ene_device *dev);
251