linux/drivers/net/ethernet/aurora/nb8800.c
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   1/*
   2 * Copyright (C) 2015 Mans Rullgard <mans@mansr.com>
   3 *
   4 * Mostly rewritten, based on driver from Sigma Designs.  Original
   5 * copyright notice below.
   6 *
   7 *
   8 * Driver for tangox SMP864x/SMP865x/SMP867x/SMP868x builtin Ethernet Mac.
   9 *
  10 * Copyright (C) 2005 Maxime Bizon <mbizon@freebox.fr>
  11 *
  12 * This program is free software; you can redistribute it and/or modify
  13 * it under the terms of the GNU General Public License as published by
  14 * the Free Software Foundation; either version 2 of the License, or
  15 * (at your option) any later version.
  16 *
  17 * This program is distributed in the hope that it will be useful,
  18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 * GNU General Public License for more details.
  21 */
  22
  23#include <linux/module.h>
  24#include <linux/etherdevice.h>
  25#include <linux/delay.h>
  26#include <linux/ethtool.h>
  27#include <linux/interrupt.h>
  28#include <linux/platform_device.h>
  29#include <linux/of_device.h>
  30#include <linux/of_mdio.h>
  31#include <linux/of_net.h>
  32#include <linux/dma-mapping.h>
  33#include <linux/phy.h>
  34#include <linux/cache.h>
  35#include <linux/jiffies.h>
  36#include <linux/io.h>
  37#include <linux/iopoll.h>
  38#include <asm/barrier.h>
  39
  40#include "nb8800.h"
  41
  42static void nb8800_tx_done(struct net_device *dev);
  43static int nb8800_dma_stop(struct net_device *dev);
  44
  45static inline u8 nb8800_readb(struct nb8800_priv *priv, int reg)
  46{
  47        return readb_relaxed(priv->base + reg);
  48}
  49
  50static inline u32 nb8800_readl(struct nb8800_priv *priv, int reg)
  51{
  52        return readl_relaxed(priv->base + reg);
  53}
  54
  55static inline void nb8800_writeb(struct nb8800_priv *priv, int reg, u8 val)
  56{
  57        writeb_relaxed(val, priv->base + reg);
  58}
  59
  60static inline void nb8800_writew(struct nb8800_priv *priv, int reg, u16 val)
  61{
  62        writew_relaxed(val, priv->base + reg);
  63}
  64
  65static inline void nb8800_writel(struct nb8800_priv *priv, int reg, u32 val)
  66{
  67        writel_relaxed(val, priv->base + reg);
  68}
  69
  70static inline void nb8800_maskb(struct nb8800_priv *priv, int reg,
  71                                u32 mask, u32 val)
  72{
  73        u32 old = nb8800_readb(priv, reg);
  74        u32 new = (old & ~mask) | (val & mask);
  75
  76        if (new != old)
  77                nb8800_writeb(priv, reg, new);
  78}
  79
  80static inline void nb8800_maskl(struct nb8800_priv *priv, int reg,
  81                                u32 mask, u32 val)
  82{
  83        u32 old = nb8800_readl(priv, reg);
  84        u32 new = (old & ~mask) | (val & mask);
  85
  86        if (new != old)
  87                nb8800_writel(priv, reg, new);
  88}
  89
  90static inline void nb8800_modb(struct nb8800_priv *priv, int reg, u8 bits,
  91                               bool set)
  92{
  93        nb8800_maskb(priv, reg, bits, set ? bits : 0);
  94}
  95
  96static inline void nb8800_setb(struct nb8800_priv *priv, int reg, u8 bits)
  97{
  98        nb8800_maskb(priv, reg, bits, bits);
  99}
 100
 101static inline void nb8800_clearb(struct nb8800_priv *priv, int reg, u8 bits)
 102{
 103        nb8800_maskb(priv, reg, bits, 0);
 104}
 105
 106static inline void nb8800_modl(struct nb8800_priv *priv, int reg, u32 bits,
 107                               bool set)
 108{
 109        nb8800_maskl(priv, reg, bits, set ? bits : 0);
 110}
 111
 112static inline void nb8800_setl(struct nb8800_priv *priv, int reg, u32 bits)
 113{
 114        nb8800_maskl(priv, reg, bits, bits);
 115}
 116
 117static inline void nb8800_clearl(struct nb8800_priv *priv, int reg, u32 bits)
 118{
 119        nb8800_maskl(priv, reg, bits, 0);
 120}
 121
 122static int nb8800_mdio_wait(struct mii_bus *bus)
 123{
 124        struct nb8800_priv *priv = bus->priv;
 125        u32 val;
 126
 127        return readl_poll_timeout_atomic(priv->base + NB8800_MDIO_CMD,
 128                                         val, !(val & MDIO_CMD_GO), 1, 1000);
 129}
 130
 131static int nb8800_mdio_cmd(struct mii_bus *bus, u32 cmd)
 132{
 133        struct nb8800_priv *priv = bus->priv;
 134        int err;
 135
 136        err = nb8800_mdio_wait(bus);
 137        if (err)
 138                return err;
 139
 140        nb8800_writel(priv, NB8800_MDIO_CMD, cmd);
 141        udelay(10);
 142        nb8800_writel(priv, NB8800_MDIO_CMD, cmd | MDIO_CMD_GO);
 143
 144        return nb8800_mdio_wait(bus);
 145}
 146
 147static int nb8800_mdio_read(struct mii_bus *bus, int phy_id, int reg)
 148{
 149        struct nb8800_priv *priv = bus->priv;
 150        u32 val;
 151        int err;
 152
 153        err = nb8800_mdio_cmd(bus, MDIO_CMD_ADDR(phy_id) | MDIO_CMD_REG(reg));
 154        if (err)
 155                return err;
 156
 157        val = nb8800_readl(priv, NB8800_MDIO_STS);
 158        if (val & MDIO_STS_ERR)
 159                return 0xffff;
 160
 161        return val & 0xffff;
 162}
 163
 164static int nb8800_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val)
 165{
 166        u32 cmd = MDIO_CMD_ADDR(phy_id) | MDIO_CMD_REG(reg) |
 167                MDIO_CMD_DATA(val) | MDIO_CMD_WR;
 168
 169        return nb8800_mdio_cmd(bus, cmd);
 170}
 171
 172static void nb8800_mac_tx(struct net_device *dev, bool enable)
 173{
 174        struct nb8800_priv *priv = netdev_priv(dev);
 175
 176        while (nb8800_readl(priv, NB8800_TXC_CR) & TCR_EN)
 177                cpu_relax();
 178
 179        nb8800_modb(priv, NB8800_TX_CTL1, TX_EN, enable);
 180}
 181
 182static void nb8800_mac_rx(struct net_device *dev, bool enable)
 183{
 184        nb8800_modb(netdev_priv(dev), NB8800_RX_CTL, RX_EN, enable);
 185}
 186
 187static void nb8800_mac_af(struct net_device *dev, bool enable)
 188{
 189        nb8800_modb(netdev_priv(dev), NB8800_RX_CTL, RX_AF_EN, enable);
 190}
 191
 192static void nb8800_start_rx(struct net_device *dev)
 193{
 194        nb8800_setl(netdev_priv(dev), NB8800_RXC_CR, RCR_EN);
 195}
 196
 197static int nb8800_alloc_rx(struct net_device *dev, unsigned int i, bool napi)
 198{
 199        struct nb8800_priv *priv = netdev_priv(dev);
 200        struct nb8800_rx_desc *rxd = &priv->rx_descs[i];
 201        struct nb8800_rx_buf *rxb = &priv->rx_bufs[i];
 202        int size = L1_CACHE_ALIGN(RX_BUF_SIZE);
 203        dma_addr_t dma_addr;
 204        struct page *page;
 205        unsigned long offset;
 206        void *data;
 207
 208        data = napi ? napi_alloc_frag(size) : netdev_alloc_frag(size);
 209        if (!data)
 210                return -ENOMEM;
 211
 212        page = virt_to_head_page(data);
 213        offset = data - page_address(page);
 214
 215        dma_addr = dma_map_page(&dev->dev, page, offset, RX_BUF_SIZE,
 216                                DMA_FROM_DEVICE);
 217
 218        if (dma_mapping_error(&dev->dev, dma_addr)) {
 219                skb_free_frag(data);
 220                return -ENOMEM;
 221        }
 222
 223        rxb->page = page;
 224        rxb->offset = offset;
 225        rxd->desc.s_addr = dma_addr;
 226
 227        return 0;
 228}
 229
 230static void nb8800_receive(struct net_device *dev, unsigned int i,
 231                           unsigned int len)
 232{
 233        struct nb8800_priv *priv = netdev_priv(dev);
 234        struct nb8800_rx_desc *rxd = &priv->rx_descs[i];
 235        struct page *page = priv->rx_bufs[i].page;
 236        int offset = priv->rx_bufs[i].offset;
 237        void *data = page_address(page) + offset;
 238        dma_addr_t dma = rxd->desc.s_addr;
 239        struct sk_buff *skb;
 240        unsigned int size;
 241        int err;
 242
 243        size = len <= RX_COPYBREAK ? len : RX_COPYHDR;
 244
 245        skb = napi_alloc_skb(&priv->napi, size);
 246        if (!skb) {
 247                netdev_err(dev, "rx skb allocation failed\n");
 248                dev->stats.rx_dropped++;
 249                return;
 250        }
 251
 252        if (len <= RX_COPYBREAK) {
 253                dma_sync_single_for_cpu(&dev->dev, dma, len, DMA_FROM_DEVICE);
 254                memcpy(skb_put(skb, len), data, len);
 255                dma_sync_single_for_device(&dev->dev, dma, len,
 256                                           DMA_FROM_DEVICE);
 257        } else {
 258                err = nb8800_alloc_rx(dev, i, true);
 259                if (err) {
 260                        netdev_err(dev, "rx buffer allocation failed\n");
 261                        dev->stats.rx_dropped++;
 262                        dev_kfree_skb(skb);
 263                        return;
 264                }
 265
 266                dma_unmap_page(&dev->dev, dma, RX_BUF_SIZE, DMA_FROM_DEVICE);
 267                memcpy(skb_put(skb, RX_COPYHDR), data, RX_COPYHDR);
 268                skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
 269                                offset + RX_COPYHDR, len - RX_COPYHDR,
 270                                RX_BUF_SIZE);
 271        }
 272
 273        skb->protocol = eth_type_trans(skb, dev);
 274        napi_gro_receive(&priv->napi, skb);
 275}
 276
 277static void nb8800_rx_error(struct net_device *dev, u32 report)
 278{
 279        if (report & RX_LENGTH_ERR)
 280                dev->stats.rx_length_errors++;
 281
 282        if (report & RX_FCS_ERR)
 283                dev->stats.rx_crc_errors++;
 284
 285        if (report & RX_FIFO_OVERRUN)
 286                dev->stats.rx_fifo_errors++;
 287
 288        if (report & RX_ALIGNMENT_ERROR)
 289                dev->stats.rx_frame_errors++;
 290
 291        dev->stats.rx_errors++;
 292}
 293
 294static int nb8800_poll(struct napi_struct *napi, int budget)
 295{
 296        struct net_device *dev = napi->dev;
 297        struct nb8800_priv *priv = netdev_priv(dev);
 298        struct nb8800_rx_desc *rxd;
 299        unsigned int last = priv->rx_eoc;
 300        unsigned int next;
 301        int work = 0;
 302
 303        nb8800_tx_done(dev);
 304
 305again:
 306        do {
 307                struct nb8800_rx_buf *rxb;
 308                unsigned int len;
 309
 310                next = (last + 1) % RX_DESC_COUNT;
 311
 312                rxb = &priv->rx_bufs[next];
 313                rxd = &priv->rx_descs[next];
 314
 315                if (!rxd->report)
 316                        break;
 317
 318                len = RX_BYTES_TRANSFERRED(rxd->report);
 319
 320                if (IS_RX_ERROR(rxd->report))
 321                        nb8800_rx_error(dev, rxd->report);
 322                else
 323                        nb8800_receive(dev, next, len);
 324
 325                dev->stats.rx_packets++;
 326                dev->stats.rx_bytes += len;
 327
 328                if (rxd->report & RX_MULTICAST_PKT)
 329                        dev->stats.multicast++;
 330
 331                rxd->report = 0;
 332                last = next;
 333                work++;
 334        } while (work < budget);
 335
 336        if (work) {
 337                priv->rx_descs[last].desc.config |= DESC_EOC;
 338                wmb();  /* ensure new EOC is written before clearing old */
 339                priv->rx_descs[priv->rx_eoc].desc.config &= ~DESC_EOC;
 340                priv->rx_eoc = last;
 341                nb8800_start_rx(dev);
 342        }
 343
 344        if (work < budget) {
 345                nb8800_writel(priv, NB8800_RX_ITR, priv->rx_itr_irq);
 346
 347                /* If a packet arrived after we last checked but
 348                 * before writing RX_ITR, the interrupt will be
 349                 * delayed, so we retrieve it now.
 350                 */
 351                if (priv->rx_descs[next].report)
 352                        goto again;
 353
 354                napi_complete_done(napi, work);
 355        }
 356
 357        return work;
 358}
 359
 360static void __nb8800_tx_dma_start(struct net_device *dev)
 361{
 362        struct nb8800_priv *priv = netdev_priv(dev);
 363        struct nb8800_tx_buf *txb;
 364        u32 txc_cr;
 365
 366        txb = &priv->tx_bufs[priv->tx_queue];
 367        if (!txb->ready)
 368                return;
 369
 370        txc_cr = nb8800_readl(priv, NB8800_TXC_CR);
 371        if (txc_cr & TCR_EN)
 372                return;
 373
 374        nb8800_writel(priv, NB8800_TX_DESC_ADDR, txb->dma_desc);
 375        wmb();          /* ensure desc addr is written before starting DMA */
 376        nb8800_writel(priv, NB8800_TXC_CR, txc_cr | TCR_EN);
 377
 378        priv->tx_queue = (priv->tx_queue + txb->chain_len) % TX_DESC_COUNT;
 379}
 380
 381static void nb8800_tx_dma_start(struct net_device *dev)
 382{
 383        struct nb8800_priv *priv = netdev_priv(dev);
 384
 385        spin_lock_irq(&priv->tx_lock);
 386        __nb8800_tx_dma_start(dev);
 387        spin_unlock_irq(&priv->tx_lock);
 388}
 389
 390static void nb8800_tx_dma_start_irq(struct net_device *dev)
 391{
 392        struct nb8800_priv *priv = netdev_priv(dev);
 393
 394        spin_lock(&priv->tx_lock);
 395        __nb8800_tx_dma_start(dev);
 396        spin_unlock(&priv->tx_lock);
 397}
 398
 399static int nb8800_xmit(struct sk_buff *skb, struct net_device *dev)
 400{
 401        struct nb8800_priv *priv = netdev_priv(dev);
 402        struct nb8800_tx_desc *txd;
 403        struct nb8800_tx_buf *txb;
 404        struct nb8800_dma_desc *desc;
 405        dma_addr_t dma_addr;
 406        unsigned int dma_len;
 407        unsigned int align;
 408        unsigned int next;
 409
 410        if (atomic_read(&priv->tx_free) <= NB8800_DESC_LOW) {
 411                netif_stop_queue(dev);
 412                return NETDEV_TX_BUSY;
 413        }
 414
 415        align = (8 - (uintptr_t)skb->data) & 7;
 416
 417        dma_len = skb->len - align;
 418        dma_addr = dma_map_single(&dev->dev, skb->data + align,
 419                                  dma_len, DMA_TO_DEVICE);
 420
 421        if (dma_mapping_error(&dev->dev, dma_addr)) {
 422                netdev_err(dev, "tx dma mapping error\n");
 423                kfree_skb(skb);
 424                dev->stats.tx_dropped++;
 425                return NETDEV_TX_OK;
 426        }
 427
 428        if (atomic_dec_return(&priv->tx_free) <= NB8800_DESC_LOW) {
 429                netif_stop_queue(dev);
 430                skb->xmit_more = 0;
 431        }
 432
 433        next = priv->tx_next;
 434        txb = &priv->tx_bufs[next];
 435        txd = &priv->tx_descs[next];
 436        desc = &txd->desc[0];
 437
 438        next = (next + 1) % TX_DESC_COUNT;
 439
 440        if (align) {
 441                memcpy(txd->buf, skb->data, align);
 442
 443                desc->s_addr =
 444                        txb->dma_desc + offsetof(struct nb8800_tx_desc, buf);
 445                desc->n_addr = txb->dma_desc + sizeof(txd->desc[0]);
 446                desc->config = DESC_BTS(2) | DESC_DS | align;
 447
 448                desc++;
 449        }
 450
 451        desc->s_addr = dma_addr;
 452        desc->n_addr = priv->tx_bufs[next].dma_desc;
 453        desc->config = DESC_BTS(2) | DESC_DS | DESC_EOF | dma_len;
 454
 455        if (!skb->xmit_more)
 456                desc->config |= DESC_EOC;
 457
 458        txb->skb = skb;
 459        txb->dma_addr = dma_addr;
 460        txb->dma_len = dma_len;
 461
 462        if (!priv->tx_chain) {
 463                txb->chain_len = 1;
 464                priv->tx_chain = txb;
 465        } else {
 466                priv->tx_chain->chain_len++;
 467        }
 468
 469        netdev_sent_queue(dev, skb->len);
 470
 471        priv->tx_next = next;
 472
 473        if (!skb->xmit_more) {
 474                smp_wmb();
 475                priv->tx_chain->ready = true;
 476                priv->tx_chain = NULL;
 477                nb8800_tx_dma_start(dev);
 478        }
 479
 480        return NETDEV_TX_OK;
 481}
 482
 483static void nb8800_tx_error(struct net_device *dev, u32 report)
 484{
 485        if (report & TX_LATE_COLLISION)
 486                dev->stats.collisions++;
 487
 488        if (report & TX_PACKET_DROPPED)
 489                dev->stats.tx_dropped++;
 490
 491        if (report & TX_FIFO_UNDERRUN)
 492                dev->stats.tx_fifo_errors++;
 493
 494        dev->stats.tx_errors++;
 495}
 496
 497static void nb8800_tx_done(struct net_device *dev)
 498{
 499        struct nb8800_priv *priv = netdev_priv(dev);
 500        unsigned int limit = priv->tx_next;
 501        unsigned int done = priv->tx_done;
 502        unsigned int packets = 0;
 503        unsigned int len = 0;
 504
 505        while (done != limit) {
 506                struct nb8800_tx_desc *txd = &priv->tx_descs[done];
 507                struct nb8800_tx_buf *txb = &priv->tx_bufs[done];
 508                struct sk_buff *skb;
 509
 510                if (!txd->report)
 511                        break;
 512
 513                skb = txb->skb;
 514                len += skb->len;
 515
 516                dma_unmap_single(&dev->dev, txb->dma_addr, txb->dma_len,
 517                                 DMA_TO_DEVICE);
 518
 519                if (IS_TX_ERROR(txd->report)) {
 520                        nb8800_tx_error(dev, txd->report);
 521                        kfree_skb(skb);
 522                } else {
 523                        consume_skb(skb);
 524                }
 525
 526                dev->stats.tx_packets++;
 527                dev->stats.tx_bytes += TX_BYTES_TRANSFERRED(txd->report);
 528                dev->stats.collisions += TX_EARLY_COLLISIONS(txd->report);
 529
 530                txb->skb = NULL;
 531                txb->ready = false;
 532                txd->report = 0;
 533
 534                done = (done + 1) % TX_DESC_COUNT;
 535                packets++;
 536        }
 537
 538        if (packets) {
 539                smp_mb__before_atomic();
 540                atomic_add(packets, &priv->tx_free);
 541                netdev_completed_queue(dev, packets, len);
 542                netif_wake_queue(dev);
 543                priv->tx_done = done;
 544        }
 545}
 546
 547static irqreturn_t nb8800_irq(int irq, void *dev_id)
 548{
 549        struct net_device *dev = dev_id;
 550        struct nb8800_priv *priv = netdev_priv(dev);
 551        irqreturn_t ret = IRQ_NONE;
 552        u32 val;
 553
 554        /* tx interrupt */
 555        val = nb8800_readl(priv, NB8800_TXC_SR);
 556        if (val) {
 557                nb8800_writel(priv, NB8800_TXC_SR, val);
 558
 559                if (val & TSR_DI)
 560                        nb8800_tx_dma_start_irq(dev);
 561
 562                if (val & TSR_TI)
 563                        napi_schedule_irqoff(&priv->napi);
 564
 565                if (unlikely(val & TSR_DE))
 566                        netdev_err(dev, "TX DMA error\n");
 567
 568                /* should never happen with automatic status retrieval */
 569                if (unlikely(val & TSR_TO))
 570                        netdev_err(dev, "TX Status FIFO overflow\n");
 571
 572                ret = IRQ_HANDLED;
 573        }
 574
 575        /* rx interrupt */
 576        val = nb8800_readl(priv, NB8800_RXC_SR);
 577        if (val) {
 578                nb8800_writel(priv, NB8800_RXC_SR, val);
 579
 580                if (likely(val & (RSR_RI | RSR_DI))) {
 581                        nb8800_writel(priv, NB8800_RX_ITR, priv->rx_itr_poll);
 582                        napi_schedule_irqoff(&priv->napi);
 583                }
 584
 585                if (unlikely(val & RSR_DE))
 586                        netdev_err(dev, "RX DMA error\n");
 587
 588                /* should never happen with automatic status retrieval */
 589                if (unlikely(val & RSR_RO))
 590                        netdev_err(dev, "RX Status FIFO overflow\n");
 591
 592                ret = IRQ_HANDLED;
 593        }
 594
 595        return ret;
 596}
 597
 598static void nb8800_mac_config(struct net_device *dev)
 599{
 600        struct nb8800_priv *priv = netdev_priv(dev);
 601        bool gigabit = priv->speed == SPEED_1000;
 602        u32 mac_mode_mask = RGMII_MODE | HALF_DUPLEX | GMAC_MODE;
 603        u32 mac_mode = 0;
 604        u32 slot_time;
 605        u32 phy_clk;
 606        u32 ict;
 607
 608        if (!priv->duplex)
 609                mac_mode |= HALF_DUPLEX;
 610
 611        if (gigabit) {
 612                if (priv->phy_mode == PHY_INTERFACE_MODE_RGMII)
 613                        mac_mode |= RGMII_MODE;
 614
 615                mac_mode |= GMAC_MODE;
 616                phy_clk = 125000000;
 617
 618                /* Should be 512 but register is only 8 bits */
 619                slot_time = 255;
 620        } else {
 621                phy_clk = 25000000;
 622                slot_time = 128;
 623        }
 624
 625        ict = DIV_ROUND_UP(phy_clk, clk_get_rate(priv->clk));
 626
 627        nb8800_writeb(priv, NB8800_IC_THRESHOLD, ict);
 628        nb8800_writeb(priv, NB8800_SLOT_TIME, slot_time);
 629        nb8800_maskb(priv, NB8800_MAC_MODE, mac_mode_mask, mac_mode);
 630}
 631
 632static void nb8800_pause_config(struct net_device *dev)
 633{
 634        struct nb8800_priv *priv = netdev_priv(dev);
 635        struct phy_device *phydev = dev->phydev;
 636        u32 rxcr;
 637
 638        if (priv->pause_aneg) {
 639                if (!phydev || !phydev->link)
 640                        return;
 641
 642                priv->pause_rx = phydev->pause;
 643                priv->pause_tx = phydev->pause ^ phydev->asym_pause;
 644        }
 645
 646        nb8800_modb(priv, NB8800_RX_CTL, RX_PAUSE_EN, priv->pause_rx);
 647
 648        rxcr = nb8800_readl(priv, NB8800_RXC_CR);
 649        if (!!(rxcr & RCR_FL) == priv->pause_tx)
 650                return;
 651
 652        if (netif_running(dev)) {
 653                napi_disable(&priv->napi);
 654                netif_tx_lock_bh(dev);
 655                nb8800_dma_stop(dev);
 656                nb8800_modl(priv, NB8800_RXC_CR, RCR_FL, priv->pause_tx);
 657                nb8800_start_rx(dev);
 658                netif_tx_unlock_bh(dev);
 659                napi_enable(&priv->napi);
 660        } else {
 661                nb8800_modl(priv, NB8800_RXC_CR, RCR_FL, priv->pause_tx);
 662        }
 663}
 664
 665static void nb8800_link_reconfigure(struct net_device *dev)
 666{
 667        struct nb8800_priv *priv = netdev_priv(dev);
 668        struct phy_device *phydev = dev->phydev;
 669        int change = 0;
 670
 671        if (phydev->link) {
 672                if (phydev->speed != priv->speed) {
 673                        priv->speed = phydev->speed;
 674                        change = 1;
 675                }
 676
 677                if (phydev->duplex != priv->duplex) {
 678                        priv->duplex = phydev->duplex;
 679                        change = 1;
 680                }
 681
 682                if (change)
 683                        nb8800_mac_config(dev);
 684
 685                nb8800_pause_config(dev);
 686        }
 687
 688        if (phydev->link != priv->link) {
 689                priv->link = phydev->link;
 690                change = 1;
 691        }
 692
 693        if (change)
 694                phy_print_status(phydev);
 695}
 696
 697static void nb8800_update_mac_addr(struct net_device *dev)
 698{
 699        struct nb8800_priv *priv = netdev_priv(dev);
 700        int i;
 701
 702        for (i = 0; i < ETH_ALEN; i++)
 703                nb8800_writeb(priv, NB8800_SRC_ADDR(i), dev->dev_addr[i]);
 704
 705        for (i = 0; i < ETH_ALEN; i++)
 706                nb8800_writeb(priv, NB8800_UC_ADDR(i), dev->dev_addr[i]);
 707}
 708
 709static int nb8800_set_mac_address(struct net_device *dev, void *addr)
 710{
 711        struct sockaddr *sock = addr;
 712
 713        if (netif_running(dev))
 714                return -EBUSY;
 715
 716        ether_addr_copy(dev->dev_addr, sock->sa_data);
 717        nb8800_update_mac_addr(dev);
 718
 719        return 0;
 720}
 721
 722static void nb8800_mc_init(struct net_device *dev, int val)
 723{
 724        struct nb8800_priv *priv = netdev_priv(dev);
 725
 726        nb8800_writeb(priv, NB8800_MC_INIT, val);
 727        readb_poll_timeout_atomic(priv->base + NB8800_MC_INIT, val, !val,
 728                                  1, 1000);
 729}
 730
 731static void nb8800_set_rx_mode(struct net_device *dev)
 732{
 733        struct nb8800_priv *priv = netdev_priv(dev);
 734        struct netdev_hw_addr *ha;
 735        int i;
 736
 737        if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
 738                nb8800_mac_af(dev, false);
 739                return;
 740        }
 741
 742        nb8800_mac_af(dev, true);
 743        nb8800_mc_init(dev, 0);
 744
 745        netdev_for_each_mc_addr(ha, dev) {
 746                for (i = 0; i < ETH_ALEN; i++)
 747                        nb8800_writeb(priv, NB8800_MC_ADDR(i), ha->addr[i]);
 748
 749                nb8800_mc_init(dev, 0xff);
 750        }
 751}
 752
 753#define RX_DESC_SIZE (RX_DESC_COUNT * sizeof(struct nb8800_rx_desc))
 754#define TX_DESC_SIZE (TX_DESC_COUNT * sizeof(struct nb8800_tx_desc))
 755
 756static void nb8800_dma_free(struct net_device *dev)
 757{
 758        struct nb8800_priv *priv = netdev_priv(dev);
 759        unsigned int i;
 760
 761        if (priv->rx_bufs) {
 762                for (i = 0; i < RX_DESC_COUNT; i++)
 763                        if (priv->rx_bufs[i].page)
 764                                put_page(priv->rx_bufs[i].page);
 765
 766                kfree(priv->rx_bufs);
 767                priv->rx_bufs = NULL;
 768        }
 769
 770        if (priv->tx_bufs) {
 771                for (i = 0; i < TX_DESC_COUNT; i++)
 772                        kfree_skb(priv->tx_bufs[i].skb);
 773
 774                kfree(priv->tx_bufs);
 775                priv->tx_bufs = NULL;
 776        }
 777
 778        if (priv->rx_descs) {
 779                dma_free_coherent(dev->dev.parent, RX_DESC_SIZE, priv->rx_descs,
 780                                  priv->rx_desc_dma);
 781                priv->rx_descs = NULL;
 782        }
 783
 784        if (priv->tx_descs) {
 785                dma_free_coherent(dev->dev.parent, TX_DESC_SIZE, priv->tx_descs,
 786                                  priv->tx_desc_dma);
 787                priv->tx_descs = NULL;
 788        }
 789}
 790
 791static void nb8800_dma_reset(struct net_device *dev)
 792{
 793        struct nb8800_priv *priv = netdev_priv(dev);
 794        struct nb8800_rx_desc *rxd;
 795        struct nb8800_tx_desc *txd;
 796        unsigned int i;
 797
 798        for (i = 0; i < RX_DESC_COUNT; i++) {
 799                dma_addr_t rx_dma = priv->rx_desc_dma + i * sizeof(*rxd);
 800
 801                rxd = &priv->rx_descs[i];
 802                rxd->desc.n_addr = rx_dma + sizeof(*rxd);
 803                rxd->desc.r_addr =
 804                        rx_dma + offsetof(struct nb8800_rx_desc, report);
 805                rxd->desc.config = priv->rx_dma_config;
 806                rxd->report = 0;
 807        }
 808
 809        rxd->desc.n_addr = priv->rx_desc_dma;
 810        rxd->desc.config |= DESC_EOC;
 811
 812        priv->rx_eoc = RX_DESC_COUNT - 1;
 813
 814        for (i = 0; i < TX_DESC_COUNT; i++) {
 815                struct nb8800_tx_buf *txb = &priv->tx_bufs[i];
 816                dma_addr_t r_dma = txb->dma_desc +
 817                        offsetof(struct nb8800_tx_desc, report);
 818
 819                txd = &priv->tx_descs[i];
 820                txd->desc[0].r_addr = r_dma;
 821                txd->desc[1].r_addr = r_dma;
 822                txd->report = 0;
 823        }
 824
 825        priv->tx_next = 0;
 826        priv->tx_queue = 0;
 827        priv->tx_done = 0;
 828        atomic_set(&priv->tx_free, TX_DESC_COUNT);
 829
 830        nb8800_writel(priv, NB8800_RX_DESC_ADDR, priv->rx_desc_dma);
 831
 832        wmb();          /* ensure all setup is written before starting */
 833}
 834
 835static int nb8800_dma_init(struct net_device *dev)
 836{
 837        struct nb8800_priv *priv = netdev_priv(dev);
 838        unsigned int n_rx = RX_DESC_COUNT;
 839        unsigned int n_tx = TX_DESC_COUNT;
 840        unsigned int i;
 841        int err;
 842
 843        priv->rx_descs = dma_alloc_coherent(dev->dev.parent, RX_DESC_SIZE,
 844                                            &priv->rx_desc_dma, GFP_KERNEL);
 845        if (!priv->rx_descs)
 846                goto err_out;
 847
 848        priv->rx_bufs = kcalloc(n_rx, sizeof(*priv->rx_bufs), GFP_KERNEL);
 849        if (!priv->rx_bufs)
 850                goto err_out;
 851
 852        for (i = 0; i < n_rx; i++) {
 853                err = nb8800_alloc_rx(dev, i, false);
 854                if (err)
 855                        goto err_out;
 856        }
 857
 858        priv->tx_descs = dma_alloc_coherent(dev->dev.parent, TX_DESC_SIZE,
 859                                            &priv->tx_desc_dma, GFP_KERNEL);
 860        if (!priv->tx_descs)
 861                goto err_out;
 862
 863        priv->tx_bufs = kcalloc(n_tx, sizeof(*priv->tx_bufs), GFP_KERNEL);
 864        if (!priv->tx_bufs)
 865                goto err_out;
 866
 867        for (i = 0; i < n_tx; i++)
 868                priv->tx_bufs[i].dma_desc =
 869                        priv->tx_desc_dma + i * sizeof(struct nb8800_tx_desc);
 870
 871        nb8800_dma_reset(dev);
 872
 873        return 0;
 874
 875err_out:
 876        nb8800_dma_free(dev);
 877
 878        return -ENOMEM;
 879}
 880
 881static int nb8800_dma_stop(struct net_device *dev)
 882{
 883        struct nb8800_priv *priv = netdev_priv(dev);
 884        struct nb8800_tx_buf *txb = &priv->tx_bufs[0];
 885        struct nb8800_tx_desc *txd = &priv->tx_descs[0];
 886        int retry = 5;
 887        u32 txcr;
 888        u32 rxcr;
 889        int err;
 890        unsigned int i;
 891
 892        /* wait for tx to finish */
 893        err = readl_poll_timeout_atomic(priv->base + NB8800_TXC_CR, txcr,
 894                                        !(txcr & TCR_EN) &&
 895                                        priv->tx_done == priv->tx_next,
 896                                        1000, 1000000);
 897        if (err)
 898                return err;
 899
 900        /* The rx DMA only stops if it reaches the end of chain.
 901         * To make this happen, we set the EOC flag on all rx
 902         * descriptors, put the device in loopback mode, and send
 903         * a few dummy frames.  The interrupt handler will ignore
 904         * these since NAPI is disabled and no real frames are in
 905         * the tx queue.
 906         */
 907
 908        for (i = 0; i < RX_DESC_COUNT; i++)
 909                priv->rx_descs[i].desc.config |= DESC_EOC;
 910
 911        txd->desc[0].s_addr =
 912                txb->dma_desc + offsetof(struct nb8800_tx_desc, buf);
 913        txd->desc[0].config = DESC_BTS(2) | DESC_DS | DESC_EOF | DESC_EOC | 8;
 914        memset(txd->buf, 0, sizeof(txd->buf));
 915
 916        nb8800_mac_af(dev, false);
 917        nb8800_setb(priv, NB8800_MAC_MODE, LOOPBACK_EN);
 918
 919        do {
 920                nb8800_writel(priv, NB8800_TX_DESC_ADDR, txb->dma_desc);
 921                wmb();
 922                nb8800_writel(priv, NB8800_TXC_CR, txcr | TCR_EN);
 923
 924                err = readl_poll_timeout_atomic(priv->base + NB8800_RXC_CR,
 925                                                rxcr, !(rxcr & RCR_EN),
 926                                                1000, 100000);
 927        } while (err && --retry);
 928
 929        nb8800_mac_af(dev, true);
 930        nb8800_clearb(priv, NB8800_MAC_MODE, LOOPBACK_EN);
 931        nb8800_dma_reset(dev);
 932
 933        return retry ? 0 : -ETIMEDOUT;
 934}
 935
 936static void nb8800_pause_adv(struct net_device *dev)
 937{
 938        struct nb8800_priv *priv = netdev_priv(dev);
 939        struct phy_device *phydev = dev->phydev;
 940        u32 adv = 0;
 941
 942        if (!phydev)
 943                return;
 944
 945        if (priv->pause_rx)
 946                adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
 947        if (priv->pause_tx)
 948                adv ^= ADVERTISED_Asym_Pause;
 949
 950        phydev->supported |= adv;
 951        phydev->advertising |= adv;
 952}
 953
 954static int nb8800_open(struct net_device *dev)
 955{
 956        struct nb8800_priv *priv = netdev_priv(dev);
 957        struct phy_device *phydev;
 958        int err;
 959
 960        /* clear any pending interrupts */
 961        nb8800_writel(priv, NB8800_RXC_SR, 0xf);
 962        nb8800_writel(priv, NB8800_TXC_SR, 0xf);
 963
 964        err = nb8800_dma_init(dev);
 965        if (err)
 966                return err;
 967
 968        err = request_irq(dev->irq, nb8800_irq, 0, dev_name(&dev->dev), dev);
 969        if (err)
 970                goto err_free_dma;
 971
 972        nb8800_mac_rx(dev, true);
 973        nb8800_mac_tx(dev, true);
 974
 975        phydev = of_phy_connect(dev, priv->phy_node,
 976                                nb8800_link_reconfigure, 0,
 977                                priv->phy_mode);
 978        if (!phydev)
 979                goto err_free_irq;
 980
 981        nb8800_pause_adv(dev);
 982
 983        netdev_reset_queue(dev);
 984        napi_enable(&priv->napi);
 985        netif_start_queue(dev);
 986
 987        nb8800_start_rx(dev);
 988        phy_start(phydev);
 989
 990        return 0;
 991
 992err_free_irq:
 993        free_irq(dev->irq, dev);
 994err_free_dma:
 995        nb8800_dma_free(dev);
 996
 997        return err;
 998}
 999
1000static int nb8800_stop(struct net_device *dev)
1001{
1002        struct nb8800_priv *priv = netdev_priv(dev);
1003        struct phy_device *phydev = dev->phydev;
1004
1005        phy_stop(phydev);
1006
1007        netif_stop_queue(dev);
1008        napi_disable(&priv->napi);
1009
1010        nb8800_dma_stop(dev);
1011        nb8800_mac_rx(dev, false);
1012        nb8800_mac_tx(dev, false);
1013
1014        phy_disconnect(phydev);
1015
1016        free_irq(dev->irq, dev);
1017
1018        nb8800_dma_free(dev);
1019
1020        return 0;
1021}
1022
1023static int nb8800_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1024{
1025        return phy_mii_ioctl(dev->phydev, rq, cmd);
1026}
1027
1028static const struct net_device_ops nb8800_netdev_ops = {
1029        .ndo_open               = nb8800_open,
1030        .ndo_stop               = nb8800_stop,
1031        .ndo_start_xmit         = nb8800_xmit,
1032        .ndo_set_mac_address    = nb8800_set_mac_address,
1033        .ndo_set_rx_mode        = nb8800_set_rx_mode,
1034        .ndo_do_ioctl           = nb8800_ioctl,
1035        .ndo_change_mtu         = eth_change_mtu,
1036        .ndo_validate_addr      = eth_validate_addr,
1037};
1038
1039static int nb8800_nway_reset(struct net_device *dev)
1040{
1041        struct phy_device *phydev = dev->phydev;
1042
1043        if (!phydev)
1044                return -ENODEV;
1045
1046        return genphy_restart_aneg(phydev);
1047}
1048
1049static void nb8800_get_pauseparam(struct net_device *dev,
1050                                  struct ethtool_pauseparam *pp)
1051{
1052        struct nb8800_priv *priv = netdev_priv(dev);
1053
1054        pp->autoneg = priv->pause_aneg;
1055        pp->rx_pause = priv->pause_rx;
1056        pp->tx_pause = priv->pause_tx;
1057}
1058
1059static int nb8800_set_pauseparam(struct net_device *dev,
1060                                 struct ethtool_pauseparam *pp)
1061{
1062        struct nb8800_priv *priv = netdev_priv(dev);
1063        struct phy_device *phydev = dev->phydev;
1064
1065        priv->pause_aneg = pp->autoneg;
1066        priv->pause_rx = pp->rx_pause;
1067        priv->pause_tx = pp->tx_pause;
1068
1069        nb8800_pause_adv(dev);
1070
1071        if (!priv->pause_aneg)
1072                nb8800_pause_config(dev);
1073        else if (phydev)
1074                phy_start_aneg(phydev);
1075
1076        return 0;
1077}
1078
1079static const char nb8800_stats_names[][ETH_GSTRING_LEN] = {
1080        "rx_bytes_ok",
1081        "rx_frames_ok",
1082        "rx_undersize_frames",
1083        "rx_fragment_frames",
1084        "rx_64_byte_frames",
1085        "rx_127_byte_frames",
1086        "rx_255_byte_frames",
1087        "rx_511_byte_frames",
1088        "rx_1023_byte_frames",
1089        "rx_max_size_frames",
1090        "rx_oversize_frames",
1091        "rx_bad_fcs_frames",
1092        "rx_broadcast_frames",
1093        "rx_multicast_frames",
1094        "rx_control_frames",
1095        "rx_pause_frames",
1096        "rx_unsup_control_frames",
1097        "rx_align_error_frames",
1098        "rx_overrun_frames",
1099        "rx_jabber_frames",
1100        "rx_bytes",
1101        "rx_frames",
1102
1103        "tx_bytes_ok",
1104        "tx_frames_ok",
1105        "tx_64_byte_frames",
1106        "tx_127_byte_frames",
1107        "tx_255_byte_frames",
1108        "tx_511_byte_frames",
1109        "tx_1023_byte_frames",
1110        "tx_max_size_frames",
1111        "tx_oversize_frames",
1112        "tx_broadcast_frames",
1113        "tx_multicast_frames",
1114        "tx_control_frames",
1115        "tx_pause_frames",
1116        "tx_underrun_frames",
1117        "tx_single_collision_frames",
1118        "tx_multi_collision_frames",
1119        "tx_deferred_collision_frames",
1120        "tx_late_collision_frames",
1121        "tx_excessive_collision_frames",
1122        "tx_bytes",
1123        "tx_frames",
1124        "tx_collisions",
1125};
1126
1127#define NB8800_NUM_STATS ARRAY_SIZE(nb8800_stats_names)
1128
1129static int nb8800_get_sset_count(struct net_device *dev, int sset)
1130{
1131        if (sset == ETH_SS_STATS)
1132                return NB8800_NUM_STATS;
1133
1134        return -EOPNOTSUPP;
1135}
1136
1137static void nb8800_get_strings(struct net_device *dev, u32 sset, u8 *buf)
1138{
1139        if (sset == ETH_SS_STATS)
1140                memcpy(buf, &nb8800_stats_names, sizeof(nb8800_stats_names));
1141}
1142
1143static u32 nb8800_read_stat(struct net_device *dev, int index)
1144{
1145        struct nb8800_priv *priv = netdev_priv(dev);
1146
1147        nb8800_writeb(priv, NB8800_STAT_INDEX, index);
1148
1149        return nb8800_readl(priv, NB8800_STAT_DATA);
1150}
1151
1152static void nb8800_get_ethtool_stats(struct net_device *dev,
1153                                     struct ethtool_stats *estats, u64 *st)
1154{
1155        unsigned int i;
1156        u32 rx, tx;
1157
1158        for (i = 0; i < NB8800_NUM_STATS / 2; i++) {
1159                rx = nb8800_read_stat(dev, i);
1160                tx = nb8800_read_stat(dev, i | 0x80);
1161                st[i] = rx;
1162                st[i + NB8800_NUM_STATS / 2] = tx;
1163        }
1164}
1165
1166static const struct ethtool_ops nb8800_ethtool_ops = {
1167        .nway_reset             = nb8800_nway_reset,
1168        .get_link               = ethtool_op_get_link,
1169        .get_pauseparam         = nb8800_get_pauseparam,
1170        .set_pauseparam         = nb8800_set_pauseparam,
1171        .get_sset_count         = nb8800_get_sset_count,
1172        .get_strings            = nb8800_get_strings,
1173        .get_ethtool_stats      = nb8800_get_ethtool_stats,
1174        .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1175        .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1176};
1177
1178static int nb8800_hw_init(struct net_device *dev)
1179{
1180        struct nb8800_priv *priv = netdev_priv(dev);
1181        u32 val;
1182
1183        val = TX_RETRY_EN | TX_PAD_EN | TX_APPEND_FCS;
1184        nb8800_writeb(priv, NB8800_TX_CTL1, val);
1185
1186        /* Collision retry count */
1187        nb8800_writeb(priv, NB8800_TX_CTL2, 5);
1188
1189        val = RX_PAD_STRIP | RX_AF_EN;
1190        nb8800_writeb(priv, NB8800_RX_CTL, val);
1191
1192        /* Chosen by fair dice roll */
1193        nb8800_writeb(priv, NB8800_RANDOM_SEED, 4);
1194
1195        /* TX cycles per deferral period */
1196        nb8800_writeb(priv, NB8800_TX_SDP, 12);
1197
1198        /* The following three threshold values have been
1199         * experimentally determined for good results.
1200         */
1201
1202        /* RX/TX FIFO threshold for partial empty (64-bit entries) */
1203        nb8800_writeb(priv, NB8800_PE_THRESHOLD, 0);
1204
1205        /* RX/TX FIFO threshold for partial full (64-bit entries) */
1206        nb8800_writeb(priv, NB8800_PF_THRESHOLD, 255);
1207
1208        /* Buffer size for transmit (64-bit entries) */
1209        nb8800_writeb(priv, NB8800_TX_BUFSIZE, 64);
1210
1211        /* Configure tx DMA */
1212
1213        val = nb8800_readl(priv, NB8800_TXC_CR);
1214        val &= TCR_LE;          /* keep endian setting */
1215        val |= TCR_DM;          /* DMA descriptor mode */
1216        val |= TCR_RS;          /* automatically store tx status  */
1217        val |= TCR_DIE;         /* interrupt on DMA chain completion */
1218        val |= TCR_TFI(7);      /* interrupt after 7 frames transmitted */
1219        val |= TCR_BTS(2);      /* 32-byte bus transaction size */
1220        nb8800_writel(priv, NB8800_TXC_CR, val);
1221
1222        /* TX complete interrupt after 10 ms or 7 frames (see above) */
1223        val = clk_get_rate(priv->clk) / 100;
1224        nb8800_writel(priv, NB8800_TX_ITR, val);
1225
1226        /* Configure rx DMA */
1227
1228        val = nb8800_readl(priv, NB8800_RXC_CR);
1229        val &= RCR_LE;          /* keep endian setting */
1230        val |= RCR_DM;          /* DMA descriptor mode */
1231        val |= RCR_RS;          /* automatically store rx status */
1232        val |= RCR_DIE;         /* interrupt at end of DMA chain */
1233        val |= RCR_RFI(7);      /* interrupt after 7 frames received */
1234        val |= RCR_BTS(2);      /* 32-byte bus transaction size */
1235        nb8800_writel(priv, NB8800_RXC_CR, val);
1236
1237        /* The rx interrupt can fire before the DMA has completed
1238         * unless a small delay is added.  50 us is hopefully enough.
1239         */
1240        priv->rx_itr_irq = clk_get_rate(priv->clk) / 20000;
1241
1242        /* In NAPI poll mode we want to disable interrupts, but the
1243         * hardware does not permit this.  Delay 10 ms instead.
1244         */
1245        priv->rx_itr_poll = clk_get_rate(priv->clk) / 100;
1246
1247        nb8800_writel(priv, NB8800_RX_ITR, priv->rx_itr_irq);
1248
1249        priv->rx_dma_config = RX_BUF_SIZE | DESC_BTS(2) | DESC_DS | DESC_EOF;
1250
1251        /* Flow control settings */
1252
1253        /* Pause time of 0.1 ms */
1254        val = 100000 / 512;
1255        nb8800_writeb(priv, NB8800_PQ1, val >> 8);
1256        nb8800_writeb(priv, NB8800_PQ2, val & 0xff);
1257
1258        /* Auto-negotiate by default */
1259        priv->pause_aneg = true;
1260        priv->pause_rx = true;
1261        priv->pause_tx = true;
1262
1263        nb8800_mc_init(dev, 0);
1264
1265        return 0;
1266}
1267
1268static int nb8800_tangox_init(struct net_device *dev)
1269{
1270        struct nb8800_priv *priv = netdev_priv(dev);
1271        u32 pad_mode = PAD_MODE_MII;
1272
1273        switch (priv->phy_mode) {
1274        case PHY_INTERFACE_MODE_MII:
1275        case PHY_INTERFACE_MODE_GMII:
1276                pad_mode = PAD_MODE_MII;
1277                break;
1278
1279        case PHY_INTERFACE_MODE_RGMII:
1280                pad_mode = PAD_MODE_RGMII;
1281                break;
1282
1283        case PHY_INTERFACE_MODE_RGMII_TXID:
1284                pad_mode = PAD_MODE_RGMII | PAD_MODE_GTX_CLK_DELAY;
1285                break;
1286
1287        default:
1288                dev_err(dev->dev.parent, "unsupported phy mode %s\n",
1289                        phy_modes(priv->phy_mode));
1290                return -EINVAL;
1291        }
1292
1293        nb8800_writeb(priv, NB8800_TANGOX_PAD_MODE, pad_mode);
1294
1295        return 0;
1296}
1297
1298static int nb8800_tangox_reset(struct net_device *dev)
1299{
1300        struct nb8800_priv *priv = netdev_priv(dev);
1301        int clk_div;
1302
1303        nb8800_writeb(priv, NB8800_TANGOX_RESET, 0);
1304        usleep_range(1000, 10000);
1305        nb8800_writeb(priv, NB8800_TANGOX_RESET, 1);
1306
1307        wmb();          /* ensure reset is cleared before proceeding */
1308
1309        clk_div = DIV_ROUND_UP(clk_get_rate(priv->clk), 2 * MAX_MDC_CLOCK);
1310        nb8800_writew(priv, NB8800_TANGOX_MDIO_CLKDIV, clk_div);
1311
1312        return 0;
1313}
1314
1315static const struct nb8800_ops nb8800_tangox_ops = {
1316        .init   = nb8800_tangox_init,
1317        .reset  = nb8800_tangox_reset,
1318};
1319
1320static int nb8800_tango4_init(struct net_device *dev)
1321{
1322        struct nb8800_priv *priv = netdev_priv(dev);
1323        int err;
1324
1325        err = nb8800_tangox_init(dev);
1326        if (err)
1327                return err;
1328
1329        /* On tango4 interrupt on DMA completion per frame works and gives
1330         * better performance despite generating more rx interrupts.
1331         */
1332
1333        /* Disable unnecessary interrupt on rx completion */
1334        nb8800_clearl(priv, NB8800_RXC_CR, RCR_RFI(7));
1335
1336        /* Request interrupt on descriptor DMA completion */
1337        priv->rx_dma_config |= DESC_ID;
1338
1339        return 0;
1340}
1341
1342static const struct nb8800_ops nb8800_tango4_ops = {
1343        .init   = nb8800_tango4_init,
1344        .reset  = nb8800_tangox_reset,
1345};
1346
1347static const struct of_device_id nb8800_dt_ids[] = {
1348        {
1349                .compatible = "aurora,nb8800",
1350        },
1351        {
1352                .compatible = "sigma,smp8642-ethernet",
1353                .data = &nb8800_tangox_ops,
1354        },
1355        {
1356                .compatible = "sigma,smp8734-ethernet",
1357                .data = &nb8800_tango4_ops,
1358        },
1359        { }
1360};
1361MODULE_DEVICE_TABLE(of, nb8800_dt_ids);
1362
1363static int nb8800_probe(struct platform_device *pdev)
1364{
1365        const struct of_device_id *match;
1366        const struct nb8800_ops *ops = NULL;
1367        struct nb8800_priv *priv;
1368        struct resource *res;
1369        struct net_device *dev;
1370        struct mii_bus *bus;
1371        const unsigned char *mac;
1372        void __iomem *base;
1373        int irq;
1374        int ret;
1375
1376        match = of_match_device(nb8800_dt_ids, &pdev->dev);
1377        if (match)
1378                ops = match->data;
1379
1380        irq = platform_get_irq(pdev, 0);
1381        if (irq <= 0) {
1382                dev_err(&pdev->dev, "No IRQ\n");
1383                return -EINVAL;
1384        }
1385
1386        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1387        base = devm_ioremap_resource(&pdev->dev, res);
1388        if (IS_ERR(base))
1389                return PTR_ERR(base);
1390
1391        dev_dbg(&pdev->dev, "AU-NB8800 Ethernet at %pa\n", &res->start);
1392
1393        dev = alloc_etherdev(sizeof(*priv));
1394        if (!dev)
1395                return -ENOMEM;
1396
1397        platform_set_drvdata(pdev, dev);
1398        SET_NETDEV_DEV(dev, &pdev->dev);
1399
1400        priv = netdev_priv(dev);
1401        priv->base = base;
1402
1403        priv->phy_mode = of_get_phy_mode(pdev->dev.of_node);
1404        if (priv->phy_mode < 0)
1405                priv->phy_mode = PHY_INTERFACE_MODE_RGMII;
1406
1407        priv->clk = devm_clk_get(&pdev->dev, NULL);
1408        if (IS_ERR(priv->clk)) {
1409                dev_err(&pdev->dev, "failed to get clock\n");
1410                ret = PTR_ERR(priv->clk);
1411                goto err_free_dev;
1412        }
1413
1414        ret = clk_prepare_enable(priv->clk);
1415        if (ret)
1416                goto err_free_dev;
1417
1418        spin_lock_init(&priv->tx_lock);
1419
1420        if (ops && ops->reset) {
1421                ret = ops->reset(dev);
1422                if (ret)
1423                        goto err_disable_clk;
1424        }
1425
1426        bus = devm_mdiobus_alloc(&pdev->dev);
1427        if (!bus) {
1428                ret = -ENOMEM;
1429                goto err_disable_clk;
1430        }
1431
1432        bus->name = "nb8800-mii";
1433        bus->read = nb8800_mdio_read;
1434        bus->write = nb8800_mdio_write;
1435        bus->parent = &pdev->dev;
1436        snprintf(bus->id, MII_BUS_ID_SIZE, "%lx.nb8800-mii",
1437                 (unsigned long)res->start);
1438        bus->priv = priv;
1439
1440        ret = of_mdiobus_register(bus, pdev->dev.of_node);
1441        if (ret) {
1442                dev_err(&pdev->dev, "failed to register MII bus\n");
1443                goto err_disable_clk;
1444        }
1445
1446        if (of_phy_is_fixed_link(pdev->dev.of_node)) {
1447                ret = of_phy_register_fixed_link(pdev->dev.of_node);
1448                if (ret < 0) {
1449                        dev_err(&pdev->dev, "bad fixed-link spec\n");
1450                        goto err_free_bus;
1451                }
1452                priv->phy_node = of_node_get(pdev->dev.of_node);
1453        }
1454
1455        if (!priv->phy_node)
1456                priv->phy_node = of_parse_phandle(pdev->dev.of_node,
1457                                                  "phy-handle", 0);
1458
1459        if (!priv->phy_node) {
1460                dev_err(&pdev->dev, "no PHY specified\n");
1461                ret = -ENODEV;
1462                goto err_free_bus;
1463        }
1464
1465        priv->mii_bus = bus;
1466
1467        ret = nb8800_hw_init(dev);
1468        if (ret)
1469                goto err_deregister_fixed_link;
1470
1471        if (ops && ops->init) {
1472                ret = ops->init(dev);
1473                if (ret)
1474                        goto err_deregister_fixed_link;
1475        }
1476
1477        dev->netdev_ops = &nb8800_netdev_ops;
1478        dev->ethtool_ops = &nb8800_ethtool_ops;
1479        dev->flags |= IFF_MULTICAST;
1480        dev->irq = irq;
1481
1482        mac = of_get_mac_address(pdev->dev.of_node);
1483        if (mac)
1484                ether_addr_copy(dev->dev_addr, mac);
1485
1486        if (!is_valid_ether_addr(dev->dev_addr))
1487                eth_hw_addr_random(dev);
1488
1489        nb8800_update_mac_addr(dev);
1490
1491        netif_carrier_off(dev);
1492
1493        ret = register_netdev(dev);
1494        if (ret) {
1495                netdev_err(dev, "failed to register netdev\n");
1496                goto err_free_dma;
1497        }
1498
1499        netif_napi_add(dev, &priv->napi, nb8800_poll, NAPI_POLL_WEIGHT);
1500
1501        netdev_info(dev, "MAC address %pM\n", dev->dev_addr);
1502
1503        return 0;
1504
1505err_free_dma:
1506        nb8800_dma_free(dev);
1507err_deregister_fixed_link:
1508        if (of_phy_is_fixed_link(pdev->dev.of_node))
1509                of_phy_deregister_fixed_link(pdev->dev.of_node);
1510err_free_bus:
1511        of_node_put(priv->phy_node);
1512        mdiobus_unregister(bus);
1513err_disable_clk:
1514        clk_disable_unprepare(priv->clk);
1515err_free_dev:
1516        free_netdev(dev);
1517
1518        return ret;
1519}
1520
1521static int nb8800_remove(struct platform_device *pdev)
1522{
1523        struct net_device *ndev = platform_get_drvdata(pdev);
1524        struct nb8800_priv *priv = netdev_priv(ndev);
1525
1526        unregister_netdev(ndev);
1527        if (of_phy_is_fixed_link(pdev->dev.of_node))
1528                of_phy_deregister_fixed_link(pdev->dev.of_node);
1529        of_node_put(priv->phy_node);
1530
1531        mdiobus_unregister(priv->mii_bus);
1532
1533        clk_disable_unprepare(priv->clk);
1534
1535        nb8800_dma_free(ndev);
1536        free_netdev(ndev);
1537
1538        return 0;
1539}
1540
1541static struct platform_driver nb8800_driver = {
1542        .driver = {
1543                .name           = "nb8800",
1544                .of_match_table = nb8800_dt_ids,
1545        },
1546        .probe  = nb8800_probe,
1547        .remove = nb8800_remove,
1548};
1549
1550module_platform_driver(nb8800_driver);
1551
1552MODULE_DESCRIPTION("Aurora AU-NB8800 Ethernet driver");
1553MODULE_AUTHOR("Mans Rullgard <mans@mansr.com>");
1554MODULE_LICENSE("GPL");
1555