linux/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
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   1/* bnx2x_ethtool.c: QLogic Everest network driver.
   2 *
   3 * Copyright (c) 2007-2013 Broadcom Corporation
   4 * Copyright (c) 2014 QLogic Corporation
   5 * All rights reserved
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation.
  10 *
  11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  12 * Written by: Eliezer Tamir
  13 * Based on code from Michael Chan's bnx2 driver
  14 * UDP CSUM errata workaround by Arik Gendelman
  15 * Slowpath and fastpath rework by Vladislav Zolotarov
  16 * Statistics and Link management by Yitchak Gertner
  17 *
  18 */
  19
  20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22#include <linux/ethtool.h>
  23#include <linux/netdevice.h>
  24#include <linux/types.h>
  25#include <linux/sched.h>
  26#include <linux/crc32.h>
  27#include "bnx2x.h"
  28#include "bnx2x_cmn.h"
  29#include "bnx2x_dump.h"
  30#include "bnx2x_init.h"
  31
  32/* Note: in the format strings below %s is replaced by the queue-name which is
  33 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  34 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  35 */
  36#define MAX_QUEUE_NAME_LEN      4
  37static const struct {
  38        long offset;
  39        int size;
  40        char string[ETH_GSTRING_LEN];
  41} bnx2x_q_stats_arr[] = {
  42/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  43        { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  44                                                8, "[%s]: rx_ucast_packets" },
  45        { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  46                                                8, "[%s]: rx_mcast_packets" },
  47        { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  48                                                8, "[%s]: rx_bcast_packets" },
  49        { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  50        { Q_STATS_OFFSET32(rx_err_discard_pkt),
  51                                         4, "[%s]: rx_phy_ip_err_discards"},
  52        { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  53                                         4, "[%s]: rx_skb_alloc_discard" },
  54        { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  55        { Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" },
  56        { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  57/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  58                                                8, "[%s]: tx_ucast_packets" },
  59        { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  60                                                8, "[%s]: tx_mcast_packets" },
  61        { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  62                                                8, "[%s]: tx_bcast_packets" },
  63        { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  64                                                8, "[%s]: tpa_aggregations" },
  65        { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  66                                        8, "[%s]: tpa_aggregated_frames"},
  67        { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
  68        { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
  69                                        4, "[%s]: driver_filtered_tx_pkt" }
  70};
  71
  72#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  73
  74static const struct {
  75        long offset;
  76        int size;
  77        bool is_port_stat;
  78        char string[ETH_GSTRING_LEN];
  79} bnx2x_stats_arr[] = {
  80/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  81                                8, false, "rx_bytes" },
  82        { STATS_OFFSET32(error_bytes_received_hi),
  83                                8, false, "rx_error_bytes" },
  84        { STATS_OFFSET32(total_unicast_packets_received_hi),
  85                                8, false, "rx_ucast_packets" },
  86        { STATS_OFFSET32(total_multicast_packets_received_hi),
  87                                8, false, "rx_mcast_packets" },
  88        { STATS_OFFSET32(total_broadcast_packets_received_hi),
  89                                8, false, "rx_bcast_packets" },
  90        { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  91                                8, true, "rx_crc_errors" },
  92        { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  93                                8, true, "rx_align_errors" },
  94        { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  95                                8, true, "rx_undersize_packets" },
  96        { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  97                                8, true, "rx_oversize_packets" },
  98/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
  99                                8, true, "rx_fragments" },
 100        { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 101                                8, true, "rx_jabbers" },
 102        { STATS_OFFSET32(no_buff_discard_hi),
 103                                8, false, "rx_discards" },
 104        { STATS_OFFSET32(mac_filter_discard),
 105                                4, true, "rx_filtered_packets" },
 106        { STATS_OFFSET32(mf_tag_discard),
 107                                4, true, "rx_mf_tag_discard" },
 108        { STATS_OFFSET32(pfc_frames_received_hi),
 109                                8, true, "pfc_frames_received" },
 110        { STATS_OFFSET32(pfc_frames_sent_hi),
 111                                8, true, "pfc_frames_sent" },
 112        { STATS_OFFSET32(brb_drop_hi),
 113                                8, true, "rx_brb_discard" },
 114        { STATS_OFFSET32(brb_truncate_hi),
 115                                8, true, "rx_brb_truncate" },
 116        { STATS_OFFSET32(pause_frames_received_hi),
 117                                8, true, "rx_pause_frames" },
 118        { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 119                                8, true, "rx_mac_ctrl_frames" },
 120        { STATS_OFFSET32(nig_timer_max),
 121                                4, true, "rx_constant_pause_events" },
 122/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 123                                4, false, "rx_phy_ip_err_discards"},
 124        { STATS_OFFSET32(rx_skb_alloc_failed),
 125                                4, false, "rx_skb_alloc_discard" },
 126        { STATS_OFFSET32(hw_csum_err),
 127                                4, false, "rx_csum_offload_errors" },
 128        { STATS_OFFSET32(driver_xoff),
 129                                4, false, "tx_exhaustion_events" },
 130        { STATS_OFFSET32(total_bytes_transmitted_hi),
 131                                8, false, "tx_bytes" },
 132        { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 133                                8, true, "tx_error_bytes" },
 134        { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 135                                8, false, "tx_ucast_packets" },
 136        { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 137                                8, false, "tx_mcast_packets" },
 138        { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 139                                8, false, "tx_bcast_packets" },
 140        { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 141                                8, true, "tx_mac_errors" },
 142        { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 143                                8, true, "tx_carrier_errors" },
 144/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 145                                8, true, "tx_single_collisions" },
 146        { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 147                                8, true, "tx_multi_collisions" },
 148        { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 149                                8, true, "tx_deferred" },
 150        { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 151                                8, true, "tx_excess_collisions" },
 152        { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 153                                8, true, "tx_late_collisions" },
 154        { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 155                                8, true, "tx_total_collisions" },
 156        { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 157                                8, true, "tx_64_byte_packets" },
 158        { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 159                                8, true, "tx_65_to_127_byte_packets" },
 160        { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 161                                8, true, "tx_128_to_255_byte_packets" },
 162        { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 163                                8, true, "tx_256_to_511_byte_packets" },
 164/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 165                                8, true, "tx_512_to_1023_byte_packets" },
 166        { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 167                                8, true, "tx_1024_to_1522_byte_packets" },
 168        { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 169                                8, true, "tx_1523_to_9022_byte_packets" },
 170        { STATS_OFFSET32(pause_frames_sent_hi),
 171                                8, true, "tx_pause_frames" },
 172        { STATS_OFFSET32(total_tpa_aggregations_hi),
 173                                8, false, "tpa_aggregations" },
 174        { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 175                                8, false, "tpa_aggregated_frames"},
 176        { STATS_OFFSET32(total_tpa_bytes_hi),
 177                                8, false, "tpa_bytes"},
 178        { STATS_OFFSET32(recoverable_error),
 179                                4, false, "recoverable_errors" },
 180        { STATS_OFFSET32(unrecoverable_error),
 181                                4, false, "unrecoverable_errors" },
 182        { STATS_OFFSET32(driver_filtered_tx_pkt),
 183                                4, false, "driver_filtered_tx_pkt" },
 184        { STATS_OFFSET32(eee_tx_lpi),
 185                                4, true, "Tx LPI entry count"}
 186};
 187
 188#define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 189
 190static int bnx2x_get_port_type(struct bnx2x *bp)
 191{
 192        int port_type;
 193        u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 194        switch (bp->link_params.phy[phy_idx].media_type) {
 195        case ETH_PHY_SFPP_10G_FIBER:
 196        case ETH_PHY_SFP_1G_FIBER:
 197        case ETH_PHY_XFP_FIBER:
 198        case ETH_PHY_KR:
 199        case ETH_PHY_CX4:
 200                port_type = PORT_FIBRE;
 201                break;
 202        case ETH_PHY_DA_TWINAX:
 203                port_type = PORT_DA;
 204                break;
 205        case ETH_PHY_BASE_T:
 206                port_type = PORT_TP;
 207                break;
 208        case ETH_PHY_NOT_PRESENT:
 209                port_type = PORT_NONE;
 210                break;
 211        case ETH_PHY_UNSPECIFIED:
 212        default:
 213                port_type = PORT_OTHER;
 214                break;
 215        }
 216        return port_type;
 217}
 218
 219static int bnx2x_get_vf_settings(struct net_device *dev,
 220                                 struct ethtool_cmd *cmd)
 221{
 222        struct bnx2x *bp = netdev_priv(dev);
 223
 224        if (bp->state == BNX2X_STATE_OPEN) {
 225                if (test_bit(BNX2X_LINK_REPORT_FD,
 226                             &bp->vf_link_vars.link_report_flags))
 227                        cmd->duplex = DUPLEX_FULL;
 228                else
 229                        cmd->duplex = DUPLEX_HALF;
 230
 231                ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed);
 232        } else {
 233                cmd->duplex = DUPLEX_UNKNOWN;
 234                ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
 235        }
 236
 237        cmd->port               = PORT_OTHER;
 238        cmd->phy_address        = 0;
 239        cmd->transceiver        = XCVR_INTERNAL;
 240        cmd->autoneg            = AUTONEG_DISABLE;
 241        cmd->maxtxpkt           = 0;
 242        cmd->maxrxpkt           = 0;
 243
 244        DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 245           "  supported 0x%x  advertising 0x%x  speed %u\n"
 246           "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 247           "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 248           cmd->cmd, cmd->supported, cmd->advertising,
 249           ethtool_cmd_speed(cmd),
 250           cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 251           cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 252
 253        return 0;
 254}
 255
 256static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 257{
 258        struct bnx2x *bp = netdev_priv(dev);
 259        int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 260        u32 media_type;
 261
 262        /* Dual Media boards present all available port types */
 263        cmd->supported = bp->port.supported[cfg_idx] |
 264                (bp->port.supported[cfg_idx ^ 1] &
 265                 (SUPPORTED_TP | SUPPORTED_FIBRE));
 266        cmd->advertising = bp->port.advertising[cfg_idx];
 267        media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
 268        if (media_type == ETH_PHY_SFP_1G_FIBER) {
 269                cmd->supported &= ~(SUPPORTED_10000baseT_Full);
 270                cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
 271        }
 272
 273        if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
 274            !(bp->flags & MF_FUNC_DIS)) {
 275                cmd->duplex = bp->link_vars.duplex;
 276
 277                if (IS_MF(bp) && !BP_NOMCP(bp))
 278                        ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 279                else
 280                        ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 281        } else {
 282                cmd->duplex = DUPLEX_UNKNOWN;
 283                ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
 284        }
 285
 286        cmd->port = bnx2x_get_port_type(bp);
 287
 288        cmd->phy_address = bp->mdio.prtad;
 289        cmd->transceiver = XCVR_INTERNAL;
 290
 291        if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 292                cmd->autoneg = AUTONEG_ENABLE;
 293        else
 294                cmd->autoneg = AUTONEG_DISABLE;
 295
 296        /* Publish LP advertised speeds and FC */
 297        if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
 298                u32 status = bp->link_vars.link_status;
 299
 300                cmd->lp_advertising |= ADVERTISED_Autoneg;
 301                if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
 302                        cmd->lp_advertising |= ADVERTISED_Pause;
 303                if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 304                        cmd->lp_advertising |= ADVERTISED_Asym_Pause;
 305
 306                if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
 307                        cmd->lp_advertising |= ADVERTISED_10baseT_Half;
 308                if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
 309                        cmd->lp_advertising |= ADVERTISED_10baseT_Full;
 310                if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
 311                        cmd->lp_advertising |= ADVERTISED_100baseT_Half;
 312                if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
 313                        cmd->lp_advertising |= ADVERTISED_100baseT_Full;
 314                if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
 315                        cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
 316                if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
 317                        if (media_type == ETH_PHY_KR) {
 318                                cmd->lp_advertising |=
 319                                        ADVERTISED_1000baseKX_Full;
 320                        } else {
 321                                cmd->lp_advertising |=
 322                                        ADVERTISED_1000baseT_Full;
 323                        }
 324                }
 325                if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
 326                        cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
 327                if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
 328                        if (media_type == ETH_PHY_KR) {
 329                                cmd->lp_advertising |=
 330                                        ADVERTISED_10000baseKR_Full;
 331                        } else {
 332                                cmd->lp_advertising |=
 333                                        ADVERTISED_10000baseT_Full;
 334                        }
 335                }
 336                if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
 337                        cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
 338        }
 339
 340        cmd->maxtxpkt = 0;
 341        cmd->maxrxpkt = 0;
 342
 343        DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 344           "  supported 0x%x  advertising 0x%x  speed %u\n"
 345           "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 346           "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 347           cmd->cmd, cmd->supported, cmd->advertising,
 348           ethtool_cmd_speed(cmd),
 349           cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 350           cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 351
 352        return 0;
 353}
 354
 355static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 356{
 357        struct bnx2x *bp = netdev_priv(dev);
 358        u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 359        u32 speed, phy_idx;
 360
 361        if (IS_MF_SD(bp))
 362                return 0;
 363
 364        DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 365           "  supported 0x%x  advertising 0x%x  speed %u\n"
 366           "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 367           "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 368           cmd->cmd, cmd->supported, cmd->advertising,
 369           ethtool_cmd_speed(cmd),
 370           cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 371           cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 372
 373        speed = ethtool_cmd_speed(cmd);
 374
 375        /* If received a request for an unknown duplex, assume full*/
 376        if (cmd->duplex == DUPLEX_UNKNOWN)
 377                cmd->duplex = DUPLEX_FULL;
 378
 379        if (IS_MF_SI(bp)) {
 380                u32 part;
 381                u32 line_speed = bp->link_vars.line_speed;
 382
 383                /* use 10G if no link detected */
 384                if (!line_speed)
 385                        line_speed = 10000;
 386
 387                if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 388                        DP(BNX2X_MSG_ETHTOOL,
 389                           "To set speed BC %X or higher is required, please upgrade BC\n",
 390                           REQ_BC_VER_4_SET_MF_BW);
 391                        return -EINVAL;
 392                }
 393
 394                part = (speed * 100) / line_speed;
 395
 396                if (line_speed < speed || !part) {
 397                        DP(BNX2X_MSG_ETHTOOL,
 398                           "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
 399                        return -EINVAL;
 400                }
 401
 402                if (bp->state != BNX2X_STATE_OPEN)
 403                        /* store value for following "load" */
 404                        bp->pending_max = part;
 405                else
 406                        bnx2x_update_max_mf_config(bp, part);
 407
 408                return 0;
 409        }
 410
 411        cfg_idx = bnx2x_get_link_cfg_idx(bp);
 412        old_multi_phy_config = bp->link_params.multi_phy_config;
 413        if (cmd->port != bnx2x_get_port_type(bp)) {
 414                switch (cmd->port) {
 415                case PORT_TP:
 416                        if (!(bp->port.supported[0] & SUPPORTED_TP ||
 417                              bp->port.supported[1] & SUPPORTED_TP)) {
 418                                DP(BNX2X_MSG_ETHTOOL,
 419                                   "Unsupported port type\n");
 420                                return -EINVAL;
 421                        }
 422                        bp->link_params.multi_phy_config &=
 423                                ~PORT_HW_CFG_PHY_SELECTION_MASK;
 424                        if (bp->link_params.multi_phy_config &
 425                            PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 426                                bp->link_params.multi_phy_config |=
 427                                PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 428                        else
 429                                bp->link_params.multi_phy_config |=
 430                                PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 431                        break;
 432                case PORT_FIBRE:
 433                case PORT_DA:
 434                case PORT_NONE:
 435                        if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 436                              bp->port.supported[1] & SUPPORTED_FIBRE)) {
 437                                DP(BNX2X_MSG_ETHTOOL,
 438                                   "Unsupported port type\n");
 439                                return -EINVAL;
 440                        }
 441                        bp->link_params.multi_phy_config &=
 442                                ~PORT_HW_CFG_PHY_SELECTION_MASK;
 443                        if (bp->link_params.multi_phy_config &
 444                            PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 445                                bp->link_params.multi_phy_config |=
 446                                PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 447                        else
 448                                bp->link_params.multi_phy_config |=
 449                                PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 450                        break;
 451                default:
 452                        DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 453                        return -EINVAL;
 454                }
 455        }
 456        /* Save new config in case command complete successfully */
 457        new_multi_phy_config = bp->link_params.multi_phy_config;
 458        /* Get the new cfg_idx */
 459        cfg_idx = bnx2x_get_link_cfg_idx(bp);
 460        /* Restore old config in case command failed */
 461        bp->link_params.multi_phy_config = old_multi_phy_config;
 462        DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
 463
 464        if (cmd->autoneg == AUTONEG_ENABLE) {
 465                u32 an_supported_speed = bp->port.supported[cfg_idx];
 466                if (bp->link_params.phy[EXT_PHY1].type ==
 467                    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
 468                        an_supported_speed |= (SUPPORTED_100baseT_Half |
 469                                               SUPPORTED_100baseT_Full);
 470                if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 471                        DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
 472                        return -EINVAL;
 473                }
 474
 475                /* advertise the requested speed and duplex if supported */
 476                if (cmd->advertising & ~an_supported_speed) {
 477                        DP(BNX2X_MSG_ETHTOOL,
 478                           "Advertisement parameters are not supported\n");
 479                        return -EINVAL;
 480                }
 481
 482                bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 483                bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 484                bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
 485                                         cmd->advertising);
 486                if (cmd->advertising) {
 487
 488                        bp->link_params.speed_cap_mask[cfg_idx] = 0;
 489                        if (cmd->advertising & ADVERTISED_10baseT_Half) {
 490                                bp->link_params.speed_cap_mask[cfg_idx] |=
 491                                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
 492                        }
 493                        if (cmd->advertising & ADVERTISED_10baseT_Full)
 494                                bp->link_params.speed_cap_mask[cfg_idx] |=
 495                                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
 496
 497                        if (cmd->advertising & ADVERTISED_100baseT_Full)
 498                                bp->link_params.speed_cap_mask[cfg_idx] |=
 499                                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
 500
 501                        if (cmd->advertising & ADVERTISED_100baseT_Half) {
 502                                bp->link_params.speed_cap_mask[cfg_idx] |=
 503                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
 504                        }
 505                        if (cmd->advertising & ADVERTISED_1000baseT_Half) {
 506                                bp->link_params.speed_cap_mask[cfg_idx] |=
 507                                        PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 508                        }
 509                        if (cmd->advertising & (ADVERTISED_1000baseT_Full |
 510                                                ADVERTISED_1000baseKX_Full))
 511                                bp->link_params.speed_cap_mask[cfg_idx] |=
 512                                        PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 513
 514                        if (cmd->advertising & (ADVERTISED_10000baseT_Full |
 515                                                ADVERTISED_10000baseKX4_Full |
 516                                                ADVERTISED_10000baseKR_Full))
 517                                bp->link_params.speed_cap_mask[cfg_idx] |=
 518                                        PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
 519
 520                        if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
 521                                bp->link_params.speed_cap_mask[cfg_idx] |=
 522                                        PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
 523                }
 524        } else { /* forced speed */
 525                /* advertise the requested speed and duplex if supported */
 526                switch (speed) {
 527                case SPEED_10:
 528                        if (cmd->duplex == DUPLEX_FULL) {
 529                                if (!(bp->port.supported[cfg_idx] &
 530                                      SUPPORTED_10baseT_Full)) {
 531                                        DP(BNX2X_MSG_ETHTOOL,
 532                                           "10M full not supported\n");
 533                                        return -EINVAL;
 534                                }
 535
 536                                advertising = (ADVERTISED_10baseT_Full |
 537                                               ADVERTISED_TP);
 538                        } else {
 539                                if (!(bp->port.supported[cfg_idx] &
 540                                      SUPPORTED_10baseT_Half)) {
 541                                        DP(BNX2X_MSG_ETHTOOL,
 542                                           "10M half not supported\n");
 543                                        return -EINVAL;
 544                                }
 545
 546                                advertising = (ADVERTISED_10baseT_Half |
 547                                               ADVERTISED_TP);
 548                        }
 549                        break;
 550
 551                case SPEED_100:
 552                        if (cmd->duplex == DUPLEX_FULL) {
 553                                if (!(bp->port.supported[cfg_idx] &
 554                                                SUPPORTED_100baseT_Full)) {
 555                                        DP(BNX2X_MSG_ETHTOOL,
 556                                           "100M full not supported\n");
 557                                        return -EINVAL;
 558                                }
 559
 560                                advertising = (ADVERTISED_100baseT_Full |
 561                                               ADVERTISED_TP);
 562                        } else {
 563                                if (!(bp->port.supported[cfg_idx] &
 564                                                SUPPORTED_100baseT_Half)) {
 565                                        DP(BNX2X_MSG_ETHTOOL,
 566                                           "100M half not supported\n");
 567                                        return -EINVAL;
 568                                }
 569
 570                                advertising = (ADVERTISED_100baseT_Half |
 571                                               ADVERTISED_TP);
 572                        }
 573                        break;
 574
 575                case SPEED_1000:
 576                        if (cmd->duplex != DUPLEX_FULL) {
 577                                DP(BNX2X_MSG_ETHTOOL,
 578                                   "1G half not supported\n");
 579                                return -EINVAL;
 580                        }
 581
 582                        if (bp->port.supported[cfg_idx] &
 583                             SUPPORTED_1000baseT_Full) {
 584                                advertising = (ADVERTISED_1000baseT_Full |
 585                                               ADVERTISED_TP);
 586
 587                        } else if (bp->port.supported[cfg_idx] &
 588                                   SUPPORTED_1000baseKX_Full) {
 589                                advertising = ADVERTISED_1000baseKX_Full;
 590                        } else {
 591                                DP(BNX2X_MSG_ETHTOOL,
 592                                   "1G full not supported\n");
 593                                return -EINVAL;
 594                        }
 595
 596                        break;
 597
 598                case SPEED_2500:
 599                        if (cmd->duplex != DUPLEX_FULL) {
 600                                DP(BNX2X_MSG_ETHTOOL,
 601                                   "2.5G half not supported\n");
 602                                return -EINVAL;
 603                        }
 604
 605                        if (!(bp->port.supported[cfg_idx]
 606                              & SUPPORTED_2500baseX_Full)) {
 607                                DP(BNX2X_MSG_ETHTOOL,
 608                                   "2.5G full not supported\n");
 609                                return -EINVAL;
 610                        }
 611
 612                        advertising = (ADVERTISED_2500baseX_Full |
 613                                       ADVERTISED_TP);
 614                        break;
 615
 616                case SPEED_10000:
 617                        if (cmd->duplex != DUPLEX_FULL) {
 618                                DP(BNX2X_MSG_ETHTOOL,
 619                                   "10G half not supported\n");
 620                                return -EINVAL;
 621                        }
 622                        phy_idx = bnx2x_get_cur_phy_idx(bp);
 623                        if ((bp->port.supported[cfg_idx] &
 624                             SUPPORTED_10000baseT_Full) &&
 625                            (bp->link_params.phy[phy_idx].media_type !=
 626                             ETH_PHY_SFP_1G_FIBER)) {
 627                                advertising = (ADVERTISED_10000baseT_Full |
 628                                               ADVERTISED_FIBRE);
 629                        } else if (bp->port.supported[cfg_idx] &
 630                               SUPPORTED_10000baseKR_Full) {
 631                                advertising = (ADVERTISED_10000baseKR_Full |
 632                                               ADVERTISED_FIBRE);
 633                        } else {
 634                                DP(BNX2X_MSG_ETHTOOL,
 635                                   "10G full not supported\n");
 636                                return -EINVAL;
 637                        }
 638
 639                        break;
 640
 641                default:
 642                        DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
 643                        return -EINVAL;
 644                }
 645
 646                bp->link_params.req_line_speed[cfg_idx] = speed;
 647                bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 648                bp->port.advertising[cfg_idx] = advertising;
 649        }
 650
 651        DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
 652           "  req_duplex %d  advertising 0x%x\n",
 653           bp->link_params.req_line_speed[cfg_idx],
 654           bp->link_params.req_duplex[cfg_idx],
 655           bp->port.advertising[cfg_idx]);
 656
 657        /* Set new config */
 658        bp->link_params.multi_phy_config = new_multi_phy_config;
 659        if (netif_running(dev)) {
 660                bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 661                bnx2x_force_link_reset(bp);
 662                bnx2x_link_set(bp);
 663        }
 664
 665        return 0;
 666}
 667
 668#define DUMP_ALL_PRESETS                0x1FFF
 669#define DUMP_MAX_PRESETS                13
 670
 671static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
 672{
 673        if (CHIP_IS_E1(bp))
 674                return dump_num_registers[0][preset-1];
 675        else if (CHIP_IS_E1H(bp))
 676                return dump_num_registers[1][preset-1];
 677        else if (CHIP_IS_E2(bp))
 678                return dump_num_registers[2][preset-1];
 679        else if (CHIP_IS_E3A0(bp))
 680                return dump_num_registers[3][preset-1];
 681        else if (CHIP_IS_E3B0(bp))
 682                return dump_num_registers[4][preset-1];
 683        else
 684                return 0;
 685}
 686
 687static int __bnx2x_get_regs_len(struct bnx2x *bp)
 688{
 689        u32 preset_idx;
 690        int regdump_len = 0;
 691
 692        /* Calculate the total preset regs length */
 693        for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
 694                regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
 695
 696        return regdump_len;
 697}
 698
 699static int bnx2x_get_regs_len(struct net_device *dev)
 700{
 701        struct bnx2x *bp = netdev_priv(dev);
 702        int regdump_len = 0;
 703
 704        if (IS_VF(bp))
 705                return 0;
 706
 707        regdump_len = __bnx2x_get_regs_len(bp);
 708        regdump_len *= 4;
 709        regdump_len += sizeof(struct dump_header);
 710
 711        return regdump_len;
 712}
 713
 714#define IS_E1_REG(chips)        ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
 715#define IS_E1H_REG(chips)       ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
 716#define IS_E2_REG(chips)        ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
 717#define IS_E3A0_REG(chips)      ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
 718#define IS_E3B0_REG(chips)      ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
 719
 720#define IS_REG_IN_PRESET(presets, idx)  \
 721                ((presets & (1 << (idx-1))) == (1 << (idx-1)))
 722
 723/******* Paged registers info selectors ********/
 724static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 725{
 726        if (CHIP_IS_E2(bp))
 727                return page_vals_e2;
 728        else if (CHIP_IS_E3(bp))
 729                return page_vals_e3;
 730        else
 731                return NULL;
 732}
 733
 734static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 735{
 736        if (CHIP_IS_E2(bp))
 737                return PAGE_MODE_VALUES_E2;
 738        else if (CHIP_IS_E3(bp))
 739                return PAGE_MODE_VALUES_E3;
 740        else
 741                return 0;
 742}
 743
 744static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 745{
 746        if (CHIP_IS_E2(bp))
 747                return page_write_regs_e2;
 748        else if (CHIP_IS_E3(bp))
 749                return page_write_regs_e3;
 750        else
 751                return NULL;
 752}
 753
 754static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 755{
 756        if (CHIP_IS_E2(bp))
 757                return PAGE_WRITE_REGS_E2;
 758        else if (CHIP_IS_E3(bp))
 759                return PAGE_WRITE_REGS_E3;
 760        else
 761                return 0;
 762}
 763
 764static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 765{
 766        if (CHIP_IS_E2(bp))
 767                return page_read_regs_e2;
 768        else if (CHIP_IS_E3(bp))
 769                return page_read_regs_e3;
 770        else
 771                return NULL;
 772}
 773
 774static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 775{
 776        if (CHIP_IS_E2(bp))
 777                return PAGE_READ_REGS_E2;
 778        else if (CHIP_IS_E3(bp))
 779                return PAGE_READ_REGS_E3;
 780        else
 781                return 0;
 782}
 783
 784static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
 785                                       const struct reg_addr *reg_info)
 786{
 787        if (CHIP_IS_E1(bp))
 788                return IS_E1_REG(reg_info->chips);
 789        else if (CHIP_IS_E1H(bp))
 790                return IS_E1H_REG(reg_info->chips);
 791        else if (CHIP_IS_E2(bp))
 792                return IS_E2_REG(reg_info->chips);
 793        else if (CHIP_IS_E3A0(bp))
 794                return IS_E3A0_REG(reg_info->chips);
 795        else if (CHIP_IS_E3B0(bp))
 796                return IS_E3B0_REG(reg_info->chips);
 797        else
 798                return false;
 799}
 800
 801static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
 802        const struct wreg_addr *wreg_info)
 803{
 804        if (CHIP_IS_E1(bp))
 805                return IS_E1_REG(wreg_info->chips);
 806        else if (CHIP_IS_E1H(bp))
 807                return IS_E1H_REG(wreg_info->chips);
 808        else if (CHIP_IS_E2(bp))
 809                return IS_E2_REG(wreg_info->chips);
 810        else if (CHIP_IS_E3A0(bp))
 811                return IS_E3A0_REG(wreg_info->chips);
 812        else if (CHIP_IS_E3B0(bp))
 813                return IS_E3B0_REG(wreg_info->chips);
 814        else
 815                return false;
 816}
 817
 818/**
 819 * bnx2x_read_pages_regs - read "paged" registers
 820 *
 821 * @bp          device handle
 822 * @p           output buffer
 823 *
 824 * Reads "paged" memories: memories that may only be read by first writing to a
 825 * specific address ("write address") and then reading from a specific address
 826 * ("read address"). There may be more than one write address per "page" and
 827 * more than one read address per write address.
 828 */
 829static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
 830{
 831        u32 i, j, k, n;
 832
 833        /* addresses of the paged registers */
 834        const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 835        /* number of paged registers */
 836        int num_pages = __bnx2x_get_page_reg_num(bp);
 837        /* write addresses */
 838        const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 839        /* number of write addresses */
 840        int write_num = __bnx2x_get_page_write_num(bp);
 841        /* read addresses info */
 842        const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 843        /* number of read addresses */
 844        int read_num = __bnx2x_get_page_read_num(bp);
 845        u32 addr, size;
 846
 847        for (i = 0; i < num_pages; i++) {
 848                for (j = 0; j < write_num; j++) {
 849                        REG_WR(bp, write_addr[j], page_addr[i]);
 850
 851                        for (k = 0; k < read_num; k++) {
 852                                if (IS_REG_IN_PRESET(read_addr[k].presets,
 853                                                     preset)) {
 854                                        size = read_addr[k].size;
 855                                        for (n = 0; n < size; n++) {
 856                                                addr = read_addr[k].addr + n*4;
 857                                                *p++ = REG_RD(bp, addr);
 858                                        }
 859                                }
 860                        }
 861                }
 862        }
 863}
 864
 865static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
 866{
 867        u32 i, j, addr;
 868        const struct wreg_addr *wreg_addr_p = NULL;
 869
 870        if (CHIP_IS_E1(bp))
 871                wreg_addr_p = &wreg_addr_e1;
 872        else if (CHIP_IS_E1H(bp))
 873                wreg_addr_p = &wreg_addr_e1h;
 874        else if (CHIP_IS_E2(bp))
 875                wreg_addr_p = &wreg_addr_e2;
 876        else if (CHIP_IS_E3A0(bp))
 877                wreg_addr_p = &wreg_addr_e3;
 878        else if (CHIP_IS_E3B0(bp))
 879                wreg_addr_p = &wreg_addr_e3b0;
 880
 881        /* Read the idle_chk registers */
 882        for (i = 0; i < IDLE_REGS_COUNT; i++) {
 883                if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
 884                    IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
 885                        for (j = 0; j < idle_reg_addrs[i].size; j++)
 886                                *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
 887                }
 888        }
 889
 890        /* Read the regular registers */
 891        for (i = 0; i < REGS_COUNT; i++) {
 892                if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
 893                    IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
 894                        for (j = 0; j < reg_addrs[i].size; j++)
 895                                *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 896                }
 897        }
 898
 899        /* Read the CAM registers */
 900        if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
 901            IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
 902                for (i = 0; i < wreg_addr_p->size; i++) {
 903                        *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
 904
 905                        /* In case of wreg_addr register, read additional
 906                           registers from read_regs array
 907                        */
 908                        for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
 909                                addr = *(wreg_addr_p->read_regs);
 910                                *p++ = REG_RD(bp, addr + j*4);
 911                        }
 912                }
 913        }
 914
 915        /* Paged registers are supported in E2 & E3 only */
 916        if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
 917                /* Read "paged" registers */
 918                bnx2x_read_pages_regs(bp, p, preset);
 919        }
 920
 921        return 0;
 922}
 923
 924static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 925{
 926        u32 preset_idx;
 927
 928        /* Read all registers, by reading all preset registers */
 929        for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
 930                /* Skip presets with IOR */
 931                if ((preset_idx == 2) ||
 932                    (preset_idx == 5) ||
 933                    (preset_idx == 8) ||
 934                    (preset_idx == 11))
 935                        continue;
 936                __bnx2x_get_preset_regs(bp, p, preset_idx);
 937                p += __bnx2x_get_preset_regs_len(bp, preset_idx);
 938        }
 939}
 940
 941static void bnx2x_get_regs(struct net_device *dev,
 942                           struct ethtool_regs *regs, void *_p)
 943{
 944        u32 *p = _p;
 945        struct bnx2x *bp = netdev_priv(dev);
 946        struct dump_header dump_hdr = {0};
 947
 948        regs->version = 2;
 949        memset(p, 0, regs->len);
 950
 951        if (!netif_running(bp->dev))
 952                return;
 953
 954        /* Disable parity attentions as long as following dump may
 955         * cause false alarms by reading never written registers. We
 956         * will re-enable parity attentions right after the dump.
 957         */
 958
 959        bnx2x_disable_blocks_parity(bp);
 960
 961        dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
 962        dump_hdr.preset = DUMP_ALL_PRESETS;
 963        dump_hdr.version = BNX2X_DUMP_VERSION;
 964
 965        /* dump_meta_data presents OR of CHIP and PATH. */
 966        if (CHIP_IS_E1(bp)) {
 967                dump_hdr.dump_meta_data = DUMP_CHIP_E1;
 968        } else if (CHIP_IS_E1H(bp)) {
 969                dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
 970        } else if (CHIP_IS_E2(bp)) {
 971                dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
 972                (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 973        } else if (CHIP_IS_E3A0(bp)) {
 974                dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
 975                (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 976        } else if (CHIP_IS_E3B0(bp)) {
 977                dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
 978                (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 979        }
 980
 981        memcpy(p, &dump_hdr, sizeof(struct dump_header));
 982        p += dump_hdr.header_size + 1;
 983
 984        /* This isn't really an error, but since attention handling is going
 985         * to print the GRC timeouts using this macro, we use the same.
 986         */
 987        BNX2X_ERR("Generating register dump. Might trigger harmless GRC timeouts\n");
 988
 989        /* Actually read the registers */
 990        __bnx2x_get_regs(bp, p);
 991
 992        /* Re-enable parity attentions */
 993        bnx2x_clear_blocks_parity(bp);
 994        bnx2x_enable_blocks_parity(bp);
 995}
 996
 997static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
 998{
 999        struct bnx2x *bp = netdev_priv(dev);
1000        int regdump_len = 0;
1001
1002        regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
1003        regdump_len *= 4;
1004        regdump_len += sizeof(struct dump_header);
1005
1006        return regdump_len;
1007}
1008
1009static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
1010{
1011        struct bnx2x *bp = netdev_priv(dev);
1012
1013        /* Use the ethtool_dump "flag" field as the dump preset index */
1014        if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
1015                return -EINVAL;
1016
1017        bp->dump_preset_idx = val->flag;
1018        return 0;
1019}
1020
1021static int bnx2x_get_dump_flag(struct net_device *dev,
1022                               struct ethtool_dump *dump)
1023{
1024        struct bnx2x *bp = netdev_priv(dev);
1025
1026        dump->version = BNX2X_DUMP_VERSION;
1027        dump->flag = bp->dump_preset_idx;
1028        /* Calculate the requested preset idx length */
1029        dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
1030        DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1031           bp->dump_preset_idx, dump->len);
1032        return 0;
1033}
1034
1035static int bnx2x_get_dump_data(struct net_device *dev,
1036                               struct ethtool_dump *dump,
1037                               void *buffer)
1038{
1039        u32 *p = buffer;
1040        struct bnx2x *bp = netdev_priv(dev);
1041        struct dump_header dump_hdr = {0};
1042
1043        /* Disable parity attentions as long as following dump may
1044         * cause false alarms by reading never written registers. We
1045         * will re-enable parity attentions right after the dump.
1046         */
1047
1048        bnx2x_disable_blocks_parity(bp);
1049
1050        dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1051        dump_hdr.preset = bp->dump_preset_idx;
1052        dump_hdr.version = BNX2X_DUMP_VERSION;
1053
1054        DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1055
1056        /* dump_meta_data presents OR of CHIP and PATH. */
1057        if (CHIP_IS_E1(bp)) {
1058                dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1059        } else if (CHIP_IS_E1H(bp)) {
1060                dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1061        } else if (CHIP_IS_E2(bp)) {
1062                dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1063                (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1064        } else if (CHIP_IS_E3A0(bp)) {
1065                dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1066                (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1067        } else if (CHIP_IS_E3B0(bp)) {
1068                dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1069                (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1070        }
1071
1072        memcpy(p, &dump_hdr, sizeof(struct dump_header));
1073        p += dump_hdr.header_size + 1;
1074
1075        /* Actually read the registers */
1076        __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1077
1078        /* Re-enable parity attentions */
1079        bnx2x_clear_blocks_parity(bp);
1080        bnx2x_enable_blocks_parity(bp);
1081
1082        return 0;
1083}
1084
1085static void bnx2x_get_drvinfo(struct net_device *dev,
1086                              struct ethtool_drvinfo *info)
1087{
1088        struct bnx2x *bp = netdev_priv(dev);
1089
1090        strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1091        strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1092
1093        bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1094
1095        strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1096}
1097
1098static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1099{
1100        struct bnx2x *bp = netdev_priv(dev);
1101
1102        if (bp->flags & NO_WOL_FLAG) {
1103                wol->supported = 0;
1104                wol->wolopts = 0;
1105        } else {
1106                wol->supported = WAKE_MAGIC;
1107                if (bp->wol)
1108                        wol->wolopts = WAKE_MAGIC;
1109                else
1110                        wol->wolopts = 0;
1111        }
1112        memset(&wol->sopass, 0, sizeof(wol->sopass));
1113}
1114
1115static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1116{
1117        struct bnx2x *bp = netdev_priv(dev);
1118
1119        if (wol->wolopts & ~WAKE_MAGIC) {
1120                DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1121                return -EINVAL;
1122        }
1123
1124        if (wol->wolopts & WAKE_MAGIC) {
1125                if (bp->flags & NO_WOL_FLAG) {
1126                        DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1127                        return -EINVAL;
1128                }
1129                bp->wol = 1;
1130        } else
1131                bp->wol = 0;
1132
1133        if (SHMEM2_HAS(bp, curr_cfg))
1134                SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
1135
1136        return 0;
1137}
1138
1139static u32 bnx2x_get_msglevel(struct net_device *dev)
1140{
1141        struct bnx2x *bp = netdev_priv(dev);
1142
1143        return bp->msg_enable;
1144}
1145
1146static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1147{
1148        struct bnx2x *bp = netdev_priv(dev);
1149
1150        if (capable(CAP_NET_ADMIN)) {
1151                /* dump MCP trace */
1152                if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1153                        bnx2x_fw_dump_lvl(bp, KERN_INFO);
1154                bp->msg_enable = level;
1155        }
1156}
1157
1158static int bnx2x_nway_reset(struct net_device *dev)
1159{
1160        struct bnx2x *bp = netdev_priv(dev);
1161
1162        if (!bp->port.pmf)
1163                return 0;
1164
1165        if (netif_running(dev)) {
1166                bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1167                bnx2x_force_link_reset(bp);
1168                bnx2x_link_set(bp);
1169        }
1170
1171        return 0;
1172}
1173
1174static u32 bnx2x_get_link(struct net_device *dev)
1175{
1176        struct bnx2x *bp = netdev_priv(dev);
1177
1178        if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1179                return 0;
1180
1181        if (IS_VF(bp))
1182                return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1183                                 &bp->vf_link_vars.link_report_flags);
1184
1185        return bp->link_vars.link_up;
1186}
1187
1188static int bnx2x_get_eeprom_len(struct net_device *dev)
1189{
1190        struct bnx2x *bp = netdev_priv(dev);
1191
1192        return bp->common.flash_size;
1193}
1194
1195/* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1196 * had we done things the other way around, if two pfs from the same port would
1197 * attempt to access nvram at the same time, we could run into a scenario such
1198 * as:
1199 * pf A takes the port lock.
1200 * pf B succeeds in taking the same lock since they are from the same port.
1201 * pf A takes the per pf misc lock. Performs eeprom access.
1202 * pf A finishes. Unlocks the per pf misc lock.
1203 * Pf B takes the lock and proceeds to perform it's own access.
1204 * pf A unlocks the per port lock, while pf B is still working (!).
1205 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1206 * access corrupted by pf B)
1207 */
1208static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1209{
1210        int port = BP_PORT(bp);
1211        int count, i;
1212        u32 val;
1213
1214        /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1215        bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1216
1217        /* adjust timeout for emulation/FPGA */
1218        count = BNX2X_NVRAM_TIMEOUT_COUNT;
1219        if (CHIP_REV_IS_SLOW(bp))
1220                count *= 100;
1221
1222        /* request access to nvram interface */
1223        REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1224               (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1225
1226        for (i = 0; i < count*10; i++) {
1227                val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1228                if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1229                        break;
1230
1231                udelay(5);
1232        }
1233
1234        if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1235                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1236                   "cannot get access to nvram interface\n");
1237                bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1238                return -EBUSY;
1239        }
1240
1241        return 0;
1242}
1243
1244static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1245{
1246        int port = BP_PORT(bp);
1247        int count, i;
1248        u32 val;
1249
1250        /* adjust timeout for emulation/FPGA */
1251        count = BNX2X_NVRAM_TIMEOUT_COUNT;
1252        if (CHIP_REV_IS_SLOW(bp))
1253                count *= 100;
1254
1255        /* relinquish nvram interface */
1256        REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1257               (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1258
1259        for (i = 0; i < count*10; i++) {
1260                val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1261                if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1262                        break;
1263
1264                udelay(5);
1265        }
1266
1267        if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1268                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1269                   "cannot free access to nvram interface\n");
1270                return -EBUSY;
1271        }
1272
1273        /* release HW lock: protect against other PFs in PF Direct Assignment */
1274        bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1275        return 0;
1276}
1277
1278static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1279{
1280        u32 val;
1281
1282        val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1283
1284        /* enable both bits, even on read */
1285        REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1286               (val | MCPR_NVM_ACCESS_ENABLE_EN |
1287                      MCPR_NVM_ACCESS_ENABLE_WR_EN));
1288}
1289
1290static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1291{
1292        u32 val;
1293
1294        val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1295
1296        /* disable both bits, even after read */
1297        REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1298               (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1299                        MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1300}
1301
1302static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1303                                  u32 cmd_flags)
1304{
1305        int count, i, rc;
1306        u32 val;
1307
1308        /* build the command word */
1309        cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1310
1311        /* need to clear DONE bit separately */
1312        REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1313
1314        /* address of the NVRAM to read from */
1315        REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1316               (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1317
1318        /* issue a read command */
1319        REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1320
1321        /* adjust timeout for emulation/FPGA */
1322        count = BNX2X_NVRAM_TIMEOUT_COUNT;
1323        if (CHIP_REV_IS_SLOW(bp))
1324                count *= 100;
1325
1326        /* wait for completion */
1327        *ret_val = 0;
1328        rc = -EBUSY;
1329        for (i = 0; i < count; i++) {
1330                udelay(5);
1331                val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1332
1333                if (val & MCPR_NVM_COMMAND_DONE) {
1334                        val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1335                        /* we read nvram data in cpu order
1336                         * but ethtool sees it as an array of bytes
1337                         * converting to big-endian will do the work
1338                         */
1339                        *ret_val = cpu_to_be32(val);
1340                        rc = 0;
1341                        break;
1342                }
1343        }
1344        if (rc == -EBUSY)
1345                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1346                   "nvram read timeout expired\n");
1347        return rc;
1348}
1349
1350int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1351                     int buf_size)
1352{
1353        int rc;
1354        u32 cmd_flags;
1355        __be32 val;
1356
1357        if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1358                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1359                   "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1360                   offset, buf_size);
1361                return -EINVAL;
1362        }
1363
1364        if (offset + buf_size > bp->common.flash_size) {
1365                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1366                   "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1367                   offset, buf_size, bp->common.flash_size);
1368                return -EINVAL;
1369        }
1370
1371        /* request access to nvram interface */
1372        rc = bnx2x_acquire_nvram_lock(bp);
1373        if (rc)
1374                return rc;
1375
1376        /* enable access to nvram interface */
1377        bnx2x_enable_nvram_access(bp);
1378
1379        /* read the first word(s) */
1380        cmd_flags = MCPR_NVM_COMMAND_FIRST;
1381        while ((buf_size > sizeof(u32)) && (rc == 0)) {
1382                rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1383                memcpy(ret_buf, &val, 4);
1384
1385                /* advance to the next dword */
1386                offset += sizeof(u32);
1387                ret_buf += sizeof(u32);
1388                buf_size -= sizeof(u32);
1389                cmd_flags = 0;
1390        }
1391
1392        if (rc == 0) {
1393                cmd_flags |= MCPR_NVM_COMMAND_LAST;
1394                rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1395                memcpy(ret_buf, &val, 4);
1396        }
1397
1398        /* disable access to nvram interface */
1399        bnx2x_disable_nvram_access(bp);
1400        bnx2x_release_nvram_lock(bp);
1401
1402        return rc;
1403}
1404
1405static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1406                              int buf_size)
1407{
1408        int rc;
1409
1410        rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1411
1412        if (!rc) {
1413                __be32 *be = (__be32 *)buf;
1414
1415                while ((buf_size -= 4) >= 0)
1416                        *buf++ = be32_to_cpu(*be++);
1417        }
1418
1419        return rc;
1420}
1421
1422static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1423{
1424        int rc = 1;
1425        u16 pm = 0;
1426        struct net_device *dev = pci_get_drvdata(bp->pdev);
1427
1428        if (bp->pdev->pm_cap)
1429                rc = pci_read_config_word(bp->pdev,
1430                                          bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1431
1432        if ((rc && !netif_running(dev)) ||
1433            (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1434                return false;
1435
1436        return true;
1437}
1438
1439static int bnx2x_get_eeprom(struct net_device *dev,
1440                            struct ethtool_eeprom *eeprom, u8 *eebuf)
1441{
1442        struct bnx2x *bp = netdev_priv(dev);
1443
1444        if (!bnx2x_is_nvm_accessible(bp)) {
1445                DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1446                   "cannot access eeprom when the interface is down\n");
1447                return -EAGAIN;
1448        }
1449
1450        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1451           "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1452           eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1453           eeprom->len, eeprom->len);
1454
1455        /* parameters already validated in ethtool_get_eeprom */
1456
1457        return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1458}
1459
1460static int bnx2x_get_module_eeprom(struct net_device *dev,
1461                                   struct ethtool_eeprom *ee,
1462                                   u8 *data)
1463{
1464        struct bnx2x *bp = netdev_priv(dev);
1465        int rc = -EINVAL, phy_idx;
1466        u8 *user_data = data;
1467        unsigned int start_addr = ee->offset, xfer_size = 0;
1468
1469        if (!bnx2x_is_nvm_accessible(bp)) {
1470                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1471                   "cannot access eeprom when the interface is down\n");
1472                return -EAGAIN;
1473        }
1474
1475        phy_idx = bnx2x_get_cur_phy_idx(bp);
1476
1477        /* Read A0 section */
1478        if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1479                /* Limit transfer size to the A0 section boundary */
1480                if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1481                        xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1482                else
1483                        xfer_size = ee->len;
1484                bnx2x_acquire_phy_lock(bp);
1485                rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1486                                                  &bp->link_params,
1487                                                  I2C_DEV_ADDR_A0,
1488                                                  start_addr,
1489                                                  xfer_size,
1490                                                  user_data);
1491                bnx2x_release_phy_lock(bp);
1492                if (rc) {
1493                        DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1494
1495                        return -EINVAL;
1496                }
1497                user_data += xfer_size;
1498                start_addr += xfer_size;
1499        }
1500
1501        /* Read A2 section */
1502        if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1503            (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1504                xfer_size = ee->len - xfer_size;
1505                /* Limit transfer size to the A2 section boundary */
1506                if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1507                        xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1508                start_addr -= ETH_MODULE_SFF_8079_LEN;
1509                bnx2x_acquire_phy_lock(bp);
1510                rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1511                                                  &bp->link_params,
1512                                                  I2C_DEV_ADDR_A2,
1513                                                  start_addr,
1514                                                  xfer_size,
1515                                                  user_data);
1516                bnx2x_release_phy_lock(bp);
1517                if (rc) {
1518                        DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1519                        return -EINVAL;
1520                }
1521        }
1522        return rc;
1523}
1524
1525static int bnx2x_get_module_info(struct net_device *dev,
1526                                 struct ethtool_modinfo *modinfo)
1527{
1528        struct bnx2x *bp = netdev_priv(dev);
1529        int phy_idx, rc;
1530        u8 sff8472_comp, diag_type;
1531
1532        if (!bnx2x_is_nvm_accessible(bp)) {
1533                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1534                   "cannot access eeprom when the interface is down\n");
1535                return -EAGAIN;
1536        }
1537        phy_idx = bnx2x_get_cur_phy_idx(bp);
1538        bnx2x_acquire_phy_lock(bp);
1539        rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1540                                          &bp->link_params,
1541                                          I2C_DEV_ADDR_A0,
1542                                          SFP_EEPROM_SFF_8472_COMP_ADDR,
1543                                          SFP_EEPROM_SFF_8472_COMP_SIZE,
1544                                          &sff8472_comp);
1545        bnx2x_release_phy_lock(bp);
1546        if (rc) {
1547                DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1548                return -EINVAL;
1549        }
1550
1551        bnx2x_acquire_phy_lock(bp);
1552        rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1553                                          &bp->link_params,
1554                                          I2C_DEV_ADDR_A0,
1555                                          SFP_EEPROM_DIAG_TYPE_ADDR,
1556                                          SFP_EEPROM_DIAG_TYPE_SIZE,
1557                                          &diag_type);
1558        bnx2x_release_phy_lock(bp);
1559        if (rc) {
1560                DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1561                return -EINVAL;
1562        }
1563
1564        if (!sff8472_comp ||
1565            (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
1566                modinfo->type = ETH_MODULE_SFF_8079;
1567                modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1568        } else {
1569                modinfo->type = ETH_MODULE_SFF_8472;
1570                modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1571        }
1572        return 0;
1573}
1574
1575static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1576                                   u32 cmd_flags)
1577{
1578        int count, i, rc;
1579
1580        /* build the command word */
1581        cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1582
1583        /* need to clear DONE bit separately */
1584        REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1585
1586        /* write the data */
1587        REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1588
1589        /* address of the NVRAM to write to */
1590        REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1591               (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1592
1593        /* issue the write command */
1594        REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1595
1596        /* adjust timeout for emulation/FPGA */
1597        count = BNX2X_NVRAM_TIMEOUT_COUNT;
1598        if (CHIP_REV_IS_SLOW(bp))
1599                count *= 100;
1600
1601        /* wait for completion */
1602        rc = -EBUSY;
1603        for (i = 0; i < count; i++) {
1604                udelay(5);
1605                val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1606                if (val & MCPR_NVM_COMMAND_DONE) {
1607                        rc = 0;
1608                        break;
1609                }
1610        }
1611
1612        if (rc == -EBUSY)
1613                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1614                   "nvram write timeout expired\n");
1615        return rc;
1616}
1617
1618#define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1619
1620static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1621                              int buf_size)
1622{
1623        int rc;
1624        u32 cmd_flags, align_offset, val;
1625        __be32 val_be;
1626
1627        if (offset + buf_size > bp->common.flash_size) {
1628                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1629                   "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1630                   offset, buf_size, bp->common.flash_size);
1631                return -EINVAL;
1632        }
1633
1634        /* request access to nvram interface */
1635        rc = bnx2x_acquire_nvram_lock(bp);
1636        if (rc)
1637                return rc;
1638
1639        /* enable access to nvram interface */
1640        bnx2x_enable_nvram_access(bp);
1641
1642        cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1643        align_offset = (offset & ~0x03);
1644        rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1645
1646        if (rc == 0) {
1647                /* nvram data is returned as an array of bytes
1648                 * convert it back to cpu order
1649                 */
1650                val = be32_to_cpu(val_be);
1651
1652                val &= ~le32_to_cpu((__force __le32)
1653                                    (0xff << BYTE_OFFSET(offset)));
1654                val |= le32_to_cpu((__force __le32)
1655                                   (*data_buf << BYTE_OFFSET(offset)));
1656
1657                rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1658                                             cmd_flags);
1659        }
1660
1661        /* disable access to nvram interface */
1662        bnx2x_disable_nvram_access(bp);
1663        bnx2x_release_nvram_lock(bp);
1664
1665        return rc;
1666}
1667
1668static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1669                             int buf_size)
1670{
1671        int rc;
1672        u32 cmd_flags;
1673        u32 val;
1674        u32 written_so_far;
1675
1676        if (buf_size == 1)      /* ethtool */
1677                return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1678
1679        if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1680                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1681                   "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1682                   offset, buf_size);
1683                return -EINVAL;
1684        }
1685
1686        if (offset + buf_size > bp->common.flash_size) {
1687                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1688                   "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1689                   offset, buf_size, bp->common.flash_size);
1690                return -EINVAL;
1691        }
1692
1693        /* request access to nvram interface */
1694        rc = bnx2x_acquire_nvram_lock(bp);
1695        if (rc)
1696                return rc;
1697
1698        /* enable access to nvram interface */
1699        bnx2x_enable_nvram_access(bp);
1700
1701        written_so_far = 0;
1702        cmd_flags = MCPR_NVM_COMMAND_FIRST;
1703        while ((written_so_far < buf_size) && (rc == 0)) {
1704                if (written_so_far == (buf_size - sizeof(u32)))
1705                        cmd_flags |= MCPR_NVM_COMMAND_LAST;
1706                else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1707                        cmd_flags |= MCPR_NVM_COMMAND_LAST;
1708                else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1709                        cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1710
1711                memcpy(&val, data_buf, 4);
1712
1713                /* Notice unlike bnx2x_nvram_read_dword() this will not
1714                 * change val using be32_to_cpu(), which causes data to flip
1715                 * if the eeprom is read and then written back. This is due
1716                 * to tools utilizing this functionality that would break
1717                 * if this would be resolved.
1718                 */
1719                rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1720
1721                /* advance to the next dword */
1722                offset += sizeof(u32);
1723                data_buf += sizeof(u32);
1724                written_so_far += sizeof(u32);
1725
1726                /* At end of each 4Kb page, release nvram lock to allow MFW
1727                 * chance to take it for its own use.
1728                 */
1729                if ((cmd_flags & MCPR_NVM_COMMAND_LAST) &&
1730                    (written_so_far < buf_size)) {
1731                        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1732                           "Releasing NVM lock after offset 0x%x\n",
1733                           (u32)(offset - sizeof(u32)));
1734                        bnx2x_release_nvram_lock(bp);
1735                        usleep_range(1000, 2000);
1736                        rc = bnx2x_acquire_nvram_lock(bp);
1737                        if (rc)
1738                                return rc;
1739                }
1740
1741                cmd_flags = 0;
1742        }
1743
1744        /* disable access to nvram interface */
1745        bnx2x_disable_nvram_access(bp);
1746        bnx2x_release_nvram_lock(bp);
1747
1748        return rc;
1749}
1750
1751static int bnx2x_set_eeprom(struct net_device *dev,
1752                            struct ethtool_eeprom *eeprom, u8 *eebuf)
1753{
1754        struct bnx2x *bp = netdev_priv(dev);
1755        int port = BP_PORT(bp);
1756        int rc = 0;
1757        u32 ext_phy_config;
1758
1759        if (!bnx2x_is_nvm_accessible(bp)) {
1760                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1761                   "cannot access eeprom when the interface is down\n");
1762                return -EAGAIN;
1763        }
1764
1765        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1766           "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1767           eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1768           eeprom->len, eeprom->len);
1769
1770        /* parameters already validated in ethtool_set_eeprom */
1771
1772        /* PHY eeprom can be accessed only by the PMF */
1773        if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1774            !bp->port.pmf) {
1775                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1776                   "wrong magic or interface is not pmf\n");
1777                return -EINVAL;
1778        }
1779
1780        ext_phy_config =
1781                SHMEM_RD(bp,
1782                         dev_info.port_hw_config[port].external_phy_config);
1783
1784        if (eeprom->magic == 0x50485950) {
1785                /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1786                bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1787
1788                bnx2x_acquire_phy_lock(bp);
1789                rc |= bnx2x_link_reset(&bp->link_params,
1790                                       &bp->link_vars, 0);
1791                if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1792                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1793                        bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1794                                       MISC_REGISTERS_GPIO_HIGH, port);
1795                bnx2x_release_phy_lock(bp);
1796                bnx2x_link_report(bp);
1797
1798        } else if (eeprom->magic == 0x50485952) {
1799                /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1800                if (bp->state == BNX2X_STATE_OPEN) {
1801                        bnx2x_acquire_phy_lock(bp);
1802                        rc |= bnx2x_link_reset(&bp->link_params,
1803                                               &bp->link_vars, 1);
1804
1805                        rc |= bnx2x_phy_init(&bp->link_params,
1806                                             &bp->link_vars);
1807                        bnx2x_release_phy_lock(bp);
1808                        bnx2x_calc_fc_adv(bp);
1809                }
1810        } else if (eeprom->magic == 0x53985943) {
1811                /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1812                if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1813                                       PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1814
1815                        /* DSP Remove Download Mode */
1816                        bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1817                                       MISC_REGISTERS_GPIO_LOW, port);
1818
1819                        bnx2x_acquire_phy_lock(bp);
1820
1821                        bnx2x_sfx7101_sp_sw_reset(bp,
1822                                                &bp->link_params.phy[EXT_PHY1]);
1823
1824                        /* wait 0.5 sec to allow it to run */
1825                        msleep(500);
1826                        bnx2x_ext_phy_hw_reset(bp, port);
1827                        msleep(500);
1828                        bnx2x_release_phy_lock(bp);
1829                }
1830        } else
1831                rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1832
1833        return rc;
1834}
1835
1836static int bnx2x_get_coalesce(struct net_device *dev,
1837                              struct ethtool_coalesce *coal)
1838{
1839        struct bnx2x *bp = netdev_priv(dev);
1840
1841        memset(coal, 0, sizeof(struct ethtool_coalesce));
1842
1843        coal->rx_coalesce_usecs = bp->rx_ticks;
1844        coal->tx_coalesce_usecs = bp->tx_ticks;
1845
1846        return 0;
1847}
1848
1849static int bnx2x_set_coalesce(struct net_device *dev,
1850                              struct ethtool_coalesce *coal)
1851{
1852        struct bnx2x *bp = netdev_priv(dev);
1853
1854        bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1855        if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1856                bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1857
1858        bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1859        if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1860                bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1861
1862        if (netif_running(dev))
1863                bnx2x_update_coalesce(bp);
1864
1865        return 0;
1866}
1867
1868static void bnx2x_get_ringparam(struct net_device *dev,
1869                                struct ethtool_ringparam *ering)
1870{
1871        struct bnx2x *bp = netdev_priv(dev);
1872
1873        ering->rx_max_pending = MAX_RX_AVAIL;
1874
1875        /* If size isn't already set, we give an estimation of the number
1876         * of buffers we'll have. We're neglecting some possible conditions
1877         * [we couldn't know for certain at this point if number of queues
1878         * might shrink] but the number would be correct for the likely
1879         * scenario.
1880         */
1881        if (bp->rx_ring_size)
1882                ering->rx_pending = bp->rx_ring_size;
1883        else if (BNX2X_NUM_RX_QUEUES(bp))
1884                ering->rx_pending = MAX_RX_AVAIL / BNX2X_NUM_RX_QUEUES(bp);
1885        else
1886                ering->rx_pending = MAX_RX_AVAIL;
1887
1888        ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1889        ering->tx_pending = bp->tx_ring_size;
1890}
1891
1892static int bnx2x_set_ringparam(struct net_device *dev,
1893                               struct ethtool_ringparam *ering)
1894{
1895        struct bnx2x *bp = netdev_priv(dev);
1896
1897        DP(BNX2X_MSG_ETHTOOL,
1898           "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1899           ering->rx_pending, ering->tx_pending);
1900
1901        if (pci_num_vf(bp->pdev)) {
1902                DP(BNX2X_MSG_IOV,
1903                   "VFs are enabled, can not change ring parameters\n");
1904                return -EPERM;
1905        }
1906
1907        if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1908                DP(BNX2X_MSG_ETHTOOL,
1909                   "Handling parity error recovery. Try again later\n");
1910                return -EAGAIN;
1911        }
1912
1913        if ((ering->rx_pending > MAX_RX_AVAIL) ||
1914            (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1915                                                    MIN_RX_SIZE_TPA)) ||
1916            (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
1917            (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1918                DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1919                return -EINVAL;
1920        }
1921
1922        bp->rx_ring_size = ering->rx_pending;
1923        bp->tx_ring_size = ering->tx_pending;
1924
1925        return bnx2x_reload_if_running(dev);
1926}
1927
1928static void bnx2x_get_pauseparam(struct net_device *dev,
1929                                 struct ethtool_pauseparam *epause)
1930{
1931        struct bnx2x *bp = netdev_priv(dev);
1932        int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1933        int cfg_reg;
1934
1935        epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1936                           BNX2X_FLOW_CTRL_AUTO);
1937
1938        if (!epause->autoneg)
1939                cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1940        else
1941                cfg_reg = bp->link_params.req_fc_auto_adv;
1942
1943        epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1944                            BNX2X_FLOW_CTRL_RX);
1945        epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1946                            BNX2X_FLOW_CTRL_TX);
1947
1948        DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1949           "  autoneg %d  rx_pause %d  tx_pause %d\n",
1950           epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1951}
1952
1953static int bnx2x_set_pauseparam(struct net_device *dev,
1954                                struct ethtool_pauseparam *epause)
1955{
1956        struct bnx2x *bp = netdev_priv(dev);
1957        u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1958        if (IS_MF(bp))
1959                return 0;
1960
1961        DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1962           "  autoneg %d  rx_pause %d  tx_pause %d\n",
1963           epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1964
1965        bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1966
1967        if (epause->rx_pause)
1968                bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1969
1970        if (epause->tx_pause)
1971                bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1972
1973        if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1974                bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1975
1976        if (epause->autoneg) {
1977                if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1978                        DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1979                        return -EINVAL;
1980                }
1981
1982                if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1983                        bp->link_params.req_flow_ctrl[cfg_idx] =
1984                                BNX2X_FLOW_CTRL_AUTO;
1985                }
1986                bp->link_params.req_fc_auto_adv = 0;
1987                if (epause->rx_pause)
1988                        bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1989
1990                if (epause->tx_pause)
1991                        bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1992
1993                if (!bp->link_params.req_fc_auto_adv)
1994                        bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
1995        }
1996
1997        DP(BNX2X_MSG_ETHTOOL,
1998           "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1999
2000        if (netif_running(dev)) {
2001                bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2002                bnx2x_force_link_reset(bp);
2003                bnx2x_link_set(bp);
2004        }
2005
2006        return 0;
2007}
2008
2009static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
2010        "register_test (offline)    ",
2011        "memory_test (offline)      ",
2012        "int_loopback_test (offline)",
2013        "ext_loopback_test (offline)",
2014        "nvram_test (online)        ",
2015        "interrupt_test (online)    ",
2016        "link_test (online)         "
2017};
2018
2019enum {
2020        BNX2X_PRI_FLAG_ISCSI,
2021        BNX2X_PRI_FLAG_FCOE,
2022        BNX2X_PRI_FLAG_STORAGE,
2023        BNX2X_PRI_FLAG_LEN,
2024};
2025
2026static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
2027        "iSCSI offload support",
2028        "FCoE offload support",
2029        "Storage only interface"
2030};
2031
2032static u32 bnx2x_eee_to_adv(u32 eee_adv)
2033{
2034        u32 modes = 0;
2035
2036        if (eee_adv & SHMEM_EEE_100M_ADV)
2037                modes |= ADVERTISED_100baseT_Full;
2038        if (eee_adv & SHMEM_EEE_1G_ADV)
2039                modes |= ADVERTISED_1000baseT_Full;
2040        if (eee_adv & SHMEM_EEE_10G_ADV)
2041                modes |= ADVERTISED_10000baseT_Full;
2042
2043        return modes;
2044}
2045
2046static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
2047{
2048        u32 eee_adv = 0;
2049        if (modes & ADVERTISED_100baseT_Full)
2050                eee_adv |= SHMEM_EEE_100M_ADV;
2051        if (modes & ADVERTISED_1000baseT_Full)
2052                eee_adv |= SHMEM_EEE_1G_ADV;
2053        if (modes & ADVERTISED_10000baseT_Full)
2054                eee_adv |= SHMEM_EEE_10G_ADV;
2055
2056        return eee_adv << shift;
2057}
2058
2059static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2060{
2061        struct bnx2x *bp = netdev_priv(dev);
2062        u32 eee_cfg;
2063
2064        if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2065                DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2066                return -EOPNOTSUPP;
2067        }
2068
2069        eee_cfg = bp->link_vars.eee_status;
2070
2071        edata->supported =
2072                bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2073                                 SHMEM_EEE_SUPPORTED_SHIFT);
2074
2075        edata->advertised =
2076                bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2077                                 SHMEM_EEE_ADV_STATUS_SHIFT);
2078        edata->lp_advertised =
2079                bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2080                                 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2081
2082        /* SHMEM value is in 16u units --> Convert to 1u units. */
2083        edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2084
2085        edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)     ? 1 : 0;
2086        edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)        ? 1 : 0;
2087        edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2088
2089        return 0;
2090}
2091
2092static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2093{
2094        struct bnx2x *bp = netdev_priv(dev);
2095        u32 eee_cfg;
2096        u32 advertised;
2097
2098        if (IS_MF(bp))
2099                return 0;
2100
2101        if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2102                DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2103                return -EOPNOTSUPP;
2104        }
2105
2106        eee_cfg = bp->link_vars.eee_status;
2107
2108        if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2109                DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2110                return -EOPNOTSUPP;
2111        }
2112
2113        advertised = bnx2x_adv_to_eee(edata->advertised,
2114                                      SHMEM_EEE_ADV_STATUS_SHIFT);
2115        if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2116                DP(BNX2X_MSG_ETHTOOL,
2117                   "Direct manipulation of EEE advertisement is not supported\n");
2118                return -EINVAL;
2119        }
2120
2121        if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2122                DP(BNX2X_MSG_ETHTOOL,
2123                   "Maximal Tx Lpi timer supported is %x(u)\n",
2124                   EEE_MODE_TIMER_MASK);
2125                return -EINVAL;
2126        }
2127        if (edata->tx_lpi_enabled &&
2128            (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2129                DP(BNX2X_MSG_ETHTOOL,
2130                   "Minimal Tx Lpi timer supported is %d(u)\n",
2131                   EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2132                return -EINVAL;
2133        }
2134
2135        /* All is well; Apply changes*/
2136        if (edata->eee_enabled)
2137                bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2138        else
2139                bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2140
2141        if (edata->tx_lpi_enabled)
2142                bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2143        else
2144                bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2145
2146        bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2147        bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2148                                    EEE_MODE_TIMER_MASK) |
2149                                    EEE_MODE_OVERRIDE_NVRAM |
2150                                    EEE_MODE_OUTPUT_TIME;
2151
2152        /* Restart link to propagate changes */
2153        if (netif_running(dev)) {
2154                bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2155                bnx2x_force_link_reset(bp);
2156                bnx2x_link_set(bp);
2157        }
2158
2159        return 0;
2160}
2161
2162enum {
2163        BNX2X_CHIP_E1_OFST = 0,
2164        BNX2X_CHIP_E1H_OFST,
2165        BNX2X_CHIP_E2_OFST,
2166        BNX2X_CHIP_E3_OFST,
2167        BNX2X_CHIP_E3B0_OFST,
2168        BNX2X_CHIP_MAX_OFST
2169};
2170
2171#define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
2172#define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
2173#define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
2174#define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
2175#define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
2176
2177#define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2178#define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2179
2180static int bnx2x_test_registers(struct bnx2x *bp)
2181{
2182        int idx, i, rc = -ENODEV;
2183        u32 wr_val = 0, hw;
2184        int port = BP_PORT(bp);
2185        static const struct {
2186                u32 hw;
2187                u32 offset0;
2188                u32 offset1;
2189                u32 mask;
2190        } reg_tbl[] = {
2191/* 0 */         { BNX2X_CHIP_MASK_ALL,
2192                        BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2193                { BNX2X_CHIP_MASK_ALL,
2194                        DORQ_REG_DB_ADDR0,              4, 0xffffffff },
2195                { BNX2X_CHIP_MASK_E1X,
2196                        HC_REG_AGG_INT_0,               4, 0x000003ff },
2197                { BNX2X_CHIP_MASK_ALL,
2198                        PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
2199                { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2200                        PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
2201                { BNX2X_CHIP_MASK_E3B0,
2202                        PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
2203                { BNX2X_CHIP_MASK_ALL,
2204                        PRS_REG_CID_PORT_0,             4, 0x00ffffff },
2205                { BNX2X_CHIP_MASK_ALL,
2206                        PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
2207                { BNX2X_CHIP_MASK_ALL,
2208                        PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2209                { BNX2X_CHIP_MASK_ALL,
2210                        PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
2211/* 10 */        { BNX2X_CHIP_MASK_ALL,
2212                        PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2213                { BNX2X_CHIP_MASK_ALL,
2214                        PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
2215                { BNX2X_CHIP_MASK_ALL,
2216                        QM_REG_CONNNUM_0,               4, 0x000fffff },
2217                { BNX2X_CHIP_MASK_ALL,
2218                        TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
2219                { BNX2X_CHIP_MASK_ALL,
2220                        SRC_REG_KEYRSS0_0,              40, 0xffffffff },
2221                { BNX2X_CHIP_MASK_ALL,
2222                        SRC_REG_KEYRSS0_7,              40, 0xffffffff },
2223                { BNX2X_CHIP_MASK_ALL,
2224                        XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2225                { BNX2X_CHIP_MASK_ALL,
2226                        XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
2227                { BNX2X_CHIP_MASK_ALL,
2228                        XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
2229                { BNX2X_CHIP_MASK_ALL,
2230                        NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
2231/* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2232                        NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
2233                { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2234                        NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
2235                { BNX2X_CHIP_MASK_ALL,
2236                        NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
2237                { BNX2X_CHIP_MASK_ALL,
2238                        NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
2239                { BNX2X_CHIP_MASK_ALL,
2240                        NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
2241                { BNX2X_CHIP_MASK_ALL,
2242                        NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
2243                { BNX2X_CHIP_MASK_ALL,
2244                        NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
2245                { BNX2X_CHIP_MASK_ALL,
2246                        NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
2247                { BNX2X_CHIP_MASK_ALL,
2248                        NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
2249                { BNX2X_CHIP_MASK_ALL,
2250                        NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
2251/* 30 */        { BNX2X_CHIP_MASK_ALL,
2252                        NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
2253                { BNX2X_CHIP_MASK_ALL,
2254                        NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
2255                { BNX2X_CHIP_MASK_ALL,
2256                        NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2257                { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2258                        NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
2259                { BNX2X_CHIP_MASK_ALL,
2260                        NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2261                { BNX2X_CHIP_MASK_ALL,
2262                        NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2263                { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2264                        NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2265                { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2266                        NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
2267
2268                { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2269        };
2270
2271        if (!bnx2x_is_nvm_accessible(bp)) {
2272                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2273                   "cannot access eeprom when the interface is down\n");
2274                return rc;
2275        }
2276
2277        if (CHIP_IS_E1(bp))
2278                hw = BNX2X_CHIP_MASK_E1;
2279        else if (CHIP_IS_E1H(bp))
2280                hw = BNX2X_CHIP_MASK_E1H;
2281        else if (CHIP_IS_E2(bp))
2282                hw = BNX2X_CHIP_MASK_E2;
2283        else if (CHIP_IS_E3B0(bp))
2284                hw = BNX2X_CHIP_MASK_E3B0;
2285        else /* e3 A0 */
2286                hw = BNX2X_CHIP_MASK_E3;
2287
2288        /* Repeat the test twice:
2289         * First by writing 0x00000000, second by writing 0xffffffff
2290         */
2291        for (idx = 0; idx < 2; idx++) {
2292
2293                switch (idx) {
2294                case 0:
2295                        wr_val = 0;
2296                        break;
2297                case 1:
2298                        wr_val = 0xffffffff;
2299                        break;
2300                }
2301
2302                for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2303                        u32 offset, mask, save_val, val;
2304                        if (!(hw & reg_tbl[i].hw))
2305                                continue;
2306
2307                        offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2308                        mask = reg_tbl[i].mask;
2309
2310                        save_val = REG_RD(bp, offset);
2311
2312                        REG_WR(bp, offset, wr_val & mask);
2313
2314                        val = REG_RD(bp, offset);
2315
2316                        /* Restore the original register's value */
2317                        REG_WR(bp, offset, save_val);
2318
2319                        /* verify value is as expected */
2320                        if ((val & mask) != (wr_val & mask)) {
2321                                DP(BNX2X_MSG_ETHTOOL,
2322                                   "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2323                                   offset, val, wr_val, mask);
2324                                goto test_reg_exit;
2325                        }
2326                }
2327        }
2328
2329        rc = 0;
2330
2331test_reg_exit:
2332        return rc;
2333}
2334
2335static int bnx2x_test_memory(struct bnx2x *bp)
2336{
2337        int i, j, rc = -ENODEV;
2338        u32 val, index;
2339        static const struct {
2340                u32 offset;
2341                int size;
2342        } mem_tbl[] = {
2343                { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
2344                { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2345                { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
2346                { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
2347                { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
2348                { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
2349                { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
2350
2351                { 0xffffffff, 0 }
2352        };
2353
2354        static const struct {
2355                char *name;
2356                u32 offset;
2357                u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2358        } prty_tbl[] = {
2359                { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
2360                        {0x3ffc0, 0,   0, 0} },
2361                { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
2362                        {0x2,     0x2, 0, 0} },
2363                { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2364                        {0,       0,   0, 0} },
2365                { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
2366                        {0x3ffc0, 0,   0, 0} },
2367                { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
2368                        {0x3ffc0, 0,   0, 0} },
2369                { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
2370                        {0x3ffc1, 0,   0, 0} },
2371
2372                { NULL, 0xffffffff, {0, 0, 0, 0} }
2373        };
2374
2375        if (!bnx2x_is_nvm_accessible(bp)) {
2376                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2377                   "cannot access eeprom when the interface is down\n");
2378                return rc;
2379        }
2380
2381        if (CHIP_IS_E1(bp))
2382                index = BNX2X_CHIP_E1_OFST;
2383        else if (CHIP_IS_E1H(bp))
2384                index = BNX2X_CHIP_E1H_OFST;
2385        else if (CHIP_IS_E2(bp))
2386                index = BNX2X_CHIP_E2_OFST;
2387        else /* e3 */
2388                index = BNX2X_CHIP_E3_OFST;
2389
2390        /* pre-Check the parity status */
2391        for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2392                val = REG_RD(bp, prty_tbl[i].offset);
2393                if (val & ~(prty_tbl[i].hw_mask[index])) {
2394                        DP(BNX2X_MSG_ETHTOOL,
2395                           "%s is 0x%x\n", prty_tbl[i].name, val);
2396                        goto test_mem_exit;
2397                }
2398        }
2399
2400        /* Go through all the memories */
2401        for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2402                for (j = 0; j < mem_tbl[i].size; j++)
2403                        REG_RD(bp, mem_tbl[i].offset + j*4);
2404
2405        /* Check the parity status */
2406        for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2407                val = REG_RD(bp, prty_tbl[i].offset);
2408                if (val & ~(prty_tbl[i].hw_mask[index])) {
2409                        DP(BNX2X_MSG_ETHTOOL,
2410                           "%s is 0x%x\n", prty_tbl[i].name, val);
2411                        goto test_mem_exit;
2412                }
2413        }
2414
2415        rc = 0;
2416
2417test_mem_exit:
2418        return rc;
2419}
2420
2421static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2422{
2423        int cnt = 1400;
2424
2425        if (link_up) {
2426                while (bnx2x_link_test(bp, is_serdes) && cnt--)
2427                        msleep(20);
2428
2429                if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2430                        DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2431
2432                cnt = 1400;
2433                while (!bp->link_vars.link_up && cnt--)
2434                        msleep(20);
2435
2436                if (cnt <= 0 && !bp->link_vars.link_up)
2437                        DP(BNX2X_MSG_ETHTOOL,
2438                           "Timeout waiting for link init\n");
2439        }
2440}
2441
2442static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2443{
2444        unsigned int pkt_size, num_pkts, i;
2445        struct sk_buff *skb;
2446        unsigned char *packet;
2447        struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2448        struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2449        struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2450        u16 tx_start_idx, tx_idx;
2451        u16 rx_start_idx, rx_idx;
2452        u16 pkt_prod, bd_prod;
2453        struct sw_tx_bd *tx_buf;
2454        struct eth_tx_start_bd *tx_start_bd;
2455        dma_addr_t mapping;
2456        union eth_rx_cqe *cqe;
2457        u8 cqe_fp_flags, cqe_fp_type;
2458        struct sw_rx_bd *rx_buf;
2459        u16 len;
2460        int rc = -ENODEV;
2461        u8 *data;
2462        struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2463                                                       txdata->txq_index);
2464
2465        /* check the loopback mode */
2466        switch (loopback_mode) {
2467        case BNX2X_PHY_LOOPBACK:
2468                if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2469                        DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2470                        return -EINVAL;
2471                }
2472                break;
2473        case BNX2X_MAC_LOOPBACK:
2474                if (CHIP_IS_E3(bp)) {
2475                        int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2476                        if (bp->port.supported[cfg_idx] &
2477                            (SUPPORTED_10000baseT_Full |
2478                             SUPPORTED_20000baseMLD2_Full |
2479                             SUPPORTED_20000baseKR2_Full))
2480                                bp->link_params.loopback_mode = LOOPBACK_XMAC;
2481                        else
2482                                bp->link_params.loopback_mode = LOOPBACK_UMAC;
2483                } else
2484                        bp->link_params.loopback_mode = LOOPBACK_BMAC;
2485
2486                bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2487                break;
2488        case BNX2X_EXT_LOOPBACK:
2489                if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2490                        DP(BNX2X_MSG_ETHTOOL,
2491                           "Can't configure external loopback\n");
2492                        return -EINVAL;
2493                }
2494                break;
2495        default:
2496                DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2497                return -EINVAL;
2498        }
2499
2500        /* prepare the loopback packet */
2501        pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2502                     bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2503        skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2504        if (!skb) {
2505                DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2506                rc = -ENOMEM;
2507                goto test_loopback_exit;
2508        }
2509        packet = skb_put(skb, pkt_size);
2510        memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2511        eth_zero_addr(packet + ETH_ALEN);
2512        memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2513        for (i = ETH_HLEN; i < pkt_size; i++)
2514                packet[i] = (unsigned char) (i & 0xff);
2515        mapping = dma_map_single(&bp->pdev->dev, skb->data,
2516                                 skb_headlen(skb), DMA_TO_DEVICE);
2517        if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2518                rc = -ENOMEM;
2519                dev_kfree_skb(skb);
2520                DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2521                goto test_loopback_exit;
2522        }
2523
2524        /* send the loopback packet */
2525        num_pkts = 0;
2526        tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2527        rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2528
2529        netdev_tx_sent_queue(txq, skb->len);
2530
2531        pkt_prod = txdata->tx_pkt_prod++;
2532        tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2533        tx_buf->first_bd = txdata->tx_bd_prod;
2534        tx_buf->skb = skb;
2535        tx_buf->flags = 0;
2536
2537        bd_prod = TX_BD(txdata->tx_bd_prod);
2538        tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2539        tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2540        tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2541        tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2542        tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2543        tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2544        tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2545        SET_FLAG(tx_start_bd->general_data,
2546                 ETH_TX_START_BD_HDR_NBDS,
2547                 1);
2548        SET_FLAG(tx_start_bd->general_data,
2549                 ETH_TX_START_BD_PARSE_NBDS,
2550                 0);
2551
2552        /* turn on parsing and get a BD */
2553        bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2554
2555        if (CHIP_IS_E1x(bp)) {
2556                u16 global_data = 0;
2557                struct eth_tx_parse_bd_e1x  *pbd_e1x =
2558                        &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2559                memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2560                SET_FLAG(global_data,
2561                         ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2562                pbd_e1x->global_data = cpu_to_le16(global_data);
2563        } else {
2564                u32 parsing_data = 0;
2565                struct eth_tx_parse_bd_e2  *pbd_e2 =
2566                        &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2567                memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2568                SET_FLAG(parsing_data,
2569                         ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2570                pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2571        }
2572        wmb();
2573
2574        txdata->tx_db.data.prod += 2;
2575        barrier();
2576        DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2577
2578        mmiowb();
2579        barrier();
2580
2581        num_pkts++;
2582        txdata->tx_bd_prod += 2; /* start + pbd */
2583
2584        udelay(100);
2585
2586        tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2587        if (tx_idx != tx_start_idx + num_pkts)
2588                goto test_loopback_exit;
2589
2590        /* Unlike HC IGU won't generate an interrupt for status block
2591         * updates that have been performed while interrupts were
2592         * disabled.
2593         */
2594        if (bp->common.int_block == INT_BLOCK_IGU) {
2595                /* Disable local BHes to prevent a dead-lock situation between
2596                 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2597                 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2598                 */
2599                local_bh_disable();
2600                bnx2x_tx_int(bp, txdata);
2601                local_bh_enable();
2602        }
2603
2604        rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2605        if (rx_idx != rx_start_idx + num_pkts)
2606                goto test_loopback_exit;
2607
2608        cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2609        cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2610        cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2611        if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2612                goto test_loopback_rx_exit;
2613
2614        len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2615        if (len != pkt_size)
2616                goto test_loopback_rx_exit;
2617
2618        rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2619        dma_sync_single_for_cpu(&bp->pdev->dev,
2620                                   dma_unmap_addr(rx_buf, mapping),
2621                                   fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2622        data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2623        for (i = ETH_HLEN; i < pkt_size; i++)
2624                if (*(data + i) != (unsigned char) (i & 0xff))
2625                        goto test_loopback_rx_exit;
2626
2627        rc = 0;
2628
2629test_loopback_rx_exit:
2630
2631        fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2632        fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2633        fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2634        fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2635
2636        /* Update producers */
2637        bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2638                             fp_rx->rx_sge_prod);
2639
2640test_loopback_exit:
2641        bp->link_params.loopback_mode = LOOPBACK_NONE;
2642
2643        return rc;
2644}
2645
2646static int bnx2x_test_loopback(struct bnx2x *bp)
2647{
2648        int rc = 0, res;
2649
2650        if (BP_NOMCP(bp))
2651                return rc;
2652
2653        if (!netif_running(bp->dev))
2654                return BNX2X_LOOPBACK_FAILED;
2655
2656        bnx2x_netif_stop(bp, 1);
2657        bnx2x_acquire_phy_lock(bp);
2658
2659        res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2660        if (res) {
2661                DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2662                rc |= BNX2X_PHY_LOOPBACK_FAILED;
2663        }
2664
2665        res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2666        if (res) {
2667                DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2668                rc |= BNX2X_MAC_LOOPBACK_FAILED;
2669        }
2670
2671        bnx2x_release_phy_lock(bp);
2672        bnx2x_netif_start(bp);
2673
2674        return rc;
2675}
2676
2677static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2678{
2679        int rc;
2680        u8 is_serdes =
2681                (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2682
2683        if (BP_NOMCP(bp))
2684                return -ENODEV;
2685
2686        if (!netif_running(bp->dev))
2687                return BNX2X_EXT_LOOPBACK_FAILED;
2688
2689        bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2690        rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2691        if (rc) {
2692                DP(BNX2X_MSG_ETHTOOL,
2693                   "Can't perform self-test, nic_load (for external lb) failed\n");
2694                return -ENODEV;
2695        }
2696        bnx2x_wait_for_link(bp, 1, is_serdes);
2697
2698        bnx2x_netif_stop(bp, 1);
2699
2700        rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2701        if (rc)
2702                DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2703
2704        bnx2x_netif_start(bp);
2705
2706        return rc;
2707}
2708
2709struct code_entry {
2710        u32 sram_start_addr;
2711        u32 code_attribute;
2712#define CODE_IMAGE_TYPE_MASK                    0xf0800003
2713#define CODE_IMAGE_VNTAG_PROFILES_DATA          0xd0000003
2714#define CODE_IMAGE_LENGTH_MASK                  0x007ffffc
2715#define CODE_IMAGE_TYPE_EXTENDED_DIR            0xe0000000
2716        u32 nvm_start_addr;
2717};
2718
2719#define CODE_ENTRY_MAX                  16
2720#define CODE_ENTRY_EXTENDED_DIR_IDX     15
2721#define MAX_IMAGES_IN_EXTENDED_DIR      64
2722#define NVRAM_DIR_OFFSET                0x14
2723
2724#define EXTENDED_DIR_EXISTS(code)                                         \
2725        ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2726         (code & CODE_IMAGE_LENGTH_MASK) != 0)
2727
2728#define CRC32_RESIDUAL                  0xdebb20e3
2729#define CRC_BUFF_SIZE                   256
2730
2731static int bnx2x_nvram_crc(struct bnx2x *bp,
2732                           int offset,
2733                           int size,
2734                           u8 *buff)
2735{
2736        u32 crc = ~0;
2737        int rc = 0, done = 0;
2738
2739        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2740           "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2741
2742        while (done < size) {
2743                int count = min_t(int, size - done, CRC_BUFF_SIZE);
2744
2745                rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2746
2747                if (rc)
2748                        return rc;
2749
2750                crc = crc32_le(crc, buff, count);
2751                done += count;
2752        }
2753
2754        if (crc != CRC32_RESIDUAL)
2755                rc = -EINVAL;
2756
2757        return rc;
2758}
2759
2760static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2761                                struct code_entry *entry,
2762                                u8 *buff)
2763{
2764        size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2765        u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2766        int rc;
2767
2768        /* Zero-length images and AFEX profiles do not have CRC */
2769        if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2770                return 0;
2771
2772        rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2773        if (rc)
2774                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2775                   "image %x has failed crc test (rc %d)\n", type, rc);
2776
2777        return rc;
2778}
2779
2780static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2781{
2782        int rc;
2783        struct code_entry entry;
2784
2785        rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2786        if (rc)
2787                return rc;
2788
2789        return bnx2x_test_nvram_dir(bp, &entry, buff);
2790}
2791
2792static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2793{
2794        u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2795        struct code_entry entry;
2796        int i;
2797
2798        rc = bnx2x_nvram_read32(bp,
2799                                dir_offset +
2800                                sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2801                                (u32 *)&entry, sizeof(entry));
2802        if (rc)
2803                return rc;
2804
2805        if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2806                return 0;
2807
2808        rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2809                                &cnt, sizeof(u32));
2810        if (rc)
2811                return rc;
2812
2813        dir_offset = entry.nvm_start_addr + 8;
2814
2815        for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2816                rc = bnx2x_test_dir_entry(bp, dir_offset +
2817                                              sizeof(struct code_entry) * i,
2818                                          buff);
2819                if (rc)
2820                        return rc;
2821        }
2822
2823        return 0;
2824}
2825
2826static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2827{
2828        u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2829        int i;
2830
2831        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2832
2833        for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2834                rc = bnx2x_test_dir_entry(bp, dir_offset +
2835                                              sizeof(struct code_entry) * i,
2836                                          buff);
2837                if (rc)
2838                        return rc;
2839        }
2840
2841        return bnx2x_test_nvram_ext_dirs(bp, buff);
2842}
2843
2844struct crc_pair {
2845        int offset;
2846        int size;
2847};
2848
2849static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2850                                const struct crc_pair *nvram_tbl, u8 *buf)
2851{
2852        int i;
2853
2854        for (i = 0; nvram_tbl[i].size; i++) {
2855                int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2856                                         nvram_tbl[i].size, buf);
2857                if (rc) {
2858                        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2859                           "nvram_tbl[%d] has failed crc test (rc %d)\n",
2860                           i, rc);
2861                        return rc;
2862                }
2863        }
2864
2865        return 0;
2866}
2867
2868static int bnx2x_test_nvram(struct bnx2x *bp)
2869{
2870        const struct crc_pair nvram_tbl[] = {
2871                {     0,  0x14 }, /* bootstrap */
2872                {  0x14,  0xec }, /* dir */
2873                { 0x100, 0x350 }, /* manuf_info */
2874                { 0x450,  0xf0 }, /* feature_info */
2875                { 0x640,  0x64 }, /* upgrade_key_info */
2876                { 0x708,  0x70 }, /* manuf_key_info */
2877                {     0,     0 }
2878        };
2879        const struct crc_pair nvram_tbl2[] = {
2880                { 0x7e8, 0x350 }, /* manuf_info2 */
2881                { 0xb38,  0xf0 }, /* feature_info */
2882                {     0,     0 }
2883        };
2884
2885        u8 *buf;
2886        int rc;
2887        u32 magic;
2888
2889        if (BP_NOMCP(bp))
2890                return 0;
2891
2892        buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2893        if (!buf) {
2894                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2895                rc = -ENOMEM;
2896                goto test_nvram_exit;
2897        }
2898
2899        rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2900        if (rc) {
2901                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2902                   "magic value read (rc %d)\n", rc);
2903                goto test_nvram_exit;
2904        }
2905
2906        if (magic != 0x669955aa) {
2907                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2908                   "wrong magic value (0x%08x)\n", magic);
2909                rc = -ENODEV;
2910                goto test_nvram_exit;
2911        }
2912
2913        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2914        rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2915        if (rc)
2916                goto test_nvram_exit;
2917
2918        if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2919                u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2920                           SHARED_HW_CFG_HIDE_PORT1;
2921
2922                if (!hide) {
2923                        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2924                           "Port 1 CRC test-set\n");
2925                        rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2926                        if (rc)
2927                                goto test_nvram_exit;
2928                }
2929        }
2930
2931        rc = bnx2x_test_nvram_dirs(bp, buf);
2932
2933test_nvram_exit:
2934        kfree(buf);
2935        return rc;
2936}
2937
2938/* Send an EMPTY ramrod on the first queue */
2939static int bnx2x_test_intr(struct bnx2x *bp)
2940{
2941        struct bnx2x_queue_state_params params = {NULL};
2942
2943        if (!netif_running(bp->dev)) {
2944                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2945                   "cannot access eeprom when the interface is down\n");
2946                return -ENODEV;
2947        }
2948
2949        params.q_obj = &bp->sp_objs->q_obj;
2950        params.cmd = BNX2X_Q_CMD_EMPTY;
2951
2952        __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2953
2954        return bnx2x_queue_state_change(bp, &params);
2955}
2956
2957static void bnx2x_self_test(struct net_device *dev,
2958                            struct ethtool_test *etest, u64 *buf)
2959{
2960        struct bnx2x *bp = netdev_priv(dev);
2961        u8 is_serdes, link_up;
2962        int rc, cnt = 0;
2963
2964        if (pci_num_vf(bp->pdev)) {
2965                DP(BNX2X_MSG_IOV,
2966                   "VFs are enabled, can not perform self test\n");
2967                return;
2968        }
2969
2970        if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2971                netdev_err(bp->dev,
2972                           "Handling parity error recovery. Try again later\n");
2973                etest->flags |= ETH_TEST_FL_FAILED;
2974                return;
2975        }
2976
2977        DP(BNX2X_MSG_ETHTOOL,
2978           "Self-test command parameters: offline = %d, external_lb = %d\n",
2979           (etest->flags & ETH_TEST_FL_OFFLINE),
2980           (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2981
2982        memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2983
2984        if (bnx2x_test_nvram(bp) != 0) {
2985                if (!IS_MF(bp))
2986                        buf[4] = 1;
2987                else
2988                        buf[0] = 1;
2989                etest->flags |= ETH_TEST_FL_FAILED;
2990        }
2991
2992        if (!netif_running(dev)) {
2993                DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
2994                return;
2995        }
2996
2997        is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2998        link_up = bp->link_vars.link_up;
2999        /* offline tests are not supported in MF mode */
3000        if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
3001                int port = BP_PORT(bp);
3002                u32 val;
3003
3004                /* save current value of input enable for TX port IF */
3005                val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
3006                /* disable input for TX port IF */
3007                REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
3008
3009                bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3010                rc = bnx2x_nic_load(bp, LOAD_DIAG);
3011                if (rc) {
3012                        etest->flags |= ETH_TEST_FL_FAILED;
3013                        DP(BNX2X_MSG_ETHTOOL,
3014                           "Can't perform self-test, nic_load (for offline) failed\n");
3015                        return;
3016                }
3017
3018                /* wait until link state is restored */
3019                bnx2x_wait_for_link(bp, 1, is_serdes);
3020
3021                if (bnx2x_test_registers(bp) != 0) {
3022                        buf[0] = 1;
3023                        etest->flags |= ETH_TEST_FL_FAILED;
3024                }
3025                if (bnx2x_test_memory(bp) != 0) {
3026                        buf[1] = 1;
3027                        etest->flags |= ETH_TEST_FL_FAILED;
3028                }
3029
3030                buf[2] = bnx2x_test_loopback(bp); /* internal LB */
3031                if (buf[2] != 0)
3032                        etest->flags |= ETH_TEST_FL_FAILED;
3033
3034                if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
3035                        buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
3036                        if (buf[3] != 0)
3037                                etest->flags |= ETH_TEST_FL_FAILED;
3038                        etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3039                }
3040
3041                bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3042
3043                /* restore input for TX port IF */
3044                REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
3045                rc = bnx2x_nic_load(bp, LOAD_NORMAL);
3046                if (rc) {
3047                        etest->flags |= ETH_TEST_FL_FAILED;
3048                        DP(BNX2X_MSG_ETHTOOL,
3049                           "Can't perform self-test, nic_load (for online) failed\n");
3050                        return;
3051                }
3052                /* wait until link state is restored */
3053                bnx2x_wait_for_link(bp, link_up, is_serdes);
3054        }
3055
3056        if (bnx2x_test_intr(bp) != 0) {
3057                if (!IS_MF(bp))
3058                        buf[5] = 1;
3059                else
3060                        buf[1] = 1;
3061                etest->flags |= ETH_TEST_FL_FAILED;
3062        }
3063
3064        if (link_up) {
3065                cnt = 100;
3066                while (bnx2x_link_test(bp, is_serdes) && --cnt)
3067                        msleep(20);
3068        }
3069
3070        if (!cnt) {
3071                if (!IS_MF(bp))
3072                        buf[6] = 1;
3073                else
3074                        buf[2] = 1;
3075                etest->flags |= ETH_TEST_FL_FAILED;
3076        }
3077}
3078
3079#define IS_PORT_STAT(i)         (bnx2x_stats_arr[i].is_port_stat)
3080#define HIDE_PORT_STAT(bp)      IS_VF(bp)
3081
3082/* ethtool statistics are displayed for all regular ethernet queues and the
3083 * fcoe L2 queue if not disabled
3084 */
3085static int bnx2x_num_stat_queues(struct bnx2x *bp)
3086{
3087        return BNX2X_NUM_ETH_QUEUES(bp);
3088}
3089
3090static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3091{
3092        struct bnx2x *bp = netdev_priv(dev);
3093        int i, num_strings = 0;
3094
3095        switch (stringset) {
3096        case ETH_SS_STATS:
3097                if (is_multi(bp)) {
3098                        num_strings = bnx2x_num_stat_queues(bp) *
3099                                      BNX2X_NUM_Q_STATS;
3100                } else
3101                        num_strings = 0;
3102                if (HIDE_PORT_STAT(bp)) {
3103                        for (i = 0; i < BNX2X_NUM_STATS; i++)
3104                                if (!IS_PORT_STAT(i))
3105                                        num_strings++;
3106                } else
3107                        num_strings += BNX2X_NUM_STATS;
3108
3109                return num_strings;
3110
3111        case ETH_SS_TEST:
3112                return BNX2X_NUM_TESTS(bp);
3113
3114        case ETH_SS_PRIV_FLAGS:
3115                return BNX2X_PRI_FLAG_LEN;
3116
3117        default:
3118                return -EINVAL;
3119        }
3120}
3121
3122static u32 bnx2x_get_private_flags(struct net_device *dev)
3123{
3124        struct bnx2x *bp = netdev_priv(dev);
3125        u32 flags = 0;
3126
3127        flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3128        flags |= (!(bp->flags & NO_FCOE_FLAG)  ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3129        flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3130
3131        return flags;
3132}
3133
3134static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3135{
3136        struct bnx2x *bp = netdev_priv(dev);
3137        int i, j, k, start;
3138        char queue_name[MAX_QUEUE_NAME_LEN+1];
3139
3140        switch (stringset) {
3141        case ETH_SS_STATS:
3142                k = 0;
3143                if (is_multi(bp)) {
3144                        for_each_eth_queue(bp, i) {
3145                                memset(queue_name, 0, sizeof(queue_name));
3146                                sprintf(queue_name, "%d", i);
3147                                for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3148                                        snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3149                                                ETH_GSTRING_LEN,
3150                                                bnx2x_q_stats_arr[j].string,
3151                                                queue_name);
3152                                k += BNX2X_NUM_Q_STATS;
3153                        }
3154                }
3155
3156                for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3157                        if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3158                                continue;
3159                        strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3160                                   bnx2x_stats_arr[i].string);
3161                        j++;
3162                }
3163
3164                break;
3165
3166        case ETH_SS_TEST:
3167                /* First 4 tests cannot be done in MF mode */
3168                if (!IS_MF(bp))
3169                        start = 0;
3170                else
3171                        start = 4;
3172                memcpy(buf, bnx2x_tests_str_arr + start,
3173                       ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3174                break;
3175
3176        case ETH_SS_PRIV_FLAGS:
3177                memcpy(buf, bnx2x_private_arr,
3178                       ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3179                break;
3180        }
3181}
3182
3183static void bnx2x_get_ethtool_stats(struct net_device *dev,
3184                                    struct ethtool_stats *stats, u64 *buf)
3185{
3186        struct bnx2x *bp = netdev_priv(dev);
3187        u32 *hw_stats, *offset;
3188        int i, j, k = 0;
3189
3190        if (is_multi(bp)) {
3191                for_each_eth_queue(bp, i) {
3192                        hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3193                        for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3194                                if (bnx2x_q_stats_arr[j].size == 0) {
3195                                        /* skip this counter */
3196                                        buf[k + j] = 0;
3197                                        continue;
3198                                }
3199                                offset = (hw_stats +
3200                                          bnx2x_q_stats_arr[j].offset);
3201                                if (bnx2x_q_stats_arr[j].size == 4) {
3202                                        /* 4-byte counter */
3203                                        buf[k + j] = (u64) *offset;
3204                                        continue;
3205                                }
3206                                /* 8-byte counter */
3207                                buf[k + j] = HILO_U64(*offset, *(offset + 1));
3208                        }
3209                        k += BNX2X_NUM_Q_STATS;
3210                }
3211        }
3212
3213        hw_stats = (u32 *)&bp->eth_stats;
3214        for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3215                if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3216                        continue;
3217                if (bnx2x_stats_arr[i].size == 0) {
3218                        /* skip this counter */
3219                        buf[k + j] = 0;
3220                        j++;
3221                        continue;
3222                }
3223                offset = (hw_stats + bnx2x_stats_arr[i].offset);
3224                if (bnx2x_stats_arr[i].size == 4) {
3225                        /* 4-byte counter */
3226                        buf[k + j] = (u64) *offset;
3227                        j++;
3228                        continue;
3229                }
3230                /* 8-byte counter */
3231                buf[k + j] = HILO_U64(*offset, *(offset + 1));
3232                j++;
3233        }
3234}
3235
3236static int bnx2x_set_phys_id(struct net_device *dev,
3237                             enum ethtool_phys_id_state state)
3238{
3239        struct bnx2x *bp = netdev_priv(dev);
3240
3241        if (!bnx2x_is_nvm_accessible(bp)) {
3242                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3243                   "cannot access eeprom when the interface is down\n");
3244                return -EAGAIN;
3245        }
3246
3247        switch (state) {
3248        case ETHTOOL_ID_ACTIVE:
3249                return 1;       /* cycle on/off once per second */
3250
3251        case ETHTOOL_ID_ON:
3252                bnx2x_acquire_phy_lock(bp);
3253                bnx2x_set_led(&bp->link_params, &bp->link_vars,
3254                              LED_MODE_ON, SPEED_1000);
3255                bnx2x_release_phy_lock(bp);
3256                break;
3257
3258        case ETHTOOL_ID_OFF:
3259                bnx2x_acquire_phy_lock(bp);
3260                bnx2x_set_led(&bp->link_params, &bp->link_vars,
3261                              LED_MODE_FRONT_PANEL_OFF, 0);
3262                bnx2x_release_phy_lock(bp);
3263                break;
3264
3265        case ETHTOOL_ID_INACTIVE:
3266                bnx2x_acquire_phy_lock(bp);
3267                bnx2x_set_led(&bp->link_params, &bp->link_vars,
3268                              LED_MODE_OPER,
3269                              bp->link_vars.line_speed);
3270                bnx2x_release_phy_lock(bp);
3271        }
3272
3273        return 0;
3274}
3275
3276static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3277{
3278        switch (info->flow_type) {
3279        case TCP_V4_FLOW:
3280        case TCP_V6_FLOW:
3281                info->data = RXH_IP_SRC | RXH_IP_DST |
3282                             RXH_L4_B_0_1 | RXH_L4_B_2_3;
3283                break;
3284        case UDP_V4_FLOW:
3285                if (bp->rss_conf_obj.udp_rss_v4)
3286                        info->data = RXH_IP_SRC | RXH_IP_DST |
3287                                     RXH_L4_B_0_1 | RXH_L4_B_2_3;
3288                else
3289                        info->data = RXH_IP_SRC | RXH_IP_DST;
3290                break;
3291        case UDP_V6_FLOW:
3292                if (bp->rss_conf_obj.udp_rss_v6)
3293                        info->data = RXH_IP_SRC | RXH_IP_DST |
3294                                     RXH_L4_B_0_1 | RXH_L4_B_2_3;
3295                else
3296                        info->data = RXH_IP_SRC | RXH_IP_DST;
3297                break;
3298        case IPV4_FLOW:
3299        case IPV6_FLOW:
3300                info->data = RXH_IP_SRC | RXH_IP_DST;
3301                break;
3302        default:
3303                info->data = 0;
3304                break;
3305        }
3306
3307        return 0;
3308}
3309
3310static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3311                           u32 *rules __always_unused)
3312{
3313        struct bnx2x *bp = netdev_priv(dev);
3314
3315        switch (info->cmd) {
3316        case ETHTOOL_GRXRINGS:
3317                info->data = BNX2X_NUM_ETH_QUEUES(bp);
3318                return 0;
3319        case ETHTOOL_GRXFH:
3320                return bnx2x_get_rss_flags(bp, info);
3321        default:
3322                DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3323                return -EOPNOTSUPP;
3324        }
3325}
3326
3327static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3328{
3329        int udp_rss_requested;
3330
3331        DP(BNX2X_MSG_ETHTOOL,
3332           "Set rss flags command parameters: flow type = %d, data = %llu\n",
3333           info->flow_type, info->data);
3334
3335        switch (info->flow_type) {
3336        case TCP_V4_FLOW:
3337        case TCP_V6_FLOW:
3338                /* For TCP only 4-tupple hash is supported */
3339                if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3340                                  RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3341                        DP(BNX2X_MSG_ETHTOOL,
3342                           "Command parameters not supported\n");
3343                        return -EINVAL;
3344                }
3345                return 0;
3346
3347        case UDP_V4_FLOW:
3348        case UDP_V6_FLOW:
3349                /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3350                if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3351                                   RXH_L4_B_0_1 | RXH_L4_B_2_3))
3352                        udp_rss_requested = 1;
3353                else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3354                        udp_rss_requested = 0;
3355                else
3356                        return -EINVAL;
3357
3358                if (CHIP_IS_E1x(bp) && udp_rss_requested) {
3359                        DP(BNX2X_MSG_ETHTOOL,
3360                           "57710, 57711 boards don't support RSS according to UDP 4-tuple\n");
3361                        return -EINVAL;
3362                }
3363
3364                if ((info->flow_type == UDP_V4_FLOW) &&
3365                    (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3366                        bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3367                        DP(BNX2X_MSG_ETHTOOL,
3368                           "rss re-configured, UDP 4-tupple %s\n",
3369                           udp_rss_requested ? "enabled" : "disabled");
3370                        return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3371                } else if ((info->flow_type == UDP_V6_FLOW) &&
3372                           (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3373                        bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3374                        DP(BNX2X_MSG_ETHTOOL,
3375                           "rss re-configured, UDP 4-tupple %s\n",
3376                           udp_rss_requested ? "enabled" : "disabled");
3377                        return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3378                }
3379                return 0;
3380
3381        case IPV4_FLOW:
3382        case IPV6_FLOW:
3383                /* For IP only 2-tupple hash is supported */
3384                if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3385                        DP(BNX2X_MSG_ETHTOOL,
3386                           "Command parameters not supported\n");
3387                        return -EINVAL;
3388                }
3389                return 0;
3390
3391        case SCTP_V4_FLOW:
3392        case AH_ESP_V4_FLOW:
3393        case AH_V4_FLOW:
3394        case ESP_V4_FLOW:
3395        case SCTP_V6_FLOW:
3396        case AH_ESP_V6_FLOW:
3397        case AH_V6_FLOW:
3398        case ESP_V6_FLOW:
3399        case IP_USER_FLOW:
3400        case ETHER_FLOW:
3401                /* RSS is not supported for these protocols */
3402                if (info->data) {
3403                        DP(BNX2X_MSG_ETHTOOL,
3404                           "Command parameters not supported\n");
3405                        return -EINVAL;
3406                }
3407                return 0;
3408
3409        default:
3410                return -EINVAL;
3411        }
3412}
3413
3414static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3415{
3416        struct bnx2x *bp = netdev_priv(dev);
3417
3418        switch (info->cmd) {
3419        case ETHTOOL_SRXFH:
3420                return bnx2x_set_rss_flags(bp, info);
3421        default:
3422                DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3423                return -EOPNOTSUPP;
3424        }
3425}
3426
3427static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3428{
3429        return T_ETH_INDIRECTION_TABLE_SIZE;
3430}
3431
3432static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3433                          u8 *hfunc)
3434{
3435        struct bnx2x *bp = netdev_priv(dev);
3436        u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3437        size_t i;
3438
3439        if (hfunc)
3440                *hfunc = ETH_RSS_HASH_TOP;
3441        if (!indir)
3442                return 0;
3443
3444        /* Get the current configuration of the RSS indirection table */
3445        bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3446
3447        /*
3448         * We can't use a memcpy() as an internal storage of an
3449         * indirection table is a u8 array while indir->ring_index
3450         * points to an array of u32.
3451         *
3452         * Indirection table contains the FW Client IDs, so we need to
3453         * align the returned table to the Client ID of the leading RSS
3454         * queue.
3455         */
3456        for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3457                indir[i] = ind_table[i] - bp->fp->cl_id;
3458
3459        return 0;
3460}
3461
3462static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
3463                          const u8 *key, const u8 hfunc)
3464{
3465        struct bnx2x *bp = netdev_priv(dev);
3466        size_t i;
3467
3468        /* We require at least one supported parameter to be changed and no
3469         * change in any of the unsupported parameters
3470         */
3471        if (key ||
3472            (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3473                return -EOPNOTSUPP;
3474
3475        if (!indir)
3476                return 0;
3477
3478        for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3479                /*
3480                 * The same as in bnx2x_get_rxfh: we can't use a memcpy()
3481                 * as an internal storage of an indirection table is a u8 array
3482                 * while indir->ring_index points to an array of u32.
3483                 *
3484                 * Indirection table contains the FW Client IDs, so we need to
3485                 * align the received table to the Client ID of the leading RSS
3486                 * queue
3487                 */
3488                bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3489        }
3490
3491        return bnx2x_config_rss_eth(bp, false);
3492}
3493
3494/**
3495 * bnx2x_get_channels - gets the number of RSS queues.
3496 *
3497 * @dev:                net device
3498 * @channels:           returns the number of max / current queues
3499 */
3500static void bnx2x_get_channels(struct net_device *dev,
3501                               struct ethtool_channels *channels)
3502{
3503        struct bnx2x *bp = netdev_priv(dev);
3504
3505        channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3506        channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3507}
3508
3509/**
3510 * bnx2x_change_num_queues - change the number of RSS queues.
3511 *
3512 * @bp:                 bnx2x private structure
3513 *
3514 * Re-configure interrupt mode to get the new number of MSI-X
3515 * vectors and re-add NAPI objects.
3516 */
3517static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3518{
3519        bnx2x_disable_msi(bp);
3520        bp->num_ethernet_queues = num_rss;
3521        bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3522        BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3523        bnx2x_set_int_mode(bp);
3524}
3525
3526/**
3527 * bnx2x_set_channels - sets the number of RSS queues.
3528 *
3529 * @dev:                net device
3530 * @channels:           includes the number of queues requested
3531 */
3532static int bnx2x_set_channels(struct net_device *dev,
3533                              struct ethtool_channels *channels)
3534{
3535        struct bnx2x *bp = netdev_priv(dev);
3536
3537        DP(BNX2X_MSG_ETHTOOL,
3538           "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3539           channels->rx_count, channels->tx_count, channels->other_count,
3540           channels->combined_count);
3541
3542        if (pci_num_vf(bp->pdev)) {
3543                DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3544                return -EPERM;
3545        }
3546
3547        /* We don't support separate rx / tx channels.
3548         * We don't allow setting 'other' channels.
3549         */
3550        if (channels->rx_count || channels->tx_count || channels->other_count
3551            || (channels->combined_count == 0) ||
3552            (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3553                DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3554                return -EINVAL;
3555        }
3556
3557        /* Check if there was a change in the active parameters */
3558        if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3559                DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3560                return 0;
3561        }
3562
3563        /* Set the requested number of queues in bp context.
3564         * Note that the actual number of queues created during load may be
3565         * less than requested if memory is low.
3566         */
3567        if (unlikely(!netif_running(dev))) {
3568                bnx2x_change_num_queues(bp, channels->combined_count);
3569                return 0;
3570        }
3571        bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3572        bnx2x_change_num_queues(bp, channels->combined_count);
3573        return bnx2x_nic_load(bp, LOAD_NORMAL);
3574}
3575
3576static int bnx2x_get_ts_info(struct net_device *dev,
3577                             struct ethtool_ts_info *info)
3578{
3579        struct bnx2x *bp = netdev_priv(dev);
3580
3581        if (bp->flags & PTP_SUPPORTED) {
3582                info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3583                                        SOF_TIMESTAMPING_RX_SOFTWARE |
3584                                        SOF_TIMESTAMPING_SOFTWARE |
3585                                        SOF_TIMESTAMPING_TX_HARDWARE |
3586                                        SOF_TIMESTAMPING_RX_HARDWARE |
3587                                        SOF_TIMESTAMPING_RAW_HARDWARE;
3588
3589                if (bp->ptp_clock)
3590                        info->phc_index = ptp_clock_index(bp->ptp_clock);
3591                else
3592                        info->phc_index = -1;
3593
3594                info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3595                                   (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3596                                   (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3597                                   (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3598
3599                info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3600
3601                return 0;
3602        }
3603
3604        return ethtool_op_get_ts_info(dev, info);
3605}
3606
3607static const struct ethtool_ops bnx2x_ethtool_ops = {
3608        .get_settings           = bnx2x_get_settings,
3609        .set_settings           = bnx2x_set_settings,
3610        .get_drvinfo            = bnx2x_get_drvinfo,
3611        .get_regs_len           = bnx2x_get_regs_len,
3612        .get_regs               = bnx2x_get_regs,
3613        .get_dump_flag          = bnx2x_get_dump_flag,
3614        .get_dump_data          = bnx2x_get_dump_data,
3615        .set_dump               = bnx2x_set_dump,
3616        .get_wol                = bnx2x_get_wol,
3617        .set_wol                = bnx2x_set_wol,
3618        .get_msglevel           = bnx2x_get_msglevel,
3619        .set_msglevel           = bnx2x_set_msglevel,
3620        .nway_reset             = bnx2x_nway_reset,
3621        .get_link               = bnx2x_get_link,
3622        .get_eeprom_len         = bnx2x_get_eeprom_len,
3623        .get_eeprom             = bnx2x_get_eeprom,
3624        .set_eeprom             = bnx2x_set_eeprom,
3625        .get_coalesce           = bnx2x_get_coalesce,
3626        .set_coalesce           = bnx2x_set_coalesce,
3627        .get_ringparam          = bnx2x_get_ringparam,
3628        .set_ringparam          = bnx2x_set_ringparam,
3629        .get_pauseparam         = bnx2x_get_pauseparam,
3630        .set_pauseparam         = bnx2x_set_pauseparam,
3631        .self_test              = bnx2x_self_test,
3632        .get_sset_count         = bnx2x_get_sset_count,
3633        .get_priv_flags         = bnx2x_get_private_flags,
3634        .get_strings            = bnx2x_get_strings,
3635        .set_phys_id            = bnx2x_set_phys_id,
3636        .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3637        .get_rxnfc              = bnx2x_get_rxnfc,
3638        .set_rxnfc              = bnx2x_set_rxnfc,
3639        .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3640        .get_rxfh               = bnx2x_get_rxfh,
3641        .set_rxfh               = bnx2x_set_rxfh,
3642        .get_channels           = bnx2x_get_channels,
3643        .set_channels           = bnx2x_set_channels,
3644        .get_module_info        = bnx2x_get_module_info,
3645        .get_module_eeprom      = bnx2x_get_module_eeprom,
3646        .get_eee                = bnx2x_get_eee,
3647        .set_eee                = bnx2x_set_eee,
3648        .get_ts_info            = bnx2x_get_ts_info,
3649};
3650
3651static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3652        .get_settings           = bnx2x_get_vf_settings,
3653        .get_drvinfo            = bnx2x_get_drvinfo,
3654        .get_msglevel           = bnx2x_get_msglevel,
3655        .set_msglevel           = bnx2x_set_msglevel,
3656        .get_link               = bnx2x_get_link,
3657        .get_coalesce           = bnx2x_get_coalesce,
3658        .get_ringparam          = bnx2x_get_ringparam,
3659        .set_ringparam          = bnx2x_set_ringparam,
3660        .get_sset_count         = bnx2x_get_sset_count,
3661        .get_strings            = bnx2x_get_strings,
3662        .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3663        .get_rxnfc              = bnx2x_get_rxnfc,
3664        .set_rxnfc              = bnx2x_set_rxnfc,
3665        .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3666        .get_rxfh               = bnx2x_get_rxfh,
3667        .set_rxfh               = bnx2x_set_rxfh,
3668        .get_channels           = bnx2x_get_channels,
3669        .set_channels           = bnx2x_set_channels,
3670};
3671
3672void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3673{
3674        netdev->ethtool_ops = (IS_PF(bp)) ?
3675                &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
3676}
3677