/*
 * This file is part of the Chelsio T4 Ethernet driver for Linux.
 *
 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/bitmap.h>
#include <linux/crc32.h>
#include <linux/ctype.h>
#include <linux/debugfs.h>
#include <linux/err.h>
#include <linux/etherdevice.h>
#include <linux/firmware.h>
#include <linux/if.h>
#include <linux/if_vlan.h>
#include <linux/init.h>
#include <linux/log2.h>
#include <linux/mdio.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/mutex.h>
#include <linux/netdevice.h>
#include <linux/pci.h>
#include <linux/aer.h>
#include <linux/rtnetlink.h>
#include <linux/sched.h>
#include <linux/seq_file.h>
#include <linux/sockios.h>
#include <linux/vmalloc.h>
#include <linux/workqueue.h>
#include <net/neighbour.h>
#include <net/netevent.h>
#include <net/addrconf.h>
#include <net/bonding.h>
#include <net/addrconf.h>
#include <asm/uaccess.h>
#include <linux/crash_dump.h>

#include "cxgb4.h"
#include "cxgb4_filter.h"
#include "t4_regs.h"
#include "t4_values.h"
#include "t4_msg.h"
#include "t4fw_api.h"
#include "t4fw_version.h"
#include "cxgb4_dcb.h"
#include "cxgb4_debugfs.h"
#include "clip_tbl.h"
#include "l2t.h"
#include "sched.h"
#include "cxgb4_tc_u32.h"

char cxgb4_driver_name[] = KBUILD_MODNAME;

#ifdef DRV_VERSION
#undef DRV_VERSION
#endif
#define DRV_VERSION "2.0.0-ko"
const char cxgb4_driver_version[] = DRV_VERSION;
#define DRV_DESC "Chelsio T4/T5/T6 Network Driver"

#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
                         NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
                         NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)

/* Macros needed to support the PCI Device ID Table ...
 */
#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
        static const struct pci_device_id cxgb4_pci_tbl[] = {
#define CH_PCI_DEVICE_ID_FUNCTION 0x4

/* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
 * called for both.
 */
#define CH_PCI_DEVICE_ID_FUNCTION2 0x0

#define CH_PCI_ID_TABLE_ENTRY(devid) \
                {PCI_VDEVICE(CHELSIO, (devid)), 4}

#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
                { 0, } \
        }

#include "t4_pci_id_tbl.h"

#define FW4_FNAME "cxgb4/t4fw.bin"
#define FW5_FNAME "cxgb4/t5fw.bin"
#define FW6_FNAME "cxgb4/t6fw.bin"
#define FW4_CFNAME "cxgb4/t4-config.txt"
#define FW5_CFNAME "cxgb4/t5-config.txt"
#define FW6_CFNAME "cxgb4/t6-config.txt"
#define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
#define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
#define PHY_AQ1202_DEVICEID 0x4409
#define PHY_BCM84834_DEVICEID 0x4486

MODULE_DESCRIPTION(DRV_DESC);
MODULE_AUTHOR("Chelsio Communications");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_VERSION(DRV_VERSION);
MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
MODULE_FIRMWARE(FW4_FNAME);
MODULE_FIRMWARE(FW5_FNAME);
MODULE_FIRMWARE(FW6_FNAME);

/*
 * Normally we're willing to become the firmware's Master PF but will be happy
 * if another PF has already become the Master and initialized the adapter.
 * Setting "force_init" will cause this driver to forcibly establish itself as
 * the Master PF and initialize the adapter.
 */
static uint force_init;

module_param(force_init, uint, 0644);
MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter,"
                 "deprecated parameter");

static int dflt_msg_enable = DFLT_MSG_ENABLE;

module_param(dflt_msg_enable, int, 0644);
MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap, "
                 "deprecated parameter");

/*
 * The driver uses the best interrupt scheme available on a platform in the
 * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
 * of these schemes the driver may consider as follows:
 *
 * msi = 2: choose from among all three options
 * msi = 1: only consider MSI and INTx interrupts
 * msi = 0: force INTx interrupts
 */
static int msi = 2;

module_param(msi, int, 0644);
MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");

/*
 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
 * offset by 2 bytes in order to have the IP headers line up on 4-byte
 * boundaries.  This is a requirement for many architectures which will throw
 * a machine check fault if an attempt is made to access one of the 4-byte IP
 * header fields on a non-4-byte boundary.  And it's a major performance issue
 * even on some architectures which allow it like some implementations of the
 * x86 ISA.  However, some architectures don't mind this and for some very
 * edge-case performance sensitive applications (like forwarding large volumes
 * of small packets), setting this DMA offset to 0 will decrease the number of
 * PCI-E Bus transfers enough to measurably affect performance.
 */
static int rx_dma_offset = 2;

#ifdef CONFIG_PCI_IOV
/* Configure the number of PCI-E Virtual Function which are to be instantiated
 * on SR-IOV Capable Physical Functions.
 */
static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];

module_param_array(num_vf, uint, NULL, 0644);
MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3, deprecated parameter - please use the pci sysfs interface.");
#endif

/* TX Queue select used to determine what algorithm to use for selecting TX
 * queue. Select between the kernel provided function (select_queue=0) or user
 * cxgb_select_queue function (select_queue=1)
 *
 * Default: select_queue=0
 */
static int select_queue;
module_param(select_queue, int, 0644);
MODULE_PARM_DESC(select_queue,
                 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");

static struct dentry *cxgb4_debugfs_root;

LIST_HEAD(adapter_list);
DEFINE_MUTEX(uld_mutex);

static void link_report(struct net_device *dev)
{
        if (!netif_carrier_ok(dev))
                netdev_info(dev, "link down\n");
        else {
                static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };

                const char *s;
                const struct port_info *p = netdev_priv(dev);

                switch (p->link_cfg.speed) {
                case 10000:
                        s = "10Gbps";
                        break;
                case 1000:
                        s = "1000Mbps";
                        break;
                case 100:
                        s = "100Mbps";
                        break;
                case 40000:
                        s = "40Gbps";
                        break;
                default:
                        pr_info("%s: unsupported speed: %d\n",
                                dev->name, p->link_cfg.speed);
                        return;
                }

                netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
                            fc[p->link_cfg.fc]);
        }
}

#ifdef CONFIG_CHELSIO_T4_DCB
/* Set up/tear down Data Center Bridging Priority mapping for a net device. */
static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
{
        struct port_info *pi = netdev_priv(dev);
        struct adapter *adap = pi->adapter;
        struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
        int i;

        /* We use a simple mapping of Port TX Queue Index to DCB
         * Priority when we're enabling DCB.
         */
        for (i = 0; i < pi->nqsets; i++, txq++) {
                u32 name, value;
                int err;

                name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
                        FW_PARAMS_PARAM_X_V(
                                FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
                        FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
                value = enable ? i : 0xffffffff;

                /* Since we can be called while atomic (from "interrupt
                 * level") we need to issue the Set Parameters Commannd
                 * without sleeping (timeout < 0).
                 */
                err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
                                            &name, &value,
                                            -FW_CMD_MAX_TIMEOUT);

                if (err)
                        dev_err(adap->pdev_dev,
                                "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
                                enable ? "set" : "unset", pi->port_id, i, -err);
                else
                        txq->dcb_prio = value;
        }
}

static int cxgb4_dcb_enabled(const struct net_device *dev)
{
        struct port_info *pi = netdev_priv(dev);

        if (!pi->dcb.enabled)
                return 0;

        return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
                (pi->dcb.state == CXGB4_DCB_STATE_HOST));
}
#endif /* CONFIG_CHELSIO_T4_DCB */

void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
{
        struct net_device *dev = adapter->port[port_id];

        /* Skip changes from disabled ports. */
        if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
                if (link_stat)
                        netif_carrier_on(dev);
                else {
#ifdef CONFIG_CHELSIO_T4_DCB
                        if (cxgb4_dcb_enabled(dev)) {
                                cxgb4_dcb_state_init(dev);
                                dcb_tx_queue_prio_enable(dev, false);
                        }
#endif /* CONFIG_CHELSIO_T4_DCB */
                        netif_carrier_off(dev);
                }

                link_report(dev);
        }
}

void t4_os_portmod_changed(const struct adapter *adap, int port_id)
{
        static const char *mod_str[] = {
                NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
        };

        const struct net_device *dev = adap->port[port_id];
        const struct port_info *pi = netdev_priv(dev);

        if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
                netdev_info(dev, "port module unplugged\n");
        else if (pi->mod_type < ARRAY_SIZE(mod_str))
                netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
        else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
                netdev_info(dev, "%s: unsupported port module inserted\n",
                            dev->name);
        else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
                netdev_info(dev, "%s: unknown port module inserted\n",
                            dev->name);
        else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
                netdev_info(dev, "%s: transceiver module error\n", dev->name);
        else
                netdev_info(dev, "%s: unknown module type %d inserted\n",
                            dev->name, pi->mod_type);
}

int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
module_param(dbfifo_int_thresh, int, 0644);
MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");

/*
 * usecs to sleep while draining the dbfifo
 */
static int dbfifo_drain_delay = 1000;
module_param(dbfifo_drain_delay, int, 0644);
MODULE_PARM_DESC(dbfifo_drain_delay,
                 "usecs to sleep while draining the dbfifo");

static inline int cxgb4_set_addr_hash(struct port_info *pi)
{
        struct adapter *adap = pi->adapter;
        u64 vec = 0;
        bool ucast = false;
        struct hash_mac_addr *entry;

        /* Calculate the hash vector for the updated list and program it */
        list_for_each_entry(entry, &adap->mac_hlist, list) {
                ucast |= is_unicast_ether_addr(entry->addr);
                vec |= (1ULL << hash_mac_addr(entry->addr));
        }
        return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
                                vec, false);
}

static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
{
        struct port_info *pi = netdev_priv(netdev);
        struct adapter *adap = pi->adapter;
        int ret;
        u64 mhash = 0;
        u64 uhash = 0;
        bool free = false;
        bool ucast = is_unicast_ether_addr(mac_addr);
        const u8 *maclist[1] = {mac_addr};
        struct hash_mac_addr *new_entry;

        ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
                                NULL, ucast ? &uhash : &mhash, false);
        if (ret < 0)
                goto out;
        /* if hash != 0, then add the addr to hash addr list
         * so on the end we will calculate the hash for the
         * list and program it
         */
        if (uhash || mhash) {
                new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
                if (!new_entry)
                        return -ENOMEM;
                ether_addr_copy(new_entry->addr, mac_addr);
                list_add_tail(&new_entry->list, &adap->mac_hlist);
                ret = cxgb4_set_addr_hash(pi);
        }
out:
        return ret < 0 ? ret : 0;
}

static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
{
        struct port_info *pi = netdev_priv(netdev);
        struct adapter *adap = pi->adapter;
        int ret;
        const u8 *maclist[1] = {mac_addr};
        struct hash_mac_addr *entry, *tmp;

        /* If the MAC address to be removed is in the hash addr
         * list, delete it from the list and update hash vector
         */
        list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
                if (ether_addr_equal(entry->addr, mac_addr)) {
                        list_del(&entry->list);
                        kfree(entry);
                        return cxgb4_set_addr_hash(pi);
                }
        }

        ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
        return ret < 0 ? -EINVAL : 0;
}

/*
 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
 * If @mtu is -1 it is left unchanged.
 */
static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
{
        struct port_info *pi = netdev_priv(dev);
        struct adapter *adapter = pi->adapter;

        __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
        __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);

        return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
                             (dev->flags & IFF_PROMISC) ? 1 : 0,
                             (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
                             sleep_ok);
}

/**
 *      link_start - enable a port
 *      @dev: the port to enable
 *
 *      Performs the MAC and PHY actions needed to enable a port.
 */
static int link_start(struct net_device *dev)
{
        int ret;
        struct port_info *pi = netdev_priv(dev);
        unsigned int mb = pi->adapter->pf;

        /*
         * We do not set address filters and promiscuity here, the stack does
         * that step explicitly.
         */
        ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
                            !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
        if (ret == 0) {
                ret = t4_change_mac(pi->adapter, mb, pi->viid,
                                    pi->xact_addr_filt, dev->dev_addr, true,
                                    true);
                if (ret >= 0) {
                        pi->xact_addr_filt = ret;
                        ret = 0;
                }
        }
        if (ret == 0)
                ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
                                    &pi->link_cfg);
        if (ret == 0) {
                local_bh_disable();
                ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
                                          true, CXGB4_DCB_ENABLED);
                local_bh_enable();
        }

        return ret;
}

#ifdef CONFIG_CHELSIO_T4_DCB
/* Handle a Data Center Bridging update message from the firmware. */
static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
{
        int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
        struct net_device *dev = adap->port[adap->chan_map[port]];
        int old_dcb_enabled = cxgb4_dcb_enabled(dev);
        int new_dcb_enabled;

        cxgb4_dcb_handle_fw_update(adap, pcmd);
        new_dcb_enabled = cxgb4_dcb_enabled(dev);

        /* If the DCB has become enabled or disabled on the port then we're
         * going to need to set up/tear down DCB Priority parameters for the
         * TX Queues associated with the port.
         */
        if (new_dcb_enabled != old_dcb_enabled)
                dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
}
#endif /* CONFIG_CHELSIO_T4_DCB */

/* Response queue handler for the FW event queue.
 */
static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
                          const struct pkt_gl *gl)
{
        u8 opcode = ((const struct rss_header *)rsp)->opcode;

        rsp++;                                          /* skip RSS header */

        /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
         */
        if (unlikely(opcode == CPL_FW4_MSG &&
           ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
                rsp++;
                opcode = ((const struct rss_header *)rsp)->opcode;
                rsp++;
                if (opcode != CPL_SGE_EGR_UPDATE) {
                        dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
                                , opcode);
                        goto out;
                }
        }

        if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
                const struct cpl_sge_egr_update *p = (void *)rsp;
                unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
                struct sge_txq *txq;

                txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
                txq->restarts++;
                if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
                        struct sge_eth_txq *eq;

                        eq = container_of(txq, struct sge_eth_txq, q);
                        netif_tx_wake_queue(eq->txq);
                } else {
                        struct sge_ofld_txq *oq;

                        oq = container_of(txq, struct sge_ofld_txq, q);
                        tasklet_schedule(&oq->qresume_tsk);
                }
        } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
                const struct cpl_fw6_msg *p = (void *)rsp;

#ifdef CONFIG_CHELSIO_T4_DCB
                const struct fw_port_cmd *pcmd = (const void *)p->data;
                unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
                unsigned int action =
                        FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));

                if (cmd == FW_PORT_CMD &&
                    action == FW_PORT_ACTION_GET_PORT_INFO) {
                        int port = FW_PORT_CMD_PORTID_G(
                                        be32_to_cpu(pcmd->op_to_portid));
                        struct net_device *dev =
                                q->adap->port[q->adap->chan_map[port]];
                        int state_input = ((pcmd->u.info.dcbxdis_pkd &
                                            FW_PORT_CMD_DCBXDIS_F)
                                           ? CXGB4_DCB_INPUT_FW_DISABLED
                                           : CXGB4_DCB_INPUT_FW_ENABLED);

                        cxgb4_dcb_state_fsm(dev, state_input);
                }

                if (cmd == FW_PORT_CMD &&
                    action == FW_PORT_ACTION_L2_DCB_CFG)
                        dcb_rpl(q->adap, pcmd);
                else
#endif
                        if (p->type == 0)
                                t4_handle_fw_rpl(q->adap, p->data);
        } else if (opcode == CPL_L2T_WRITE_RPL) {
                const struct cpl_l2t_write_rpl *p = (void *)rsp;

                do_l2t_write_rpl(q->adap, p);
        } else if (opcode == CPL_SET_TCB_RPL) {
                const struct cpl_set_tcb_rpl *p = (void *)rsp;

                filter_rpl(q->adap, p);
        } else
                dev_err(q->adap->pdev_dev,
                        "unexpected CPL %#x on FW event queue\n", opcode);
out:
        return 0;
}

static void disable_msi(struct adapter *adapter)
{
        if (adapter->flags & USING_MSIX) {
                pci_disable_msix(adapter->pdev);
                adapter->flags &= ~USING_MSIX;
        } else if (adapter->flags & USING_MSI) {
                pci_disable_msi(adapter->pdev);
                adapter->flags &= ~USING_MSI;
        }
}

/*
 * Interrupt handler for non-data events used with MSI-X.
 */
static irqreturn_t t4_nondata_intr(int irq, void *cookie)
{
        struct adapter *adap = cookie;
        u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));

        if (v & PFSW_F) {
                adap->swintr = 1;
                t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
        }
        if (adap->flags & MASTER_PF)
                t4_slow_intr_handler(adap);
        return IRQ_HANDLED;
}

/*
 * Name the MSI-X interrupts.
 */
static void name_msix_vecs(struct adapter *adap)
{
        int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);

        /* non-data interrupts */
        snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);

        /* FW events */
        snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
                 adap->port[0]->name);

        /* Ethernet queues */
        for_each_port(adap, j) {
                struct net_device *d = adap->port[j];
                const struct port_info *pi = netdev_priv(d);

                for (i = 0; i < pi->nqsets; i++, msi_idx++)
                        snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
                                 d->name, i);
        }
}

static int request_msix_queue_irqs(struct adapter *adap)
{
        struct sge *s = &adap->sge;
        int err, ethqidx;
        int msi_index = 2;

        err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
                          adap->msix_info[1].desc, &s->fw_evtq);
        if (err)
                return err;

        for_each_ethrxq(s, ethqidx) {
                err = request_irq(adap->msix_info[msi_index].vec,
                                  t4_sge_intr_msix, 0,
                                  adap->msix_info[msi_index].desc,
                                  &s->ethrxq[ethqidx].rspq);
                if (err)
                        goto unwind;
                msi_index++;
        }
        return 0;

unwind:
        while (--ethqidx >= 0)
                free_irq(adap->msix_info[--msi_index].vec,
                         &s->ethrxq[ethqidx].rspq);
        free_irq(adap->msix_info[1].vec, &s->fw_evtq);
        return err;
}

static void free_msix_queue_irqs(struct adapter *adap)
{
        int i, msi_index = 2;
        struct sge *s = &adap->sge;

        free_irq(adap->msix_info[1].vec, &s->fw_evtq);
        for_each_ethrxq(s, i)
                free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
}

/**
 *      cxgb4_write_rss - write the RSS table for a given port
 *      @pi: the port
 *      @queues: array of queue indices for RSS
 *
 *      Sets up the portion of the HW RSS table for the port's VI to distribute
 *      packets to the Rx queues in @queues.
 *      Should never be called before setting up sge eth rx queues
 */
int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
{
        u16 *rss;
        int i, err;
        struct adapter *adapter = pi->adapter;
        const struct sge_eth_rxq *rxq;

        rxq = &adapter->sge.ethrxq[pi->first_qset];
        rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
        if (!rss)
                return -ENOMEM;

        /* map the queue indices to queue ids */
        for (i = 0; i < pi->rss_size; i++, queues++)
                rss[i] = rxq[*queues].rspq.abs_id;

        err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
                                  pi->rss_size, rss, pi->rss_size);
        /* If Tunnel All Lookup isn't specified in the global RSS
         * Configuration, then we need to specify a default Ingress
         * Queue for any ingress packets which aren't hashed.  We'll
         * use our first ingress queue ...
         */
        if (!err)
                err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
                                       FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
                                       FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
                                       FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
                                       FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
                                       FW_RSS_VI_CONFIG_CMD_UDPEN_F,
                                       rss[0]);
        kfree(rss);
        return err;
}

/**
 *      setup_rss - configure RSS
 *      @adap: the adapter
 *
 *      Sets up RSS for each port.
 */
static int setup_rss(struct adapter *adap)
{
        int i, j, err;

        for_each_port(adap, i) {
                const struct port_info *pi = adap2pinfo(adap, i);

                /* Fill default values with equal distribution */
                for (j = 0; j < pi->rss_size; j++)
                        pi->rss[j] = j % pi->nqsets;

                err = cxgb4_write_rss(pi, pi->rss);
                if (err)
                        return err;
        }
        return 0;
}

/*
 * Return the channel of the ingress queue with the given qid.
 */
static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
{
        qid -= p->ingr_start;
        return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
}

/*
 * Wait until all NAPI handlers are descheduled.
 */
static void quiesce_rx(struct adapter *adap)
{
        int i;

        for (i = 0; i < adap->sge.ingr_sz; i++) {
                struct sge_rspq *q = adap->sge.ingr_map[i];

                if (q && q->handler) {
                        napi_disable(&q->napi);
                        local_bh_disable();
                        while (!cxgb_poll_lock_napi(q))
                                mdelay(1);
                        local_bh_enable();
                }

        }
}

/* Disable interrupt and napi handler */
static void disable_interrupts(struct adapter *adap)
{
        if (adap->flags & FULL_INIT_DONE) {
                t4_intr_disable(adap);
                if (adap->flags & USING_MSIX) {
                        free_msix_queue_irqs(adap);
                        free_irq(adap->msix_info[0].vec, adap);
                } else {
                        free_irq(adap->pdev->irq, adap);
                }
                quiesce_rx(adap);
        }
}

/*
 * Enable NAPI scheduling and interrupt generation for all Rx queues.
 */
static void enable_rx(struct adapter *adap)
{
        int i;

        for (i = 0; i < adap->sge.ingr_sz; i++) {
                struct sge_rspq *q = adap->sge.ingr_map[i];

                if (!q)
                        continue;
                if (q->handler) {
                        cxgb_busy_poll_init_lock(q);
                        napi_enable(&q->napi);
                }
                /* 0-increment GTS to start the timer and enable interrupts */
                t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
                             SEINTARM_V(q->intr_params) |
                             INGRESSQID_V(q->cntxt_id));
        }
}


static int setup_fw_sge_queues(struct adapter *adap)
{
        struct sge *s = &adap->sge;
        int err = 0;

        bitmap_zero(s->starving_fl, s->egr_sz);
        bitmap_zero(s->txq_maperr, s->egr_sz);

        if (adap->flags & USING_MSIX)
                adap->msi_idx = 1;         /* vector 0 is for non-queue interrupts */
        else {
                err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
                                       NULL, NULL, NULL, -1);
                if (err)
                        return err;
                adap->msi_idx = -((int)s->intrq.abs_id + 1);
        }

        err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
                               adap->msi_idx, NULL, fwevtq_handler, NULL, -1);
        if (err)
                t4_free_sge_resources(adap);
        return err;
}

/**
 *      setup_sge_queues - configure SGE Tx/Rx/response queues
 *      @adap: the adapter
 *
 *      Determines how many sets of SGE queues to use and initializes them.
 *      We support multiple queue sets per port if we have MSI-X, otherwise
 *      just one queue set per port.
 */
static int setup_sge_queues(struct adapter *adap)
{
        int err, i, j;
        struct sge *s = &adap->sge;
        struct sge_uld_rxq_info *rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
        unsigned int cmplqid = 0;

        for_each_port(adap, i) {
                struct net_device *dev = adap->port[i];
                struct port_info *pi = netdev_priv(dev);
                struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
                struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];

                for (j = 0; j < pi->nqsets; j++, q++) {
                        if (adap->msi_idx > 0)
                                adap->msi_idx++;
                        err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
                                               adap->msi_idx, &q->fl,
                                               t4_ethrx_handler,
                                               NULL,
                                               t4_get_mps_bg_map(adap,
                                                                 pi->tx_chan));
                        if (err)
                                goto freeout;
                        q->rspq.idx = j;
                        memset(&q->stats, 0, sizeof(q->stats));
                }
                for (j = 0; j < pi->nqsets; j++, t++) {
                        err = t4_sge_alloc_eth_txq(adap, t, dev,
                                        netdev_get_tx_queue(dev, j),
                                        s->fw_evtq.cntxt_id);
                        if (err)
                                goto freeout;
                }
        }

        j = s->ofldqsets / adap->params.nports; /* iscsi queues per channel */
        for_each_ofldtxq(s, i) {
                err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i],
                                            adap->port[i / j],
                                            s->fw_evtq.cntxt_id);
                if (err)
                        goto freeout;
        }

        for_each_port(adap, i) {
                /* Note that cmplqid below is 0 if we don't
                 * have RDMA queues, and that's the right value.
                 */
                if (rxq_info)
                        cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;

                err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
                                            s->fw_evtq.cntxt_id, cmplqid);
                if (err)
                        goto freeout;
        }

        t4_write_reg(adap, is_t4(adap->params.chip) ?
                                MPS_TRC_RSS_CONTROL_A :
                                MPS_T5_TRC_RSS_CONTROL_A,
                     RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
                     QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
        return 0;
freeout:
        t4_free_sge_resources(adap);
        return err;
}

/*
 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
 * The allocated memory is cleared.
 */
void *t4_alloc_mem(size_t size)
{
        void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);

        if (!p)
                p = vzalloc(size);
        return p;
}

/*
 * Free memory allocated through alloc_mem().
 */
void t4_free_mem(void *addr)
{
        kvfree(addr);
}

static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
                             void *accel_priv, select_queue_fallback_t fallback)
{
        int txq;

#ifdef CONFIG_CHELSIO_T4_DCB
        /* If a Data Center Bridging has been successfully negotiated on this
         * link then we'll use the skb's priority to map it to a TX Queue.
         * The skb's priority is determined via the VLAN Tag Priority Code
         * Point field.
         */
        if (cxgb4_dcb_enabled(dev)) {
                u16 vlan_tci;
                int err;

                err = vlan_get_tag(skb, &vlan_tci);
                if (unlikely(err)) {
                        if (net_ratelimit())
                                netdev_warn(dev,
                                            "TX Packet without VLAN Tag on DCB Link\n");
                        txq = 0;
                } else {
                        txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
#ifdef CONFIG_CHELSIO_T4_FCOE
                        if (skb->protocol == htons(ETH_P_FCOE))
                                txq = skb->priority & 0x7;
#endif /* CONFIG_CHELSIO_T4_FCOE */
                }
                return txq;
        }
#endif /* CONFIG_CHELSIO_T4_DCB */

        if (select_queue) {
                txq = (skb_rx_queue_recorded(skb)
                        ? skb_get_rx_queue(skb)
                        : smp_processor_id());

                while (unlikely(txq >= dev->real_num_tx_queues))
                        txq -= dev->real_num_tx_queues;

                return txq;
        }

        return fallback(dev, skb) % dev->real_num_tx_queues;
}

static int closest_timer(const struct sge *s, int time)
{
        int i, delta, match = 0, min_delta = INT_MAX;

        for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
                delta = time - s->timer_val[i];
                if (delta < 0)
                        delta = -delta;
                if (delta < min_delta) {
                        min_delta = delta;
                        match = i;
                }
        }

        return match;
}

static int closest_thres(const struct sge *s, int thres)
{
        int i, delta, match = 0, min_delta = INT_MAX;

        for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
                delta = thres - s->counter_val[i];
                if (delta < 0)
                        delta = -delta;
                if (delta < min_delta) {
                        min_delta = delta;
                        match = i;
                }
        }
        return match;
}

/**
 *      cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 *      @q: the Rx queue
 *      @us: the hold-off time in us, or 0 to disable timer
 *      @cnt: the hold-off packet count, or 0 to disable counter
 *
 *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
 *      one of the two needs to be enabled for the queue to generate interrupts.
 */
int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
                               unsigned int us, unsigned int cnt)
{
        struct adapter *adap = q->adap;

        if ((us | cnt) == 0)
                cnt = 1;

        if (cnt) {
                int err;
                u32 v, new_idx;

                new_idx = closest_thres(&adap->sge, cnt);
                if (q->desc && q->pktcnt_idx != new_idx) {
                        /* the queue has already been created, update it */
                        v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
                            FW_PARAMS_PARAM_X_V(
                                        FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
                            FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
                        err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
                                            &v, &new_idx);
                        if (err)
                                return err;
                }
                q->pktcnt_idx = new_idx;
        }

        us = us == 0 ? 6 : closest_timer(&adap->sge, us);
        q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
        return 0;
}

static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
{
        const struct port_info *pi = netdev_priv(dev);
        netdev_features_t changed = dev->features ^ features;
        int err;

        if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
                return 0;

        err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
                            -1, -1, -1,
                            !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
        if (unlikely(err))
                dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
        return err;
}

static int setup_debugfs(struct adapter *adap)
{
        if (IS_ERR_OR_NULL(adap->debugfs_root))
                return -1;

#ifdef CONFIG_DEBUG_FS
        t4_setup_debugfs(adap);
#endif
        return 0;
}

/*
 * upper-layer driver support
 */

/*
 * Allocate an active-open TID and set it to the supplied value.
 */
int cxgb4_alloc_atid(struct tid_info *t, void *data)
{
        int atid = -1;

        spin_lock_bh(&t->atid_lock);
        if (t->afree) {
                union aopen_entry *p = t->afree;

                atid = (p - t->atid_tab) + t->atid_base;
                t->afree = p->next;
                p->data = data;
                t->atids_in_use++;
        }
        spin_unlock_bh(&t->atid_lock);
        return atid;
}
EXPORT_SYMBOL(cxgb4_alloc_atid);

/*
 * Release an active-open TID.
 */
void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
{
        union aopen_entry *p = &t->atid_tab[atid - t->atid_base];

        spin_lock_bh(&t->atid_lock);
        p->next = t->afree;
        t->afree = p;
        t->atids_in_use--;
        spin_unlock_bh(&t->atid_lock);
}
EXPORT_SYMBOL(cxgb4_free_atid);

/*
 * Allocate a server TID and set it to the supplied value.
 */
int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
{
        int stid;

        spin_lock_bh(&t->stid_lock);
        if (family == PF_INET) {
                stid = find_first_zero_bit(t->stid_bmap, t->nstids);
                if (stid < t->nstids)
                        __set_bit(stid, t->stid_bmap);
                else
                        stid = -1;
        } else {
                stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
                if (stid < 0)
                        stid = -1;
        }
        if (stid >= 0) {
                t->stid_tab[stid].data = data;
                stid += t->stid_base;
                /* IPv6 requires max of 520 bits or 16 cells in TCAM
                 * This is equivalent to 4 TIDs. With CLIP enabled it
                 * needs 2 TIDs.
                 */
                if (family == PF_INET)
                        t->stids_in_use++;
                else
                        t->stids_in_use += 2;
        }
        spin_unlock_bh(&t->stid_lock);
        return stid;
}
EXPORT_SYMBOL(cxgb4_alloc_stid);

/* Allocate a server filter TID and set it to the supplied value.
 */
int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
{
        int stid;

        spin_lock_bh(&t->stid_lock);
        if (family == PF_INET) {
                stid = find_next_zero_bit(t->stid_bmap,
                                t->nstids + t->nsftids, t->nstids);
                if (stid < (t->nstids + t->nsftids))
                        __set_bit(stid, t->stid_bmap);
                else
                        stid = -1;
        } else {
                stid = -1;
        }
        if (stid >= 0) {
                t->stid_tab[stid].data = data;
                stid -= t->nstids;
                stid += t->sftid_base;
                t->sftids_in_use++;
        }
        spin_unlock_bh(&t->stid_lock);
        return stid;
}
EXPORT_SYMBOL(cxgb4_alloc_sftid);

/* Release a server TID.
 */
void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
{
        /* Is it a server filter TID? */
        if (t->nsftids && (stid >= t->sftid_base)) {
                stid -= t->sftid_base;
                stid += t->nstids;
        } else {
                stid -= t->stid_base;
        }

        spin_lock_bh(&t->stid_lock);
        if (family == PF_INET)
                __clear_bit(stid, t->stid_bmap);
        else
                bitmap_release_region(t->stid_bmap, stid, 1);
        t->stid_tab[stid].data = NULL;
        if (stid < t->nstids) {
                if (family == PF_INET)
                        t->stids_in_use--;
                else
                        t->stids_in_use -= 2;
        } else {
                t->sftids_in_use--;
        }
        spin_unlock_bh(&t->stid_lock);
}
EXPORT_SYMBOL(cxgb4_free_stid);

/*
 * Populate a TID_RELEASE WR.  Caller must properly size the skb.
 */
static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
                           unsigned int tid)
{
        struct cpl_tid_release *req;

        set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
        req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
        INIT_TP_WR(req, tid);
        OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
}

/*
 * Queue a TID release request and if necessary schedule a work queue to
 * process it.
 */
static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
                                    unsigned int tid)
{
        void **p = &t->tid_tab[tid];
        struct adapter *adap = container_of(t, struct adapter, tids);

        spin_lock_bh(&adap->tid_release_lock);
        *p = adap->tid_release_head;
        /* Low 2 bits encode the Tx channel number */
        adap->tid_release_head = (void **)((uintptr_t)p | chan);
        if (!adap->tid_release_task_busy) {
                adap->tid_release_task_busy = true;
                queue_work(adap->workq, &adap->tid_release_task);
        }
        spin_unlock_bh(&adap->tid_release_lock);
}

/*
 * Process the list of pending TID release requests.
 */
static void process_tid_release_list(struct work_struct *work)
{
        struct sk_buff *skb;
        struct adapter *adap;

        adap = container_of(work, struct adapter, tid_release_task);

        spin_lock_bh(&adap->tid_release_lock);
        while (adap->tid_release_head) {
                void **p = adap->tid_release_head;
                unsigned int chan = (uintptr_t)p & 3;
                p = (void *)p - chan;

                adap->tid_release_head = *p;
                *p = NULL;
                spin_unlock_bh(&adap->tid_release_lock);

                while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
                                         GFP_KERNEL)))
                        schedule_timeout_uninterruptible(1);

                mk_tid_release(skb, chan, p - adap->tids.tid_tab);
                t4_ofld_send(adap, skb);
                spin_lock_bh(&adap->tid_release_lock);
        }
        adap->tid_release_task_busy = false;
        spin_unlock_bh(&adap->tid_release_lock);
}

/*
 * Release a TID and inform HW.  If we are unable to allocate the release
 * message we defer to a work queue.
 */
void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
{
        struct sk_buff *skb;
        struct adapter *adap = container_of(t, struct adapter, tids);

        WARN_ON(tid >= t->ntids);

        if (t->tid_tab[tid]) {
                t->tid_tab[tid] = NULL;
                if (t->hash_base && (tid >= t->hash_base))
                        atomic_dec(&t->hash_tids_in_use);
                else
                        atomic_dec(&t->tids_in_use);
        }

        skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
        if (likely(skb)) {
                mk_tid_release(skb, chan, tid);
                t4_ofld_send(adap, skb);
        } else
                cxgb4_queue_tid_release(t, chan, tid);
}
EXPORT_SYMBOL(cxgb4_remove_tid);

/*
 * Allocate and initialize the TID tables.  Returns 0 on success.
 */
static int tid_init(struct tid_info *t)
{
        struct adapter *adap = container_of(t, struct adapter, tids);
        unsigned int max_ftids = t->nftids + t->nsftids;
        unsigned int natids = t->natids;
        unsigned int stid_bmap_size;
        unsigned int ftid_bmap_size;
        size_t size;

        stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
        ftid_bmap_size = BITS_TO_LONGS(t->nftids);
        size = t->ntids * sizeof(*t->tid_tab) +
               natids * sizeof(*t->atid_tab) +
               t->nstids * sizeof(*t->stid_tab) +
               t->nsftids * sizeof(*t->stid_tab) +
               stid_bmap_size * sizeof(long) +
               max_ftids * sizeof(*t->ftid_tab) +
               ftid_bmap_size * sizeof(long);

        t->tid_tab = t4_alloc_mem(size);
        if (!t->tid_tab)
                return -ENOMEM;

        t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
        t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
        t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
        t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
        t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
        spin_lock_init(&t->stid_lock);
        spin_lock_init(&t->atid_lock);
        spin_lock_init(&t->ftid_lock);

        t->stids_in_use = 0;
        t->sftids_in_use = 0;
        t->afree = NULL;
        t->atids_in_use = 0;
        atomic_set(&t->tids_in_use, 0);
        atomic_set(&t->hash_tids_in_use, 0);

        /* Setup the free list for atid_tab and clear the stid bitmap. */
        if (natids) {
                while (--natids)
                        t->atid_tab[natids - 1].next = &t->atid_tab[natids];
                t->afree = t->atid_tab;
        }

        if (is_offload(adap)) {
                bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
                /* Reserve stid 0 for T4/T5 adapters */
                if (!t->stid_base &&
                    CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
                        __set_bit(0, t->stid_bmap);
        }

        bitmap_zero(t->ftid_bmap, t->nftids);
        return 0;
}

/**
 *      cxgb4_create_server - create an IP server
 *      @dev: the device
 *      @stid: the server TID
 *      @sip: local IP address to bind server to
 *      @sport: the server's TCP port
 *      @queue: queue to direct messages from this server to
 *
 *      Create an IP server for the given port and address.
 *      Returns <0 on error and one of the %NET_XMIT_* values on success.
 */
int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
                        __be32 sip, __be16 sport, __be16 vlan,
                        unsigned int queue)
{
        unsigned int chan;
        struct sk_buff *skb;
        struct adapter *adap;
        struct cpl_pass_open_req *req;
        int ret;

        skb = alloc_skb(sizeof(*req), GFP_KERNEL);
        if (!skb)
                return -ENOMEM;

        adap = netdev2adap(dev);
        req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
        INIT_TP_WR(req, 0);
        OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
        req->local_port = sport;
        req->peer_port = htons(0);
        req->local_ip = sip;
        req->peer_ip = htonl(0);
        chan = rxq_to_chan(&adap->sge, queue);
        req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
        req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
                                SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
        ret = t4_mgmt_tx(adap, skb);
        return net_xmit_eval(ret);
}
EXPORT_SYMBOL(cxgb4_create_server);

/*      cxgb4_create_server6 - create an IPv6 server
 *      @dev: the device
 *      @stid: the server TID
 *      @sip: local IPv6 address to bind server to
 *      @sport: the server's TCP port
 *      @queue: queue to direct messages from this server to
 *
 *      Create an IPv6 server for the given port and address.
 *      Returns <0 on error and one of the %NET_XMIT_* values on success.
 */
int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
                         const struct in6_addr *sip, __be16 sport,
                         unsigned int queue)
{
        unsigned int chan;
        struct sk_buff *skb;
        struct adapter *adap;
        struct cpl_pass_open_req6 *req;
        int ret;

        skb = alloc_skb(sizeof(*req), GFP_KERNEL);
        if (!skb)
                return -ENOMEM;

        adap = netdev2adap(dev);
        req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
        INIT_TP_WR(req, 0);
        OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
        req->local_port = sport;
        req->peer_port = htons(0);
        req->local_ip_hi = *(__be64 *)(sip->s6_addr);
        req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
        req->peer_ip_hi = cpu_to_be64(0);
        req->peer_ip_lo = cpu_to_be64(0);
        chan = rxq_to_chan(&adap->sge, queue);
        req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
        req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
                                SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
        ret = t4_mgmt_tx(adap, skb);
        return net_xmit_eval(ret);
}
EXPORT_SYMBOL(cxgb4_create_server6);

int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
                        unsigned int queue, bool ipv6)
{
        struct sk_buff *skb;
        struct adapter *adap;
        struct cpl_close_listsvr_req *req;
        int ret;

        adap = netdev2adap(dev);

        skb = alloc_skb(sizeof(*req), GFP_KERNEL);
        if (!skb)
                return -ENOMEM;

        req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
        INIT_TP_WR(req, 0);
        OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
        req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
                                LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
        ret = t4_mgmt_tx(adap, skb);
        return net_xmit_eval(ret);
}
EXPORT_SYMBOL(cxgb4_remove_server);

/**
 *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
 *      @mtus: the HW MTU table
 *      @mtu: the target MTU
 *      @idx: index of selected entry in the MTU table
 *
 *      Returns the index and the value in the HW MTU table that is closest to
 *      but does not exceed @mtu, unless @mtu is smaller than any value in the
 *      table, in which case that smallest available value is selected.
 */
unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
                            unsigned int *idx)
{
        unsigned int i = 0;

        while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
                ++i;
        if (idx)
                *idx = i;
        return mtus[i];
}
EXPORT_SYMBOL(cxgb4_best_mtu);

/**
 *     cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
 *     @mtus: the HW MTU table
 *     @header_size: Header Size
 *     @data_size_max: maximum Data Segment Size
 *     @data_size_align: desired Data Segment Size Alignment (2^N)
 *     @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
 *
 *     Similar to cxgb4_best_mtu() but instead of searching the Hardware
 *     MTU Table based solely on a Maximum MTU parameter, we break that
 *     parameter up into a Header Size and Maximum Data Segment Size, and
 *     provide a desired Data Segment Size Alignment.  If we find an MTU in
 *     the Hardware MTU Table which will result in a Data Segment Size with
 *     the requested alignment _and_ that MTU isn't "too far" from the
 *     closest MTU, then we'll return that rather than the closest MTU.
 */
unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
                                    unsigned short header_size,
                                    unsigned short data_size_max,
                                    unsigned short data_size_align,
                                    unsigned int *mtu_idxp)
{
        unsigned short max_mtu = header_size + data_size_max;
        unsigned short data_size_align_mask = data_size_align - 1;
        int mtu_idx, aligned_mtu_idx;

        /* Scan the MTU Table till we find an MTU which is larger than our
         * Maximum MTU or we reach the end of the table.  Along the way,
         * record the last MTU found, if any, which will result in a Data
         * Segment Length matching the requested alignment.
         */
        for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
                unsigned short data_size = mtus[mtu_idx] - header_size;

                /* If this MTU minus the Header Size would result in a
                 * Data Segment Size of the desired alignment, remember it.
                 */
                if ((data_size & data_size_align_mask) == 0)
                        aligned_mtu_idx = mtu_idx;

                /* If we're not at the end of the Hardware MTU Table and the
                 * next element is larger than our Maximum MTU, drop out of
                 * the loop.
                 */
                if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
                        break;
        }

        /* If we fell out of the loop because we ran to the end of the table,
         * then we just have to use the last [largest] entry.
         */
        if (mtu_idx == NMTUS)
                mtu_idx--;

        /* If we found an MTU which resulted in the requested Data Segment
         * Length alignment and that's "not far" from the largest MTU which is
         * less than or equal to the maximum MTU, then use that.
         */
        if (aligned_mtu_idx >= 0 &&
            mtu_idx - aligned_mtu_idx <= 1)
                mtu_idx = aligned_mtu_idx;

        /* If the caller has passed in an MTU Index pointer, pass the
         * MTU Index back.  Return the MTU value.
         */
        if (mtu_idxp)
                *mtu_idxp = mtu_idx;
        return mtus[mtu_idx];
}
EXPORT_SYMBOL(cxgb4_best_aligned_mtu);

/**
 *      cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI
 *      @chip: chip type
 *      @viid: VI id of the given port
 *
 *      Return the SMT index for this VI.
 */
unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid)
{
        /* In T4/T5, SMT contains 256 SMAC entries organized in
         * 128 rows of 2 entries each.
         * In T6, SMT contains 256 SMAC entries in 256 rows.
         * TODO: The below code needs to be updated when we add support
         * for 256 VFs.
         */
        if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
                return ((viid & 0x7f) << 1);
        else
                return (viid & 0x7f);
}
EXPORT_SYMBOL(cxgb4_tp_smt_idx);

/**
 *      cxgb4_port_chan - get the HW channel of a port
 *      @dev: the net device for the port
 *
 *      Return the HW Tx channel of the given port.
 */
unsigned int cxgb4_port_chan(const struct net_device *dev)
{
        return netdev2pinfo(dev)->tx_chan;
}
EXPORT_SYMBOL(cxgb4_port_chan);

unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
{
        struct adapter *adap = netdev2adap(dev);
        u32 v1, v2, lp_count, hp_count;

        v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
        v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
        if (is_t4(adap->params.chip)) {
                lp_count = LP_COUNT_G(v1);
                hp_count = HP_COUNT_G(v1);
        } else {
                lp_count = LP_COUNT_T5_G(v1);
                hp_count = HP_COUNT_T5_G(v2);
        }
        return lpfifo ? lp_count : hp_count;
}
EXPORT_SYMBOL(cxgb4_dbfifo_count);

/**
 *      cxgb4_port_viid - get the VI id of a port
 *      @dev: the net device for the port
 *
 *      Return the VI id of the given port.
 */
unsigned int cxgb4_port_viid(const struct net_device *dev)
{
        return netdev2pinfo(dev)->viid;
}
EXPORT_SYMBOL(cxgb4_port_viid);

/**
 *      cxgb4_port_idx - get the index of a port
 *      @dev: the net device for the port
 *
 *      Return the index of the given port.
 */
unsigned int cxgb4_port_idx(const struct net_device *dev)
{
        return netdev2pinfo(dev)->port_id;
}
EXPORT_SYMBOL(cxgb4_port_idx);

void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
                         struct tp_tcp_stats *v6)
{
        struct adapter *adap = pci_get_drvdata(pdev);

        spin_lock(&adap->stats_lock);
        t4_tp_get_tcp_stats(adap, v4, v6);
        spin_unlock(&adap->stats_lock);
}
EXPORT_SYMBOL(cxgb4_get_tcp_stats);

void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
                      const unsigned int *pgsz_order)
{
        struct adapter *adap = netdev2adap(dev);

        t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
        t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
                     HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
                     HPZ3_V(pgsz_order[3]));
}
EXPORT_SYMBOL(cxgb4_iscsi_init);

int cxgb4_flush_eq_cache(struct net_device *dev)
{
        struct adapter *adap = netdev2adap(dev);

        return t4_sge_ctxt_flush(adap, adap->mbox);
}
EXPORT_SYMBOL(cxgb4_flush_eq_cache);

static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
{
        u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
        __be64 indices;
        int ret;

        spin_lock(&adap->win0_lock);
        ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
                           sizeof(indices), (__be32 *)&indices,
                           T4_MEMORY_READ);
        spin_unlock(&adap->win0_lock);
        if (!ret) {
                *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
                *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
        }
        return ret;
}

int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
                        u16 size)
{
        struct adapter *adap = netdev2adap(dev);
        u16 hw_pidx, hw_cidx;
        int ret;

        ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
        if (ret)
                goto out;

        if (pidx != hw_pidx) {
                u16 delta;
                u32 val;

                if (pidx >= hw_pidx)
                        delta = pidx - hw_pidx;
                else
                        delta = size - hw_pidx + pidx;

                if (is_t4(adap->params.chip))
                        val = PIDX_V(delta);
                else
                        val = PIDX_T5_V(delta);
                wmb();
                t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
                             QID_V(qid) | val);
        }
out:
        return ret;
}
EXPORT_SYMBOL(cxgb4_sync_txq_pidx);

int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
{
        struct adapter *adap;
        u32 offset, memtype, memaddr;
        u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
        u32 edc0_end, edc1_end, mc0_end, mc1_end;
        int ret;

        adap = netdev2adap(dev);

        offset = ((stag >> 8) * 32) + adap->vres.stag.start;

        /* Figure out where the offset lands in the Memory Type/Address scheme.
         * This code assumes that the memory is laid out starting at offset 0
         * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
         * and EDC1.  Some cards will have neither MC0 nor MC1, most cards have
         * MC0, and some have both MC0 and MC1.
         */
        size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
        edc0_size = EDRAM0_SIZE_G(size) << 20;
        size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
        edc1_size = EDRAM1_SIZE_G(size) << 20;
        size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
        mc0_size = EXT_MEM0_SIZE_G(size) << 20;

        edc0_end = edc0_size;
        edc1_end = edc0_end + edc1_size;
        mc0_end = edc1_end + mc0_size;

        if (offset < edc0_end) {
                memtype = MEM_EDC0;
                memaddr = offset;
        } else if (offset < edc1_end) {
                memtype = MEM_EDC1;
                memaddr = offset - edc0_end;
        } else {
                if (offset < mc0_end) {
                        memtype = MEM_MC0;
                        memaddr = offset - edc1_end;
                } else if (is_t5(adap->params.chip)) {
                        size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
                        mc1_size = EXT_MEM1_SIZE_G(size) << 20;
                        mc1_end = mc0_end + mc1_size;
                        if (offset < mc1_end) {
                                memtype = MEM_MC1;
                                memaddr = offset - mc0_end;
                        } else {
                                /* offset beyond the end of any memory */
                                goto err;
                        }
                } else {
                        /* T4/T6 only has a single memory channel */
                        goto err;
                }
        }

        spin_lock(&adap->win0_lock);
        ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
        spin_unlock(&adap->win0_lock);
        return ret;

err:
        dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
                stag, offset);
        return -EINVAL;
}
EXPORT_SYMBOL(cxgb4_read_tpte);

u64 cxgb4_read_sge_timestamp(struct net_device *dev)
{
        u32 hi, lo;
        struct adapter *adap;

        adap = netdev2adap(dev);
        lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
        hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));

        return ((u64)hi << 32) | (u64)lo;
}
EXPORT_SYMBOL(cxgb4_read_sge_timestamp);

int cxgb4_bar2_sge_qregs(struct net_device *dev,
                         unsigned int qid,
                         enum cxgb4_bar2_qtype qtype,
                         int user,
                         u64 *pbar2_qoffset,
                         unsigned int *pbar2_qid)
{
        return t4_bar2_sge_qregs(netdev2adap(dev),
                                 qid,
                                 (qtype == CXGB4_BAR2_QTYPE_EGRESS
                                  ? T4_BAR2_QTYPE_EGRESS
                                  : T4_BAR2_QTYPE_INGRESS),
                                 user,
                                 pbar2_qoffset,
                                 pbar2_qid);
}
EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);

static struct pci_driver cxgb4_driver;

static void check_neigh_update(struct neighbour *neigh)
{
        const struct device *parent;
        const struct net_device *netdev = neigh->dev;

        if (netdev->priv_flags & IFF_802_1Q_VLAN)
                netdev = vlan_dev_real_dev(netdev);
        parent = netdev->dev.parent;
        if (parent && parent->driver == &cxgb4_driver.driver)
                t4_l2t_update(dev_get_drvdata(parent), neigh);
}

static int netevent_cb(struct notifier_block *nb, unsigned long event,
                       void *data)
{
        switch (event) {
        case NETEVENT_NEIGH_UPDATE:
                check_neigh_update(data);
                break;
        case NETEVENT_REDIRECT:
        default:
                break;
        }
        return 0;
}

static bool netevent_registered;
static struct notifier_block cxgb4_netevent_nb = {
        .notifier_call = netevent_cb
};

static void drain_db_fifo(struct adapter *adap, int usecs)
{
        u32 v1, v2, lp_count, hp_count;

        do {
                v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
                v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
                if (is_t4(adap->params.chip)) {
                        lp_count = LP_COUNT_G(v1);
                        hp_count = HP_COUNT_G(v1);
                } else {
                        lp_count = LP_COUNT_T5_G(v1);
                        hp_count = HP_COUNT_T5_G(v2);
                }

                if (lp_count == 0 && hp_count == 0)
                        break;
                set_current_state(TASK_UNINTERRUPTIBLE);
                schedule_timeout(usecs_to_jiffies(usecs));
        } while (1);
}

static void disable_txq_db(struct sge_txq *q)
{
        unsigned long flags;

        spin_lock_irqsave(&q->db_lock, flags);
        q->db_disabled = 1;
        spin_unlock_irqrestore(&q->db_lock, flags);
}

static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
{
        spin_lock_irq(&q->db_lock);
        if (q->db_pidx_inc) {
                /* Make sure that all writes to the TX descriptors
                 * are committed before we tell HW about them.
                 */
                wmb();
                t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
                             QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
                q->db_pidx_inc = 0;
        }
        q->db_disabled = 0;
        spin_unlock_irq(&q->db_lock);
}

static void disable_dbs(struct adapter *adap)
{
        int i;

        for_each_ethrxq(&adap->sge, i)
                disable_txq_db(&adap->sge.ethtxq[i].q);
        for_each_ofldtxq(&adap->sge, i)
                disable_txq_db(&adap->sge.ofldtxq[i].q);
        for_each_port(adap, i)
                disable_txq_db(&adap->sge.ctrlq[i].q);
}

static void enable_dbs(struct adapter *adap)
{
        int i;

        for_each_ethrxq(&adap->sge, i)
                enable_txq_db(adap, &adap->sge.ethtxq[i].q);
        for_each_ofldtxq(&adap->sge, i)
                enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
        for_each_port(adap, i)
                enable_txq_db(adap, &adap->sge.ctrlq[i].q);
}

static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
{
        enum cxgb4_uld type = CXGB4_ULD_RDMA;

        if (adap->uld && adap->uld[type].handle)
                adap->uld[type].control(adap->uld[type].handle, cmd);
}

static void process_db_full(struct work_struct *work)
{
        struct adapter *adap;

        adap = container_of(work, struct adapter, db_full_task);

        drain_db_fifo(adap, dbfifo_drain_delay);
        enable_dbs(adap);
        notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
        if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
                t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
                                 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
                                 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
        else
                t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
                                 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
}

static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
{
        u16 hw_pidx, hw_cidx;
        int ret;

        spin_lock_irq(&q->db_lock);
        ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
        if (ret)
                goto out;
        if (q->db_pidx != hw_pidx) {
                u16 delta;
                u32 val;

                if (q->db_pidx >= hw_pidx)
                        delta = q->db_pidx - hw_pidx;
                else
                        delta = q->size - hw_pidx + q->db_pidx;

                if (is_t4(adap->params.chip))
                        val = PIDX_V(delta);
                else
                        val = PIDX_T5_V(delta);
                wmb();
                t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
                             QID_V(q->cntxt_id) | val);
        }
out:
        q->db_disabled = 0;
        q->db_pidx_inc = 0;
        spin_unlock_irq(&q->db_lock);
        if (ret)
                CH_WARN(adap, "DB drop recovery failed.\n");

}

static void recover_all_queues(struct adapter *adap)
{
        int i;

        for_each_ethrxq(&adap->sge, i)
                sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
        for_each_ofldtxq(&adap->sge, i)
                sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
        for_each_port(adap, i)
                sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
}

static void process_db_drop(struct work_struct *work)
{
        struct adapter *adap;

        adap = container_of(work, struct adapter, db_drop_task);

        if (is_t4(adap->params.chip)) {
                drain_db_fifo(adap, dbfifo_drain_delay);
                notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
                drain_db_fifo(adap, dbfifo_drain_delay);
                recover_all_queues(adap);
                drain_db_fifo(adap, dbfifo_drain_delay);
                enable_dbs(adap);
                notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
        } else if (is_t5(adap->params.chip)) {
                u32 dropped_db = t4_read_reg(adap, 0x010ac);
                u16 qid = (dropped_db >> 15) & 0x1ffff;
                u16 pidx_inc = dropped_db & 0x1fff;
                u64 bar2_qoffset;
                unsigned int bar2_qid;
                int ret;

                ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
                                        0, &bar2_qoffset, &bar2_qid);
                if (ret)
                        dev_err(adap->pdev_dev, "doorbell drop recovery: "
                                "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
                else
                        writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
                               adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);

                /* Re-enable BAR2 WC */
                t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
        }

        if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
                t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
}

void t4_db_full(struct adapter *adap)
{
        if (is_t4(adap->params.chip)) {
                disable_dbs(adap);
                notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
                t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
                                 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
                queue_work(adap->workq, &adap->db_full_task);
        }
}

void t4_db_dropped(struct adapter *adap)
{
        if (is_t4(adap->params.chip)) {
                disable_dbs(adap);
                notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
        }
        queue_work(adap->workq, &adap->db_drop_task);
}

void t4_register_netevent_notifier(void)
{
        if (!netevent_registered) {
                register_netevent_notifier(&cxgb4_netevent_nb);
                netevent_registered = true;
        }
}

static void detach_ulds(struct adapter *adap)
{
        unsigned int i;

        mutex_lock(&uld_mutex);
        list_del(&adap->list_node);
        for (i = 0; i < CXGB4_ULD_MAX; i++)
                if (adap->uld && adap->uld[i].handle) {
                        adap->uld[i].state_change(adap->uld[i].handle,
                                             CXGB4_STATE_DETACH);
                        adap->uld[i].handle = NULL;
                }
        if (netevent_registered && list_empty(&adapter_list)) {
                unregister_netevent_notifier(&cxgb4_netevent_nb);
                netevent_registered = false;
        }
        mutex_unlock(&uld_mutex);
}

static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
{
        unsigned int i;

        mutex_lock(&uld_mutex);
        for (i = 0; i < CXGB4_ULD_MAX; i++)
                if (adap->uld && adap->uld[i].handle)
                        adap->uld[i].state_change(adap->uld[i].handle,
                                                  new_state);
        mutex_unlock(&uld_mutex);
}

#if IS_ENABLED(CONFIG_IPV6)
static int cxgb4_inet6addr_handler(struct notifier_block *this,
                                   unsigned long event, void *data)
{
        struct inet6_ifaddr *ifa = data;
        struct net_device *event_dev = ifa->idev->dev;
        const struct device *parent = NULL;
#if IS_ENABLED(CONFIG_BONDING)
        struct adapter *adap;
#endif
        if (event_dev->priv_flags & IFF_802_1Q_VLAN)
                event_dev = vlan_dev_real_dev(event_dev);
#if IS_ENABLED(CONFIG_BONDING)
        if (event_dev->flags & IFF_MASTER) {
                list_for_each_entry(adap, &adapter_list, list_node) {
                        switch (event) {
                        case NETDEV_UP:
                                cxgb4_clip_get(adap->port[0],
                                               (const u32 *)ifa, 1);
                                break;
                        case NETDEV_DOWN:
                                cxgb4_clip_release(adap->port[0],
                                                   (const u32 *)ifa, 1);
                                break;
                        default:
                                break;
                        }
                }
                return NOTIFY_OK;
        }
#endif

        if (event_dev)
                parent = event_dev->dev.parent;

        if (parent && parent->driver == &cxgb4_driver.driver) {
                switch (event) {
                case NETDEV_UP:
                        cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
                        break;
                case NETDEV_DOWN:
                        cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
                        break;
                default:
                        break;
                }
        }
        return NOTIFY_OK;
}

static bool inet6addr_registered;
static struct notifier_block cxgb4_inet6addr_notifier = {
        .notifier_call = cxgb4_inet6addr_handler
};

static void update_clip(const struct adapter *adap)
{
        int i;
        struct net_device *dev;
        int ret;

        rcu_read_lock();

        for (i = 0; i < MAX_NPORTS; i++) {
                dev = adap->port[i];
                ret = 0;

                if (dev)
                        ret = cxgb4_update_root_dev_clip(dev);

                if (ret < 0)
                        break;
        }
        rcu_read_unlock();
}
#endif /* IS_ENABLED(CONFIG_IPV6) */

/**
 *      cxgb_up - enable the adapter
 *      @adap: adapter being enabled
 *
 *      Called when the first port is enabled, this function performs the
 *      actions necessary to make an adapter operational, such as completing
 *      the initialization of HW modules, and enabling interrupts.
 *
 *      Must be called with the rtnl lock held.
 */
static int cxgb_up(struct adapter *adap)
{
        int err;

        err = setup_sge_queues(adap);
        if (err)
                goto out;
        err = setup_rss(adap);
        if (err)
                goto freeq;

        if (adap->flags & USING_MSIX) {
                name_msix_vecs(adap);
                err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
                                  adap->msix_info[0].desc, adap);
                if (err)
                        goto irq_err;
                err = request_msix_queue_irqs(adap);
                if (err) {
                        free_irq(adap->msix_info[0].vec, adap);
                        goto irq_err;
                }
        } else {
                err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
                                  (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
                                  adap->port[0]->name, adap);
                if (err)
                        goto irq_err;
        }
        enable_rx(adap);
        t4_sge_start(adap);
        t4_intr_enable(adap);
        adap->flags |= FULL_INIT_DONE;
        notify_ulds(adap, CXGB4_STATE_UP);
#if IS_ENABLED(CONFIG_IPV6)
        update_clip(adap);
#endif
        /* Initialize hash mac addr list*/
        INIT_LIST_HEAD(&adap->mac_hlist);
 out:
        return err;
 irq_err:
        dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
 freeq:
        t4_free_sge_resources(adap);
        goto out;
}

static void cxgb_down(struct adapter *adapter)
{
        cancel_work_sync(&adapter->tid_release_task);
        cancel_work_sync(&adapter->db_full_task);
        cancel_work_sync(&adapter->db_drop_task);
        adapter->tid_release_task_busy = false;
        adapter->tid_release_head = NULL;

        t4_sge_stop(adapter);
        t4_free_sge_resources(adapter);
        adapter->flags &= ~FULL_INIT_DONE;
}

/*
 * net_device operations
 */
static int cxgb_open(struct net_device *dev)
{
        int err;
        struct port_info *pi = netdev_priv(dev);
        struct adapter *adapter = pi->adapter;

        netif_carrier_off(dev);

        if (!(adapter->flags & FULL_INIT_DONE)) {
                err = cxgb_up(adapter);
                if (err < 0)
                        return err;
        }

        err = link_start(dev);
        if (!err)
                netif_tx_start_all_queues(dev);
        return err;
}

static int cxgb_close(struct net_device *dev)
{
        struct port_info *pi = netdev_priv(dev);
        struct adapter *adapter = pi->adapter;

        netif_tx_stop_all_queues(dev);
        netif_carrier_off(dev);
        return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false);
}

int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
                __be32 sip, __be16 sport, __be16 vlan,
                unsigned int queue, unsigned char port, unsigned char mask)
{
        int ret;
        struct filter_entry *f;
        struct adapter *adap;
        int i;
        u8 *val;

        adap = netdev2adap(dev);

        /* Adjust stid to correct filter index */
        stid -= adap->tids.sftid_base;
        stid += adap->tids.nftids;

        /* Check to make sure the filter requested is writable ...
         */
        f = &adap->tids.ftid_tab[stid];
        ret = writable_filter(f);
        if (ret)
                return ret;

        /* Clear out any old resources being used by the filter before
         * we start constructing the new filter.
         */
        if (f->valid)
                clear_filter(adap, f);

        /* Clear out filter specifications */
        memset(&f->fs, 0, sizeof(struct ch_filter_specification));
        f->fs.val.lport = cpu_to_be16(sport);
        f->fs.mask.lport  = ~0;
        val = (u8 *)&sip;
        if ((val[0] | val[1] | val[2] | val[3]) != 0) {
                for (i = 0; i < 4; i++) {
                        f->fs.val.lip[i] = val[i];
                        f->fs.mask.lip[i] = ~0;
                }
                if (adap->params.tp.vlan_pri_map & PORT_F) {
                        f->fs.val.iport = port;
                        f->fs.mask.iport = mask;
                }
        }

        if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
                f->fs.val.proto = IPPROTO_TCP;
                f->fs.mask.proto = ~0;
        }

        f->fs.dirsteer = 1;
        f->fs.iq = queue;
        /* Mark filter as locked */
        f->locked = 1;
        f->fs.rpttid = 1;

        ret = set_filter_wr(adap, stid);
        if (ret) {
                clear_filter(adap, f);
                return ret;
        }

        return 0;
}
EXPORT_SYMBOL(cxgb4_create_server_filter);

int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
                unsigned int queue, bool ipv6)
{
        struct filter_entry *f;
        struct adapter *adap;

        adap = netdev2adap(dev);

        /* Adjust stid to correct filter index */
        stid -= adap->tids.sftid_base;
        stid += adap->tids.nftids;

        f = &adap->tids.ftid_tab[stid];
        /* Unlock the filter */
        f->locked = 0;

        return delete_filter(adap, stid);
}
EXPORT_SYMBOL(cxgb4_remove_server_filter);

static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
                                                struct rtnl_link_stats64 *ns)
{
        struct port_stats stats;
        struct port_info *p = netdev_priv(dev);
        struct adapter *adapter = p->adapter;

        /* Block retrieving statistics during EEH error
         * recovery. Otherwise, the recovery might fail
         * and the PCI device will be removed permanently
         */
        spin_lock(&adapter->stats_lock);
        if (!netif_device_present(dev)) {
                spin_unlock(&adapter->stats_lock);
                return ns;
        }
        t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
                                 &p->stats_base);
        spin_unlock(&adapter->stats_lock);

        ns->tx_bytes   = stats.tx_octets;
        ns->tx_packets = stats.tx_frames;
        ns->rx_bytes   = stats.rx_octets;
        ns->rx_packets = stats.rx_frames;
        ns->multicast  = stats.rx_mcast_frames;

        /* detailed rx_errors */
        ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
                               stats.rx_runt;
        ns->rx_over_errors   = 0;
        ns->rx_crc_errors    = stats.rx_fcs_err;
        ns->rx_frame_errors  = stats.rx_symbol_err;
        ns->rx_fifo_errors   = stats.rx_ovflow0 + stats.rx_ovflow1 +
                               stats.rx_ovflow2 + stats.rx_ovflow3 +
                               stats.rx_trunc0 + stats.rx_trunc1 +
                               stats.rx_trunc2 + stats.rx_trunc3;
        ns->rx_missed_errors = 0;

        /* detailed tx_errors */
        ns->tx_aborted_errors   = 0;
        ns->tx_carrier_errors   = 0;
        ns->tx_fifo_errors      = 0;
        ns->tx_heartbeat_errors = 0;
        ns->tx_window_errors    = 0;

        ns->tx_errors = stats.tx_error_frames;
        ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
                ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
        return ns;
}

static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
{
        unsigned int mbox;
        int ret = 0, prtad, devad;
        struct port_info *pi = netdev_priv(dev);
        struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;

        switch (cmd) {
        case SIOCGMIIPHY:
                if (pi->mdio_addr < 0)
                        return -EOPNOTSUPP;
                data->phy_id = pi->mdio_addr;
                break;
        case SIOCGMIIREG:
        case SIOCSMIIREG:
                if (mdio_phy_id_is_c45(data->phy_id)) {
                        prtad = mdio_phy_id_prtad(data->phy_id);
                        devad = mdio_phy_id_devad(data->phy_id);
                } else if (data->phy_id < 32) {
                        prtad = data->phy_id;
                        devad = 0;
                        data->reg_num &= 0x1f;
                } else
                        return -EINVAL;

                mbox = pi->adapter->pf;
                if (cmd == SIOCGMIIREG)
                        ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
                                         data->reg_num, &data->val_out);
                else
                        ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
                                         data->reg_num, data->val_in);
                break;
        case SIOCGHWTSTAMP:
                return copy_to_user(req->ifr_data, &pi->tstamp_config,
                                    sizeof(pi->tstamp_config)) ?
                        -EFAULT : 0;
        case SIOCSHWTSTAMP:
                if (copy_from_user(&pi->tstamp_config, req->ifr_data,
                                   sizeof(pi->tstamp_config)))
                        return -EFAULT;

                switch (pi->tstamp_config.rx_filter) {
                case HWTSTAMP_FILTER_NONE:
                        pi->rxtstamp = false;
                        break;
                case HWTSTAMP_FILTER_ALL:
                        pi->rxtstamp = true;
                        break;
                default:
                        pi->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
                        return -ERANGE;
                }

                return copy_to_user(req->ifr_data, &pi->tstamp_config,
                                    sizeof(pi->tstamp_config)) ?
                        -EFAULT : 0;
        default:
                return -EOPNOTSUPP;
        }
        return ret;
}

static void cxgb_set_rxmode(struct net_device *dev)
{
        /* unfortunately we can't return errors to the stack */
        set_rxmode(dev, -1, false);
}

static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
{
        int ret;
        struct port_info *pi = netdev_priv(dev);

        if (new_mtu < 81 || new_mtu > MAX_MTU)         /* accommodate SACK */
                return -EINVAL;
        ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
                            -1, -1, -1, true);
        if (!ret)
                dev->mtu = new_mtu;
        return ret;
}

#ifdef CONFIG_PCI_IOV
static int dummy_open(struct net_device *dev)
{
        /* Turn carrier off since we don't have to transmit anything on this
         * interface.
         */
        netif_carrier_off(dev);
        return 0;
}

/* Fill MAC address that will be assigned by the FW */
static void fill_vf_station_mac_addr(struct adapter *adap)
{
        unsigned int i;
        u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
        int err;
        u8 *na;
        u16 a, b;

        err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
        if (!err) {
                na = adap->params.vpd.na;
                for (i = 0; i < ETH_ALEN; i++)
                        hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
                                      hex2val(na[2 * i + 1]));
                a = (hw_addr[0] << 8) | hw_addr[1];
                b = (hw_addr[1] << 8) | hw_addr[2];
                a ^= b;
                a |= 0x0200;    /* locally assigned Ethernet MAC address */
                a &= ~0x0100;   /* not a multicast Ethernet MAC address */
                macaddr[0] = a >> 8;
                macaddr[1] = a & 0xff;

                for (i = 2; i < 5; i++)
                        macaddr[i] = hw_addr[i + 1];

                for (i = 0; i < adap->num_vfs; i++) {
                        macaddr[5] = adap->pf * 16 + i;
                        ether_addr_copy(adap->vfinfo[i].vf_mac_addr, macaddr);
                }
        }
}

static int cxgb_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
{
        struct port_info *pi = netdev_priv(dev);
        struct adapter *adap = pi->adapter;
        int ret;

        /* verify MAC addr is valid */
        if (!is_valid_ether_addr(mac)) {
                dev_err(pi->adapter->pdev_dev,
                        "Invalid Ethernet address %pM for VF %d\n",
                        mac, vf);
                return -EINVAL;
        }

        dev_info(pi->adapter->pdev_dev,
                 "Setting MAC %pM on VF %d\n", mac, vf);
        ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
        if (!ret)
                ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
        return ret;
}

static int cxgb_get_vf_config(struct net_device *dev,
                              int vf, struct ifla_vf_info *ivi)
{
        struct port_info *pi = netdev_priv(dev);
        struct adapter *adap = pi->adapter;

        if (vf >= adap->num_vfs)
                return -EINVAL;
        ivi->vf = vf;
        ether_addr_copy(ivi->mac, adap->vfinfo[vf].vf_mac_addr);
        return 0;
}
#endif

static int cxgb_set_mac_addr(struct net_device *dev, void *p)
{
        int ret;
        struct sockaddr *addr = p;
        struct port_info *pi = netdev_priv(dev);

        if (!is_valid_ether_addr(addr->sa_data))
                return -EADDRNOTAVAIL;

        ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
                            pi->xact_addr_filt, addr->sa_data, true, true);
        if (ret < 0)
                return ret;

        memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
        pi->xact_addr_filt = ret;
        return 0;
}

#ifdef CONFIG_NET_POLL_CONTROLLER
static void cxgb_netpoll(struct net_device *dev)
{
        struct port_info *pi = netdev_priv(dev);
        struct adapter *adap = pi->adapter;

        if (adap->flags & USING_MSIX) {
                int i;
                struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];

                for (i = pi->nqsets; i; i--, rx++)
                        t4_sge_intr_msix(0, &rx->rspq);
        } else
                t4_intr_handler(adap)(0, adap);
}
#endif

static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
{
        struct port_info *pi = netdev_priv(dev);
        struct adapter *adap = pi->adapter;
        struct sched_class *e;
        struct ch_sched_params p;
        struct ch_sched_queue qe;
        u32 req_rate;
        int err = 0;

        if (!can_sched(dev))
                return -ENOTSUPP;

        if (index < 0 || index > pi->nqsets - 1)
                return -EINVAL;

        if (!(adap->flags & FULL_INIT_DONE)) {
                dev_err(adap->pdev_dev,
                        "Failed to rate limit on queue %d. Link Down?\n",
                        index);
                return -EINVAL;
        }

        /* Convert from Mbps to Kbps */
        req_rate = rate << 10;

        /* Max rate is 10 Gbps */
        if (req_rate >= SCHED_MAX_RATE_KBPS) {
                dev_err(adap->pdev_dev,
                        "Invalid rate %u Mbps, Max rate is %u Gbps\n",
                        rate, SCHED_MAX_RATE_KBPS);
                return -ERANGE;
        }

        /* First unbind the queue from any existing class */
        memset(&qe, 0, sizeof(qe));
        qe.queue = index;
        qe.class = SCHED_CLS_NONE;

        err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
        if (err) {
                dev_err(adap->pdev_dev,
                        "Unbinding Queue %d on port %d fail. Err: %d\n",
                        index, pi->port_id, err);
                return err;
        }

        /* Queue already unbound */
        if (!req_rate)
                return 0;

        /* Fetch any available unused or matching scheduling class */
        memset(&p, 0, sizeof(p));
        p.type = SCHED_CLASS_TYPE_PACKET;
        p.u.params.level    = SCHED_CLASS_LEVEL_CL_RL;
        p.u.params.mode     = SCHED_CLASS_MODE_CLASS;
        p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
        p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
        p.u.params.channel  = pi->tx_chan;
        p.u.params.class    = SCHED_CLS_NONE;
        p.u.params.minrate  = 0;
        p.u.params.maxrate  = req_rate;
        p.u.params.weight   = 0;
        p.u.params.pktsize  = dev->mtu;

        e = cxgb4_sched_class_alloc(dev, &p);
        if (!e)
                return -ENOMEM;

        /* Bind the queue to a scheduling class */
        memset(&qe, 0, sizeof(qe));
        qe.queue = index;
        qe.class = e->idx;

        err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
        if (err)
                dev_err(adap->pdev_dev,
                        "Queue rate limiting failed. Err: %d\n", err);
        return err;
}

static int cxgb_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
                         struct tc_to_netdev *tc)
{
        struct port_info *pi = netdev2pinfo(dev);
        struct adapter *adap = netdev2adap(dev);

        if (!(adap->flags & FULL_INIT_DONE)) {
                dev_err(adap->pdev_dev,
                        "Failed to setup tc on port %d. Link Down?\n",
                        pi->port_id);
                return -EINVAL;
        }

        if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) &&
            tc->type == TC_SETUP_CLSU32) {
                switch (tc->cls_u32->command) {
                case TC_CLSU32_NEW_KNODE:
                case TC_CLSU32_REPLACE_KNODE:
                        return cxgb4_config_knode(dev, proto, tc->cls_u32);
                case TC_CLSU32_DELETE_KNODE:
                        return cxgb4_delete_knode(dev, proto, tc->cls_u32);
                default:
                        return -EOPNOTSUPP;
                }
        }

        return -EOPNOTSUPP;
}

static const struct net_device_ops cxgb4_netdev_ops = {
        .ndo_open             = cxgb_open,
        .ndo_stop             = cxgb_close,
        .ndo_start_xmit       = t4_eth_xmit,
        .ndo_select_queue     = cxgb_select_queue,
        .ndo_get_stats64      = cxgb_get_stats,
        .ndo_set_rx_mode      = cxgb_set_rxmode,
        .ndo_set_mac_address  = cxgb_set_mac_addr,
        .ndo_set_features     = cxgb_set_features,
        .ndo_validate_addr    = eth_validate_addr,
        .ndo_do_ioctl         = cxgb_ioctl,
        .ndo_change_mtu       = cxgb_change_mtu,
#ifdef CONFIG_NET_POLL_CONTROLLER
        .ndo_poll_controller  = cxgb_netpoll,
#endif
#ifdef CONFIG_CHELSIO_T4_FCOE
        .ndo_fcoe_enable      = cxgb_fcoe_enable,
        .ndo_fcoe_disable     = cxgb_fcoe_disable,
#endif /* CONFIG_CHELSIO_T4_FCOE */
#ifdef CONFIG_NET_RX_BUSY_POLL
        .ndo_busy_poll        = cxgb_busy_poll,
#endif
        .ndo_set_tx_maxrate   = cxgb_set_tx_maxrate,
        .ndo_setup_tc         = cxgb_setup_tc,
};

#ifdef CONFIG_PCI_IOV
static const struct net_device_ops cxgb4_mgmt_netdev_ops = {
        .ndo_open             = dummy_open,
        .ndo_set_vf_mac       = cxgb_set_vf_mac,
        .ndo_get_vf_config    = cxgb_get_vf_config,
};
#endif

static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
{
        struct adapter *adapter = netdev2adap(dev);

        strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
        strlcpy(info->version, cxgb4_driver_version,
                sizeof(info->version));
        strlcpy(info->bus_info, pci_name(adapter->pdev),
                sizeof(info->bus_info));
}

static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = {
        .get_drvinfo       = get_drvinfo,
};

void t4_fatal_err(struct adapter *adap)
{
        t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);
        t4_intr_disable(adap);
        dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
}

static void setup_memwin(struct adapter *adap)
{
        u32 nic_win_base = t4_get_util_window(adap);

        t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
}

static void setup_memwin_rdma(struct adapter *adap)
{
        if (adap->vres.ocq.size) {
                u32 start;
                unsigned int sz_kb;

                start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
                start &= PCI_BASE_ADDRESS_MEM_MASK;
                start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
                sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
                t4_write_reg(adap,
                             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
                             start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
                t4_write_reg(adap,
                             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
                             adap->vres.ocq.start);
                t4_read_reg(adap,
                            PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
        }
}

static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
{
        u32 v;
        int ret;

        /* get device capabilities */
        memset(c, 0, sizeof(*c));
        c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
                               FW_CMD_REQUEST_F | FW_CMD_READ_F);
        c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
        ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
        if (ret < 0)
                return ret;

        c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
                               FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
        ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
        if (ret < 0)
                return ret;

        ret = t4_config_glbl_rss(adap, adap->pf,
                                 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
                                 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
                                 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
        if (ret < 0)
                return ret;

        ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
                          MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
                          FW_CMD_CAP_PF);
        if (ret < 0)
                return ret;

        t4_sge_init(adap);

        /* tweak some settings */
        t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
        t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
        t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
        v = t4_read_reg(adap, TP_PIO_DATA_A);
        t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);

        /* first 4 Tx modulation queues point to consecutive Tx channels */
        adap->params.tp.tx_modq_map = 0xE4;
        t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
                     TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));

        /* associate each Tx modulation queue with consecutive Tx channels */
        v = 0x84218421;
        t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
                          &v, 1, TP_TX_SCHED_HDR_A);
        t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
                          &v, 1, TP_TX_SCHED_FIFO_A);
        t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
                          &v, 1, TP_TX_SCHED_PCMD_A);

#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
        if (is_offload(adap)) {
                t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
                             TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
                             TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
                             TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
                             TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
                t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
                             TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
                             TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
                             TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
                             TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
        }

        /* get basic stuff going */
        return t4_early_init(adap, adap->pf);
}

/*
 * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
 */
#define MAX_ATIDS 8192U

/*
 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
 *
 * If the firmware we're dealing with has Configuration File support, then
 * we use that to perform all configuration
 */

/*
 * Tweak configuration based on module parameters, etc.  Most of these have
 * defaults assigned to them by Firmware Configuration Files (if we're using
 * them) but need to be explicitly set if we're using hard-coded
 * initialization.  But even in the case of using Firmware Configuration
 * Files, we'd like to expose the ability to change these via module
 * parameters so these are essentially common tweaks/settings for
 * Configuration Files and hard-coded initialization ...
 */
static int adap_init0_tweaks(struct adapter *adapter)
{
        /*
         * Fix up various Host-Dependent Parameters like Page Size, Cache
         * Line Size, etc.  The firmware default is for a 4KB Page Size and
         * 64B Cache Line Size ...
         */
        t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);

        /*
         * Process module parameters which affect early initialization.
         */
        if (rx_dma_offset != 2 && rx_dma_offset != 0) {
                dev_err(&adapter->pdev->dev,
                        "Ignoring illegal rx_dma_offset=%d, using 2\n",
                        rx_dma_offset);
                rx_dma_offset = 2;
        }
        t4_set_reg_field(adapter, SGE_CONTROL_A,
                         PKTSHIFT_V(PKTSHIFT_M),
                         PKTSHIFT_V(rx_dma_offset));

        /*
         * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
         * adds the pseudo header itself.
         */
        t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
                               CSUM_HAS_PSEUDO_HDR_F, 0);

        return 0;
}

/* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
 * unto themselves and they contain their own firmware to perform their
 * tasks ...
 */
static int phy_aq1202_version(const u8 *phy_fw_data,
                              size_t phy_fw_size)
{
        int offset;

        /* At offset 0x8 you're looking for the primary image's
         * starting offset which is 3 Bytes wide
         *
         * At offset 0xa of the primary image, you look for the offset
         * of the DRAM segment which is 3 Bytes wide.
         *
         * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
         * wide
         */
        #define be16(__p) (((__p)[0] << 8) | (__p)[1])
        #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
        #define le24(__p) (le16(__p) | ((__p)[2] << 16))

        offset = le24(phy_fw_data + 0x8) << 12;
        offset = le24(phy_fw_data + offset + 0xa);
        return be16(phy_fw_data + offset + 0x27e);

        #undef be16
        #undef le16
        #undef le24
}

static struct info_10gbt_phy_fw {
        unsigned int phy_fw_id;         /* PCI Device ID */
        char *phy_fw_file;              /* /lib/firmware/ PHY Firmware file */
        int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
        int phy_flash;                  /* Has FLASH for PHY Firmware */
} phy_info_array[] = {
        {
                PHY_AQ1202_DEVICEID,
                PHY_AQ1202_FIRMWARE,
                phy_aq1202_version,
                1,
        },
        {
                PHY_BCM84834_DEVICEID,
                PHY_BCM84834_FIRMWARE,
                NULL,
                0,
        },
        { 0, NULL, NULL },
};