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8#ifndef _SUNHME_H
9#define _SUNHME_H
10
11#include <linux/pci.h>
12
13
14#define GREG_SWRESET 0x000UL
15#define GREG_CFG 0x004UL
16#define GREG_STAT 0x108UL
17#define GREG_IMASK 0x10cUL
18#define GREG_REG_SIZE 0x110UL
19
20
21#define GREG_RESET_ETX 0x01
22#define GREG_RESET_ERX 0x02
23#define GREG_RESET_ALL 0x03
24
25
26#define GREG_CFG_BURSTMSK 0x03
27#define GREG_CFG_BURST16 0x00
28#define GREG_CFG_BURST32 0x01
29#define GREG_CFG_BURST64 0x02
30#define GREG_CFG_64BIT 0x04
31#define GREG_CFG_PARITY 0x08
32#define GREG_CFG_RESV 0x10
33
34
35#define GREG_STAT_GOTFRAME 0x00000001
36#define GREG_STAT_RCNTEXP 0x00000002
37#define GREG_STAT_ACNTEXP 0x00000004
38#define GREG_STAT_CCNTEXP 0x00000008
39#define GREG_STAT_LCNTEXP 0x00000010
40#define GREG_STAT_RFIFOVF 0x00000020
41#define GREG_STAT_CVCNTEXP 0x00000040
42#define GREG_STAT_STSTERR 0x00000080
43#define GREG_STAT_SENTFRAME 0x00000100
44#define GREG_STAT_TFIFO_UND 0x00000200
45#define GREG_STAT_MAXPKTERR 0x00000400
46#define GREG_STAT_NCNTEXP 0x00000800
47#define GREG_STAT_ECNTEXP 0x00001000
48#define GREG_STAT_LCCNTEXP 0x00002000
49#define GREG_STAT_FCNTEXP 0x00004000
50#define GREG_STAT_DTIMEXP 0x00008000
51#define GREG_STAT_RXTOHOST 0x00010000
52#define GREG_STAT_NORXD 0x00020000
53#define GREG_STAT_RXERR 0x00040000
54#define GREG_STAT_RXLATERR 0x00080000
55#define GREG_STAT_RXPERR 0x00100000
56#define GREG_STAT_RXTERR 0x00200000
57#define GREG_STAT_EOPERR 0x00400000
58#define GREG_STAT_MIFIRQ 0x00800000
59#define GREG_STAT_HOSTTOTX 0x01000000
60#define GREG_STAT_TXALL 0x02000000
61#define GREG_STAT_TXEACK 0x04000000
62#define GREG_STAT_TXLERR 0x08000000
63#define GREG_STAT_TXPERR 0x10000000
64#define GREG_STAT_TXTERR 0x20000000
65#define GREG_STAT_SLVERR 0x40000000
66#define GREG_STAT_SLVPERR 0x80000000
67
68
69#define GREG_STAT_ERRORS 0xfc7efefc
70
71
72#define GREG_IMASK_GOTFRAME 0x00000001
73#define GREG_IMASK_RCNTEXP 0x00000002
74#define GREG_IMASK_ACNTEXP 0x00000004
75#define GREG_IMASK_CCNTEXP 0x00000008
76#define GREG_IMASK_LCNTEXP 0x00000010
77#define GREG_IMASK_RFIFOVF 0x00000020
78#define GREG_IMASK_CVCNTEXP 0x00000040
79#define GREG_IMASK_STSTERR 0x00000080
80#define GREG_IMASK_SENTFRAME 0x00000100
81#define GREG_IMASK_TFIFO_UND 0x00000200
82#define GREG_IMASK_MAXPKTERR 0x00000400
83#define GREG_IMASK_NCNTEXP 0x00000800
84#define GREG_IMASK_ECNTEXP 0x00001000
85#define GREG_IMASK_LCCNTEXP 0x00002000
86#define GREG_IMASK_FCNTEXP 0x00004000
87#define GREG_IMASK_DTIMEXP 0x00008000
88#define GREG_IMASK_RXTOHOST 0x00010000
89#define GREG_IMASK_NORXD 0x00020000
90#define GREG_IMASK_RXERR 0x00040000
91#define GREG_IMASK_RXLATERR 0x00080000
92#define GREG_IMASK_RXPERR 0x00100000
93#define GREG_IMASK_RXTERR 0x00200000
94#define GREG_IMASK_EOPERR 0x00400000
95#define GREG_IMASK_MIFIRQ 0x00800000
96#define GREG_IMASK_HOSTTOTX 0x01000000
97#define GREG_IMASK_TXALL 0x02000000
98#define GREG_IMASK_TXEACK 0x04000000
99#define GREG_IMASK_TXLERR 0x08000000
100#define GREG_IMASK_TXPERR 0x10000000
101#define GREG_IMASK_TXTERR 0x20000000
102#define GREG_IMASK_SLVERR 0x40000000
103#define GREG_IMASK_SLVPERR 0x80000000
104
105
106#define ETX_PENDING 0x00UL
107#define ETX_CFG 0x04UL
108#define ETX_RING 0x08UL
109#define ETX_BBASE 0x0cUL
110#define ETX_BDISP 0x10UL
111#define ETX_FIFOWPTR 0x14UL
112#define ETX_FIFOSWPTR 0x18UL
113#define ETX_FIFORPTR 0x1cUL
114#define ETX_FIFOSRPTR 0x20UL
115#define ETX_FIFOPCNT 0x24UL
116#define ETX_SMACHINE 0x28UL
117#define ETX_RSIZE 0x2cUL
118#define ETX_BPTR 0x30UL
119#define ETX_REG_SIZE 0x34UL
120
121
122#define ETX_TP_DMAWAKEUP 0x00000001
123
124
125#define ETX_CFG_DMAENABLE 0x00000001
126#define ETX_CFG_FIFOTHRESH 0x000003fe
127#define ETX_CFG_IRQDAFTER 0x00000400
128#define ETX_CFG_IRQDBEFORE 0x00000000
129
130#define ETX_RSIZE_SHIFT 4
131
132
133#define ERX_CFG 0x00UL
134#define ERX_RING 0x04UL
135#define ERX_BPTR 0x08UL
136#define ERX_FIFOWPTR 0x0cUL
137#define ERX_FIFOSWPTR 0x10UL
138#define ERX_FIFORPTR 0x14UL
139#define ERX_FIFOSRPTR 0x18UL
140#define ERX_SMACHINE 0x1cUL
141#define ERX_REG_SIZE 0x20UL
142
143
144#define ERX_CFG_DMAENABLE 0x00000001
145#define ERX_CFG_RESV1 0x00000006
146#define ERX_CFG_BYTEOFFSET 0x00000038
147#define ERX_CFG_RESV2 0x000001c0
148#define ERX_CFG_SIZE32 0x00000000
149#define ERX_CFG_SIZE64 0x00000200
150#define ERX_CFG_SIZE128 0x00000400
151#define ERX_CFG_SIZE256 0x00000600
152#define ERX_CFG_RESV3 0x0000f800
153#define ERX_CFG_CSUMSTART 0x007f0000
154
155
156
157#define BMAC_XIFCFG 0x0000UL
158
159#define BMAC_TXSWRESET 0x208UL
160#define BMAC_TXCFG 0x20cUL
161#define BMAC_IGAP1 0x210UL
162#define BMAC_IGAP2 0x214UL
163#define BMAC_ALIMIT 0x218UL
164#define BMAC_STIME 0x21cUL
165#define BMAC_PLEN 0x220UL
166#define BMAC_PPAT 0x224UL
167#define BMAC_TXSDELIM 0x228UL
168#define BMAC_JSIZE 0x22cUL
169#define BMAC_TXMAX 0x230UL
170#define BMAC_TXMIN 0x234UL
171#define BMAC_PATTEMPT 0x238UL
172#define BMAC_DTCTR 0x23cUL
173#define BMAC_NCCTR 0x240UL
174#define BMAC_FCCTR 0x244UL
175#define BMAC_EXCTR 0x248UL
176#define BMAC_LTCTR 0x24cUL
177#define BMAC_RSEED 0x250UL
178#define BMAC_TXSMACHINE 0x254UL
179
180#define BMAC_RXSWRESET 0x308UL
181#define BMAC_RXCFG 0x30cUL
182#define BMAC_RXMAX 0x310UL
183#define BMAC_RXMIN 0x314UL
184#define BMAC_MACADDR2 0x318UL
185#define BMAC_MACADDR1 0x31cUL
186#define BMAC_MACADDR0 0x320UL
187#define BMAC_FRCTR 0x324UL
188#define BMAC_GLECTR 0x328UL
189#define BMAC_UNALECTR 0x32cUL
190#define BMAC_RCRCECTR 0x330UL
191#define BMAC_RXSMACHINE 0x334UL
192#define BMAC_RXCVALID 0x338UL
193
194#define BMAC_HTABLE3 0x340UL
195#define BMAC_HTABLE2 0x344UL
196#define BMAC_HTABLE1 0x348UL
197#define BMAC_HTABLE0 0x34cUL
198#define BMAC_AFILTER2 0x350UL
199#define BMAC_AFILTER1 0x354UL
200#define BMAC_AFILTER0 0x358UL
201#define BMAC_AFMASK 0x35cUL
202#define BMAC_REG_SIZE 0x360UL
203
204
205#define BIGMAC_XCFG_ODENABLE 0x00000001
206#define BIGMAC_XCFG_XLBACK 0x00000002
207#define BIGMAC_XCFG_MLBACK 0x00000004
208#define BIGMAC_XCFG_MIIDISAB 0x00000008
209#define BIGMAC_XCFG_SQENABLE 0x00000010
210#define BIGMAC_XCFG_SQETWIN 0x000003e0
211#define BIGMAC_XCFG_LANCE 0x00000010
212#define BIGMAC_XCFG_LIPG0 0x000003e0
213
214
215#define BIGMAC_TXCFG_ENABLE 0x00000001
216#define BIGMAC_TXCFG_SMODE 0x00000020
217#define BIGMAC_TXCFG_CIGN 0x00000040
218#define BIGMAC_TXCFG_FCSOFF 0x00000080
219#define BIGMAC_TXCFG_DBACKOFF 0x00000100
220#define BIGMAC_TXCFG_FULLDPLX 0x00000200
221#define BIGMAC_TXCFG_DGIVEUP 0x00000400
222
223
224#define BIGMAC_RXCFG_ENABLE 0x00000001
225#define BIGMAC_RXCFG_PSTRIP 0x00000020
226#define BIGMAC_RXCFG_PMISC 0x00000040
227#define BIGMAC_RXCFG_DERR 0x00000080
228#define BIGMAC_RXCFG_DCRCS 0x00000100
229#define BIGMAC_RXCFG_REJME 0x00000200
230#define BIGMAC_RXCFG_PGRP 0x00000400
231#define BIGMAC_RXCFG_HENABLE 0x00000800
232#define BIGMAC_RXCFG_AENABLE 0x00001000
233
234
235#define TCVR_BBCLOCK 0x00UL
236#define TCVR_BBDATA 0x04UL
237#define TCVR_BBOENAB 0x08UL
238#define TCVR_FRAME 0x0cUL
239#define TCVR_CFG 0x10UL
240#define TCVR_IMASK 0x14UL
241#define TCVR_STATUS 0x18UL
242#define TCVR_SMACHINE 0x1cUL
243#define TCVR_REG_SIZE 0x20UL
244
245
246#define FRAME_WRITE 0x50020000
247#define FRAME_READ 0x60020000
248
249
250#define TCV_CFG_PSELECT 0x00000001
251#define TCV_CFG_PENABLE 0x00000002
252#define TCV_CFG_BENABLE 0x00000004
253#define TCV_CFG_PREGADDR 0x000000f8
254#define TCV_CFG_MDIO0 0x00000100
255#define TCV_CFG_MDIO1 0x00000200
256#define TCV_CFG_PDADDR 0x00007c00
257
258
259#define TCV_PADDR_ETX 0
260#define TCV_PADDR_ITX 1
261
262
263#define TCV_STAT_BASIC 0xffff0000
264#define TCV_STAT_NORMAL 0x0000ffff
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280
281#define DP83840_CSCONFIG 0x17
282
283
284#define CSCONFIG_RESV1 0x0001
285#define CSCONFIG_LED4 0x0002
286#define CSCONFIG_LED1 0x0004
287#define CSCONFIG_RESV2 0x0008
288#define CSCONFIG_TCVDISAB 0x0010
289#define CSCONFIG_DFBYPASS 0x0020
290#define CSCONFIG_GLFORCE 0x0040
291#define CSCONFIG_CLKTRISTATE 0x0080
292#define CSCONFIG_RESV3 0x0700
293#define CSCONFIG_ENCODE 0x0800
294#define CSCONFIG_RENABLE 0x1000
295#define CSCONFIG_TCDISABLE 0x2000
296#define CSCONFIG_RESV4 0x4000
297#define CSCONFIG_NDISABLE 0x8000
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304
305typedef u32 __bitwise__ hme32;
306
307struct happy_meal_rxd {
308 hme32 rx_flags;
309 hme32 rx_addr;
310};
311
312#define RXFLAG_OWN 0x80000000
313#define RXFLAG_OVERFLOW 0x40000000
314#define RXFLAG_SIZE 0x3fff0000
315#define RXFLAG_CSUM 0x0000ffff
316
317struct happy_meal_txd {
318 hme32 tx_flags;
319 hme32 tx_addr;
320};
321
322#define TXFLAG_OWN 0x80000000
323#define TXFLAG_SOP 0x40000000
324#define TXFLAG_EOP 0x20000000
325#define TXFLAG_CSENABLE 0x10000000
326#define TXFLAG_CSLOCATION 0x0ff00000
327#define TXFLAG_CSBUFBEGIN 0x000fc000
328#define TXFLAG_SIZE 0x00003fff
329
330#define TX_RING_SIZE 32
331#define RX_RING_SIZE 32
332
333#if (TX_RING_SIZE < 16 || TX_RING_SIZE > 256 || (TX_RING_SIZE % 16) != 0)
334#error TX_RING_SIZE holds illegal value
335#endif
336
337#define TX_RING_MAXSIZE 256
338#define RX_RING_MAXSIZE 256
339
340
341#if (RX_RING_SIZE == 32)
342#define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE32|((14/2)<<16))
343#else
344#if (RX_RING_SIZE == 64)
345#define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE64|((14/2)<<16))
346#else
347#if (RX_RING_SIZE == 128)
348#define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE128|((14/2)<<16))
349#else
350#if (RX_RING_SIZE == 256)
351#define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE256|((14/2)<<16))
352#else
353#error RX_RING_SIZE holds illegal value
354#endif
355#endif
356#endif
357#endif
358
359#define NEXT_RX(num) (((num) + 1) & (RX_RING_SIZE - 1))
360#define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))
361#define PREV_RX(num) (((num) - 1) & (RX_RING_SIZE - 1))
362#define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))
363
364#define TX_BUFFS_AVAIL(hp) \
365 (((hp)->tx_old <= (hp)->tx_new) ? \
366 (hp)->tx_old + (TX_RING_SIZE - 1) - (hp)->tx_new : \
367 (hp)->tx_old - (hp)->tx_new - 1)
368
369#define RX_OFFSET 2
370#define RX_BUF_ALLOC_SIZE (1546 + RX_OFFSET + 64)
371
372#define RX_COPY_THRESHOLD 256
373
374struct hmeal_init_block {
375 struct happy_meal_rxd happy_meal_rxd[RX_RING_MAXSIZE];
376 struct happy_meal_txd happy_meal_txd[TX_RING_MAXSIZE];
377};
378
379#define hblock_offset(mem, elem) \
380((__u32)((unsigned long)(&(((struct hmeal_init_block *)0)->mem[elem]))))
381
382
383enum happy_transceiver {
384 external = 0,
385 internal = 1,
386 none = 2,
387};
388
389
390enum happy_timer_state {
391 arbwait = 0,
392 lupwait = 1,
393 ltrywait = 2,
394 asleep = 3,
395};
396
397struct quattro;
398
399
400struct happy_meal {
401 void __iomem *gregs;
402 struct hmeal_init_block *happy_block;
403
404#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
405 u32 (*read_desc32)(hme32 *);
406 void (*write_txd)(struct happy_meal_txd *, u32, u32);
407 void (*write_rxd)(struct happy_meal_rxd *, u32, u32);
408#endif
409
410
411 void *happy_dev;
412 struct device *dma_dev;
413
414 spinlock_t happy_lock;
415
416 struct sk_buff *rx_skbs[RX_RING_SIZE];
417 struct sk_buff *tx_skbs[TX_RING_SIZE];
418
419 int rx_new, tx_new, rx_old, tx_old;
420
421 struct net_device_stats net_stats;
422
423#if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
424 u32 (*read32)(void __iomem *);
425 void (*write32)(void __iomem *, u32);
426#endif
427
428 void __iomem *etxregs;
429 void __iomem *erxregs;
430 void __iomem *bigmacregs;
431 void __iomem *tcvregs;
432
433 dma_addr_t hblock_dvma;
434 unsigned int happy_flags;
435 int irq;
436 enum happy_transceiver tcvr_type;
437 unsigned int happy_bursts;
438 unsigned int paddr;
439 unsigned short hm_revision;
440 unsigned short sw_bmcr;
441 unsigned short sw_bmsr;
442 unsigned short sw_physid1;
443 unsigned short sw_physid2;
444 unsigned short sw_advertise;
445 unsigned short sw_lpa;
446 unsigned short sw_expansion;
447 unsigned short sw_csconfig;
448 unsigned int auto_speed;
449 unsigned int forced_speed;
450 unsigned int poll_data;
451 unsigned int poll_flag;
452 unsigned int linkcheck;
453 unsigned int lnkup;
454 unsigned int lnkdown;
455 unsigned int lnkcnt;
456 struct timer_list happy_timer;
457 enum happy_timer_state timer_state;
458 unsigned int timer_ticks;
459
460 struct net_device *dev;
461 struct quattro *qfe_parent;
462 int qfe_ent;
463};
464
465
466#define HFLAG_POLL 0x00000001
467#define HFLAG_FENABLE 0x00000002
468#define HFLAG_LANCE 0x00000004
469#define HFLAG_RXENABLE 0x00000008
470#define HFLAG_AUTO 0x00000010
471#define HFLAG_FULL 0x00000020
472#define HFLAG_MACFULL 0x00000040
473#define HFLAG_POLLENABLE 0x00000080
474#define HFLAG_RXCV 0x00000100
475#define HFLAG_INIT 0x00000200
476#define HFLAG_LINKUP 0x00000400
477#define HFLAG_PCI 0x00000800
478#define HFLAG_QUATTRO 0x00001000
479
480#define HFLAG_20_21 (HFLAG_POLLENABLE | HFLAG_FENABLE)
481#define HFLAG_NOT_A0 (HFLAG_POLLENABLE | HFLAG_FENABLE | HFLAG_LANCE | HFLAG_RXCV)
482
483
484struct quattro {
485 struct net_device *happy_meals[4];
486
487
488 void *quattro_dev;
489
490 struct quattro *next;
491
492
493#ifdef CONFIG_SBUS
494 struct linux_prom_ranges ranges[8];
495#endif
496 int nranges;
497};
498
499
500#define ALIGNED_RX_SKB_ADDR(addr) \
501 ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
502#define happy_meal_alloc_skb(__length, __gfp_flags) \
503({ struct sk_buff *__skb; \
504 __skb = alloc_skb((__length) + 64, (__gfp_flags)); \
505 if(__skb) { \
506 int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \
507 if(__offset) \
508 skb_reserve(__skb, __offset); \
509 } \
510 __skb; \
511})
512
513#endif
514