1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33#ifndef RT2800_H
34#define RT2800_H
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59#define RF2820 0x0001
60#define RF2850 0x0002
61#define RF2720 0x0003
62#define RF2750 0x0004
63#define RF3020 0x0005
64#define RF2020 0x0006
65#define RF3021 0x0007
66#define RF3022 0x0008
67#define RF3052 0x0009
68#define RF2853 0x000a
69#define RF3320 0x000b
70#define RF3322 0x000c
71#define RF3053 0x000d
72#define RF5592 0x000f
73#define RF3070 0x3070
74#define RF3290 0x3290
75#define RF5360 0x5360
76#define RF5362 0x5362
77#define RF5370 0x5370
78#define RF5372 0x5372
79#define RF5390 0x5390
80#define RF5392 0x5392
81
82
83
84
85#define REV_RT2860C 0x0100
86#define REV_RT2860D 0x0101
87#define REV_RT2872E 0x0200
88#define REV_RT3070E 0x0200
89#define REV_RT3070F 0x0201
90#define REV_RT3071E 0x0211
91#define REV_RT3090E 0x0211
92#define REV_RT3390E 0x0211
93#define REV_RT3593E 0x0211
94#define REV_RT5390F 0x0502
95#define REV_RT5390R 0x1502
96#define REV_RT5592C 0x0221
97
98#define DEFAULT_RSSI_OFFSET 120
99
100
101
102
103#define CSR_REG_BASE 0x1000
104#define CSR_REG_SIZE 0x0800
105#define EEPROM_BASE 0x0000
106#define EEPROM_SIZE 0x0200
107#define BBP_BASE 0x0000
108#define BBP_SIZE 0x00ff
109#define RF_BASE 0x0004
110#define RF_SIZE 0x0010
111#define RFCSR_BASE 0x0000
112#define RFCSR_SIZE 0x0040
113
114
115
116
117#define NUM_TX_QUEUES 4
118
119
120
121
122
123
124
125
126
127#define MAC_CSR0_3290 0x0000
128
129
130
131
132
133
134
135#define E2PROM_CSR 0x0004
136#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
137#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
138#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
139#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
140#define E2PROM_CSR_TYPE FIELD32(0x00000030)
141#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
142#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
143
144
145
146
147#define CMB_CTRL 0x0020
148#define AUX_OPT_BIT0 FIELD32(0x00000001)
149#define AUX_OPT_BIT1 FIELD32(0x00000002)
150#define AUX_OPT_BIT2 FIELD32(0x00000004)
151#define AUX_OPT_BIT3 FIELD32(0x00000008)
152#define AUX_OPT_BIT4 FIELD32(0x00000010)
153#define AUX_OPT_BIT5 FIELD32(0x00000020)
154#define AUX_OPT_BIT6 FIELD32(0x00000040)
155#define AUX_OPT_BIT7 FIELD32(0x00000080)
156#define AUX_OPT_BIT8 FIELD32(0x00000100)
157#define AUX_OPT_BIT9 FIELD32(0x00000200)
158#define AUX_OPT_BIT10 FIELD32(0x00000400)
159#define AUX_OPT_BIT11 FIELD32(0x00000800)
160#define AUX_OPT_BIT12 FIELD32(0x00001000)
161#define AUX_OPT_BIT13 FIELD32(0x00002000)
162#define AUX_OPT_BIT14 FIELD32(0x00004000)
163#define AUX_OPT_BIT15 FIELD32(0x00008000)
164#define LDO25_LEVEL FIELD32(0x00030000)
165#define LDO25_LARGEA FIELD32(0x00040000)
166#define LDO25_FRC_ON FIELD32(0x00080000)
167#define CMB_RSV FIELD32(0x00300000)
168#define XTAL_RDY FIELD32(0x00400000)
169#define PLL_LD FIELD32(0x00800000)
170#define LDO_CORE_LEVEL FIELD32(0x0F000000)
171#define LDO_BGSEL FIELD32(0x30000000)
172#define LDO3_EN FIELD32(0x40000000)
173#define LDO0_EN FIELD32(0x80000000)
174
175
176
177
178#define EFUSE_CTRL_3290 0x0024
179
180
181
182
183#define EFUSE_DATA3_3290 0x0028
184
185
186
187
188#define EFUSE_DATA2_3290 0x002c
189
190
191
192
193#define EFUSE_DATA1_3290 0x0030
194
195
196
197
198#define EFUSE_DATA0_3290 0x0034
199
200
201
202
203
204#define OSC_CTRL 0x0038
205#define OSC_REF_CYCLE FIELD32(0x00001fff)
206#define OSC_RSV FIELD32(0x0000e000)
207#define OSC_CAL_CNT FIELD32(0x0fff0000)
208#define OSC_CAL_ACK FIELD32(0x10000000)
209#define OSC_CLK_32K_VLD FIELD32(0x20000000)
210#define OSC_CAL_REQ FIELD32(0x40000000)
211#define OSC_ROSC_EN FIELD32(0x80000000)
212
213
214
215
216#define COEX_CFG0 0x0040
217#define COEX_CFG_ANT FIELD32(0xff000000)
218
219
220
221#define COEX_CFG1 0x0044
222
223
224
225
226#define COEX_CFG2 0x0048
227#define BT_COEX_CFG1 FIELD32(0xff000000)
228#define BT_COEX_CFG0 FIELD32(0x00ff0000)
229#define WL_COEX_CFG1 FIELD32(0x0000ff00)
230#define WL_COEX_CFG0 FIELD32(0x000000ff)
231
232
233
234
235#define PLL_CTRL 0x0050
236#define PLL_RESERVED_INPUT1 FIELD32(0x000000ff)
237#define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00)
238#define PLL_CONTROL FIELD32(0x00070000)
239#define PLL_LPF_R1 FIELD32(0x00080000)
240#define PLL_LPF_C1_CTRL FIELD32(0x00300000)
241#define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
242#define PLL_CP_CURRENT_CTRL FIELD32(0x03000000)
243#define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000)
244#define PLL_LOCK_CTRL FIELD32(0x70000000)
245#define PLL_VBGBK_EN FIELD32(0x80000000)
246
247
248
249
250
251
252#define WLAN_FUN_CTRL 0x0080
253#define WLAN_EN FIELD32(0x00000001)
254#define WLAN_CLK_EN FIELD32(0x00000002)
255#define WLAN_RSV1 FIELD32(0x00000004)
256#define WLAN_RESET FIELD32(0x00000008)
257#define PCIE_APP0_CLK_REQ FIELD32(0x00000010)
258#define FRC_WL_ANT_SET FIELD32(0x00000020)
259#define INV_TR_SW0 FIELD32(0x00000040)
260#define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100)
261#define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200)
262#define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400)
263#define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800)
264#define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000)
265#define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000)
266#define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000)
267#define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000)
268#define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00)
269#define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000)
270#define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000)
271#define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000)
272#define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000)
273#define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000)
274#define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000)
275#define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000)
276#define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000)
277#define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000)
278#define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000)
279#define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000)
280#define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000)
281#define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000)
282#define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000)
283#define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000)
284#define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000)
285#define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000)
286#define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000)
287
288
289
290
291#define AUX_CTRL 0x10c
292#define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
293#define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
294
295
296
297
298#define OPT_14_CSR 0x0114
299#define OPT_14_CSR_BIT0 FIELD32(0x00000001)
300
301
302
303
304
305
306#define INT_SOURCE_CSR 0x0200
307#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
308#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
309#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
310#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
311#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
312#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
313#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
314#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
315#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
316#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
317#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
318#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
319#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
320#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
321#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
322#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
323#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
324#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
325
326
327
328
329#define INT_MASK_CSR 0x0204
330#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
331#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
332#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
333#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
334#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
335#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
336#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
337#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
338#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
339#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
340#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
341#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
342#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
343#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
344#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
345#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
346#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
347#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
348
349
350
351
352#define WPDMA_GLO_CFG 0x0208
353#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
354#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
355#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
356#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
357#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
358#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
359#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
360#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
361#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
362
363
364
365
366#define WPDMA_RST_IDX 0x020c
367#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
368#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
369#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
370#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
371#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
372#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
373#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
374
375
376
377
378#define DELAY_INT_CFG 0x0210
379#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
380#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
381#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
382#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
383#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
384#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
385
386
387
388
389
390
391
392
393#define WMM_AIFSN_CFG 0x0214
394#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
395#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
396#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
397#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
398
399
400
401
402
403
404
405
406#define WMM_CWMIN_CFG 0x0218
407#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
408#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
409#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
410#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
411
412
413
414
415
416
417
418
419#define WMM_CWMAX_CFG 0x021c
420#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
421#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
422#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
423#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
424
425
426
427
428
429
430#define WMM_TXOP0_CFG 0x0220
431#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
432#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
433
434
435
436
437
438
439#define WMM_TXOP1_CFG 0x0224
440#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
441#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
442
443
444
445
446
447
448#define GPIO_CTRL 0x0228
449#define GPIO_CTRL_VAL0 FIELD32(0x00000001)
450#define GPIO_CTRL_VAL1 FIELD32(0x00000002)
451#define GPIO_CTRL_VAL2 FIELD32(0x00000004)
452#define GPIO_CTRL_VAL3 FIELD32(0x00000008)
453#define GPIO_CTRL_VAL4 FIELD32(0x00000010)
454#define GPIO_CTRL_VAL5 FIELD32(0x00000020)
455#define GPIO_CTRL_VAL6 FIELD32(0x00000040)
456#define GPIO_CTRL_VAL7 FIELD32(0x00000080)
457#define GPIO_CTRL_DIR0 FIELD32(0x00000100)
458#define GPIO_CTRL_DIR1 FIELD32(0x00000200)
459#define GPIO_CTRL_DIR2 FIELD32(0x00000400)
460#define GPIO_CTRL_DIR3 FIELD32(0x00000800)
461#define GPIO_CTRL_DIR4 FIELD32(0x00001000)
462#define GPIO_CTRL_DIR5 FIELD32(0x00002000)
463#define GPIO_CTRL_DIR6 FIELD32(0x00004000)
464#define GPIO_CTRL_DIR7 FIELD32(0x00008000)
465#define GPIO_CTRL_VAL8 FIELD32(0x00010000)
466#define GPIO_CTRL_VAL9 FIELD32(0x00020000)
467#define GPIO_CTRL_VAL10 FIELD32(0x00040000)
468#define GPIO_CTRL_DIR8 FIELD32(0x01000000)
469#define GPIO_CTRL_DIR9 FIELD32(0x02000000)
470#define GPIO_CTRL_DIR10 FIELD32(0x04000000)
471
472
473
474
475#define MCU_CMD_CFG 0x022c
476
477
478
479
480#define TX_BASE_PTR0 0x0230
481#define TX_MAX_CNT0 0x0234
482#define TX_CTX_IDX0 0x0238
483#define TX_DTX_IDX0 0x023c
484
485
486
487
488#define TX_BASE_PTR1 0x0240
489#define TX_MAX_CNT1 0x0244
490#define TX_CTX_IDX1 0x0248
491#define TX_DTX_IDX1 0x024c
492
493
494
495
496#define TX_BASE_PTR2 0x0250
497#define TX_MAX_CNT2 0x0254
498#define TX_CTX_IDX2 0x0258
499#define TX_DTX_IDX2 0x025c
500
501
502
503
504#define TX_BASE_PTR3 0x0260
505#define TX_MAX_CNT3 0x0264
506#define TX_CTX_IDX3 0x0268
507#define TX_DTX_IDX3 0x026c
508
509
510
511
512#define TX_BASE_PTR4 0x0270
513#define TX_MAX_CNT4 0x0274
514#define TX_CTX_IDX4 0x0278
515#define TX_DTX_IDX4 0x027c
516
517
518
519
520#define TX_BASE_PTR5 0x0280
521#define TX_MAX_CNT5 0x0284
522#define TX_CTX_IDX5 0x0288
523#define TX_DTX_IDX5 0x028c
524
525
526
527
528#define RX_BASE_PTR 0x0290
529#define RX_MAX_CNT 0x0294
530#define RX_CRX_IDX 0x0298
531#define RX_DRX_IDX 0x029c
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547#define USB_DMA_CFG 0x02a0
548#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
549#define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
550#define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
551#define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
552#define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
553#define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
554#define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
555#define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
556#define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
557#define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
558#define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
559
560
561
562
563
564
565
566#define US_CYC_CNT 0x02a4
567#define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
568#define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
569
570
571
572
573
574#define PBF_SYS_CTRL 0x0400
575#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
576#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
577
578
579
580
581#define HOST_CMD_CSR 0x0404
582#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
583
584
585
586
587
588#define PBF_CFG 0x0408
589#define PBF_MAX_PCNT 0x040c
590#define PBF_CTRL 0x0410
591#define PBF_INT_STA 0x0414
592#define PBF_INT_ENA 0x0418
593
594
595
596
597#define BCN_OFFSET0 0x042c
598#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
599#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
600#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
601#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
602
603
604
605
606#define BCN_OFFSET1 0x0430
607#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
608#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
609#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
610#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
611
612
613
614
615
616
617
618
619#define TXRXQ_PCNT 0x0438
620#define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
621#define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
622#define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
623#define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
624
625
626
627
628
629#define PBF_DBG 0x043c
630
631
632
633
634#define RF_CSR_CFG 0x0500
635#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
636#define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
637#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
638#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
639
640
641
642
643#define EFUSE_CTRL 0x0580
644#define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
645#define EFUSE_CTRL_MODE FIELD32(0x000000c0)
646#define EFUSE_CTRL_KICK FIELD32(0x40000000)
647#define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
648
649
650
651
652#define EFUSE_DATA0 0x0590
653
654
655
656
657#define EFUSE_DATA1 0x0594
658
659
660
661
662#define EFUSE_DATA2 0x0598
663
664
665
666
667#define EFUSE_DATA3 0x059c
668
669
670
671
672#define LDO_CFG0 0x05d4
673#define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
674#define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
675#define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
676#define LDO_CFG0_BGSEL FIELD32(0x03000000)
677#define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
678#define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
679#define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
680
681
682
683
684#define GPIO_SWITCH 0x05dc
685#define GPIO_SWITCH_0 FIELD32(0x00000001)
686#define GPIO_SWITCH_1 FIELD32(0x00000002)
687#define GPIO_SWITCH_2 FIELD32(0x00000004)
688#define GPIO_SWITCH_3 FIELD32(0x00000008)
689#define GPIO_SWITCH_4 FIELD32(0x00000010)
690#define GPIO_SWITCH_5 FIELD32(0x00000020)
691#define GPIO_SWITCH_6 FIELD32(0x00000040)
692#define GPIO_SWITCH_7 FIELD32(0x00000080)
693
694
695
696
697#define MAC_DEBUG_INDEX 0x05e8
698#define MAC_DEBUG_INDEX_XTAL FIELD32(0x80000000)
699
700
701
702
703
704
705
706
707
708
709
710#define MAC_CSR0 0x1000
711#define MAC_CSR0_REVISION FIELD32(0x0000ffff)
712#define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
713
714
715
716
717#define MAC_SYS_CTRL 0x1004
718#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
719#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
720#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
721#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
722#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
723#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
724#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
725#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
726
727
728
729
730#define MAC_ADDR_DW0 0x1008
731#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
732#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
733#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
734#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
735
736
737
738
739
740
741
742
743
744#define MAC_ADDR_DW1 0x100c
745#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
746#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
747#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
748
749
750
751
752#define MAC_BSSID_DW0 0x1010
753#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
754#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
755#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
756#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
757
758
759
760
761
762
763
764
765
766
767
768
769#define MAC_BSSID_DW1 0x1014
770#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
771#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
772#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
773#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
774
775
776
777
778
779
780
781#define MAX_LEN_CFG 0x1018
782#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
783#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
784#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
785#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
786
787
788
789
790
791
792
793
794
795
796#define BBP_CSR_CFG 0x101c
797#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
798#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
799#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
800#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
801#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
802#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
803
804
805
806
807
808
809
810
811
812#define RF_CSR_CFG0 0x1020
813#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
814#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
815#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
816#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
817#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
818#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
819
820
821
822
823
824
825
826
827#define RF_CSR_CFG1 0x1024
828#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
829#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
830
831
832
833
834
835#define RF_CSR_CFG2 0x1028
836#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852#define LED_CFG 0x102c
853#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
854#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
855#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
856#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
857#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
858#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
859#define LED_CFG_LED_POLAR FIELD32(0x40000000)
860
861
862
863
864
865
866
867
868
869#define AMPDU_BA_WINSIZE 0x1040
870#define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
871#define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
872
873
874
875
876
877
878
879
880
881
882
883#define XIFS_TIME_CFG 0x1100
884#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
885#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
886#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
887#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
888#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
889
890
891
892
893#define BKOFF_SLOT_CFG 0x1104
894#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
895#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
896
897
898
899
900#define NAV_TIME_CFG 0x1108
901#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
902#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
903#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
904#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
905
906
907
908
909
910
911
912
913
914#define CH_TIME_CFG 0x110c
915#define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
916#define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
917#define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
918#define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
919#define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
920
921
922
923
924#define PBF_LIFE_TIMER 0x1110
925
926
927
928
929
930
931
932
933#define BCN_TIME_CFG 0x1114
934#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
935#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
936#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
937#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
938#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
939#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
940
941
942
943
944
945
946#define TBTT_SYNC_CFG 0x1118
947#define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
948#define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
949#define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
950#define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
951
952
953
954
955#define TSF_TIMER_DW0 0x111c
956#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
957
958
959
960
961#define TSF_TIMER_DW1 0x1120
962#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
963
964
965
966
967#define TBTT_TIMER 0x1124
968
969
970
971
972
973
974#define INT_TIMER_CFG 0x1128
975#define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
976#define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
977
978
979
980
981#define INT_TIMER_EN 0x112c
982#define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
983#define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
984
985
986
987
988#define CH_IDLE_STA 0x1130
989
990
991
992
993#define CH_BUSY_STA 0x1134
994
995
996
997
998#define CH_BUSY_STA_SEC 0x1138
999
1000
1001
1002
1003
1004
1005#define MAC_STATUS_CFG 0x1200
1006#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
1007
1008
1009
1010
1011#define PWR_PIN_CFG 0x1204
1012
1013
1014
1015
1016
1017
1018#define AUTOWAKEUP_CFG 0x1208
1019#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
1020#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
1021#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
1022
1023
1024
1025
1026#define EDCA_AC0_CFG 0x1300
1027#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
1028#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
1029#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
1030#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
1031
1032
1033
1034
1035#define EDCA_AC1_CFG 0x1304
1036#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
1037#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
1038#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
1039#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
1040
1041
1042
1043
1044#define EDCA_AC2_CFG 0x1308
1045#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
1046#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
1047#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
1048#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
1049
1050
1051
1052
1053#define EDCA_AC3_CFG 0x130c
1054#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
1055#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
1056#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
1057#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
1058
1059
1060
1061
1062#define EDCA_TID_AC_MAP 0x1310
1063
1064
1065
1066
1067#define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
1068#define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
1069#define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
1070#define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
1071#define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
1072#define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
1073#define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
1074#define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
1075
1076
1077
1078
1079#define TX_PWR_CFG_0 0x1314
1080#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
1081#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
1082#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
1083#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
1084#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
1085#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
1086#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
1087#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
1088
1089#define TX_PWR_CFG_0_CCK1_CH0 FIELD32(0x0000000f)
1090#define TX_PWR_CFG_0_CCK1_CH1 FIELD32(0x000000f0)
1091#define TX_PWR_CFG_0_CCK5_CH0 FIELD32(0x00000f00)
1092#define TX_PWR_CFG_0_CCK5_CH1 FIELD32(0x0000f000)
1093#define TX_PWR_CFG_0_OFDM6_CH0 FIELD32(0x000f0000)
1094#define TX_PWR_CFG_0_OFDM6_CH1 FIELD32(0x00f00000)
1095#define TX_PWR_CFG_0_OFDM12_CH0 FIELD32(0x0f000000)
1096#define TX_PWR_CFG_0_OFDM12_CH1 FIELD32(0xf0000000)
1097
1098
1099
1100
1101#define TX_PWR_CFG_1 0x1318
1102#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
1103#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
1104#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
1105#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
1106#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
1107#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
1108#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
1109#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
1110
1111#define TX_PWR_CFG_1_OFDM24_CH0 FIELD32(0x0000000f)
1112#define TX_PWR_CFG_1_OFDM24_CH1 FIELD32(0x000000f0)
1113#define TX_PWR_CFG_1_OFDM48_CH0 FIELD32(0x00000f00)
1114#define TX_PWR_CFG_1_OFDM48_CH1 FIELD32(0x0000f000)
1115#define TX_PWR_CFG_1_MCS0_CH0 FIELD32(0x000f0000)
1116#define TX_PWR_CFG_1_MCS0_CH1 FIELD32(0x00f00000)
1117#define TX_PWR_CFG_1_MCS2_CH0 FIELD32(0x0f000000)
1118#define TX_PWR_CFG_1_MCS2_CH1 FIELD32(0xf0000000)
1119
1120
1121
1122
1123#define TX_PWR_CFG_2 0x131c
1124#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
1125#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
1126#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
1127#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
1128#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
1129#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
1130#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
1131#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
1132
1133#define TX_PWR_CFG_2_MCS4_CH0 FIELD32(0x0000000f)
1134#define TX_PWR_CFG_2_MCS4_CH1 FIELD32(0x000000f0)
1135#define TX_PWR_CFG_2_MCS6_CH0 FIELD32(0x00000f00)
1136#define TX_PWR_CFG_2_MCS6_CH1 FIELD32(0x0000f000)
1137#define TX_PWR_CFG_2_MCS8_CH0 FIELD32(0x000f0000)
1138#define TX_PWR_CFG_2_MCS8_CH1 FIELD32(0x00f00000)
1139#define TX_PWR_CFG_2_MCS10_CH0 FIELD32(0x0f000000)
1140#define TX_PWR_CFG_2_MCS10_CH1 FIELD32(0xf0000000)
1141
1142
1143
1144
1145#define TX_PWR_CFG_3 0x1320
1146#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
1147#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
1148#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
1149#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
1150#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
1151#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
1152#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
1153#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
1154
1155#define TX_PWR_CFG_3_MCS12_CH0 FIELD32(0x0000000f)
1156#define TX_PWR_CFG_3_MCS12_CH1 FIELD32(0x000000f0)
1157#define TX_PWR_CFG_3_MCS14_CH0 FIELD32(0x00000f00)
1158#define TX_PWR_CFG_3_MCS14_CH1 FIELD32(0x0000f000)
1159#define TX_PWR_CFG_3_STBC0_CH0 FIELD32(0x000f0000)
1160#define TX_PWR_CFG_3_STBC0_CH1 FIELD32(0x00f00000)
1161#define TX_PWR_CFG_3_STBC2_CH0 FIELD32(0x0f000000)
1162#define TX_PWR_CFG_3_STBC2_CH1 FIELD32(0xf0000000)
1163
1164
1165
1166
1167#define TX_PWR_CFG_4 0x1324
1168#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
1169#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
1170#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
1171#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
1172
1173#define TX_PWR_CFG_3_STBC4_CH0 FIELD32(0x0000000f)
1174#define TX_PWR_CFG_3_STBC4_CH1 FIELD32(0x000000f0)
1175#define TX_PWR_CFG_3_STBC6_CH0 FIELD32(0x00000f00)
1176#define TX_PWR_CFG_3_STBC6_CH1 FIELD32(0x0000f000)
1177
1178
1179
1180
1181#define TX_PIN_CFG 0x1328
1182#define TX_PIN_CFG_PA_PE_DISABLE 0xfcfffff0
1183#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
1184#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
1185#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
1186#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
1187#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
1188#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
1189#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
1190#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
1191#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
1192#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
1193#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
1194#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
1195#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
1196#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
1197#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
1198#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
1199#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
1200#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
1201#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
1202#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
1203#define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
1204#define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
1205#define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
1206#define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000)
1207#define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000)
1208#define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000)
1209#define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000)
1210#define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000)
1211
1212
1213
1214
1215#define TX_BAND_CFG 0x132c
1216#define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
1217#define TX_BAND_CFG_A FIELD32(0x00000002)
1218#define TX_BAND_CFG_BG FIELD32(0x00000004)
1219
1220
1221
1222
1223#define TX_SW_CFG0 0x1330
1224
1225
1226
1227
1228#define TX_SW_CFG1 0x1334
1229
1230
1231
1232
1233#define TX_SW_CFG2 0x1338
1234
1235
1236
1237
1238#define TXOP_THRES_CFG 0x133c
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256#define TXOP_CTRL_CFG 0x1340
1257#define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
1258#define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
1259#define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1260#define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1261#define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
1262#define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
1263#define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
1264#define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
1265#define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
1266#define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
1267
1268
1269
1270
1271
1272
1273#define TX_RTS_CFG 0x1344
1274#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1275#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
1276#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286#define TX_TIMEOUT_CFG 0x1348
1287#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
1288#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
1289#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302#define TX_RTY_CFG 0x134c
1303#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
1304#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
1305#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
1306#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
1307#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
1308#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322#define TX_LINK_CFG 0x1350
1323#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1324#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
1325#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1326#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1327#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1328#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1329#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1330#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1331
1332
1333
1334
1335#define HT_FBK_CFG0 0x1354
1336#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1337#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1338#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1339#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1340#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1341#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1342#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1343#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1344
1345
1346
1347
1348#define HT_FBK_CFG1 0x1358
1349#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1350#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1351#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1352#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1353#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1354#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1355#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1356#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1357
1358
1359
1360
1361#define LG_FBK_CFG0 0x135c
1362#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1363#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1364#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1365#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1366#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1367#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1368#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1369#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1370
1371
1372
1373
1374#define LG_FBK_CFG1 0x1360
1375#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1376#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1377#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1378#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395#define CCK_PROT_CFG 0x1364
1396#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1397#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1398#define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1399#define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1400#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1401#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1402#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1403#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1404#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1405#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1406#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1407
1408
1409
1410
1411#define OFDM_PROT_CFG 0x1368
1412#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1413#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1414#define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1415#define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1416#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1417#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1418#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1419#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1420#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1421#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1422#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1423
1424
1425
1426
1427#define MM20_PROT_CFG 0x136c
1428#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1429#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1430#define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1431#define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1432#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1433#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1434#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1435#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1436#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1437#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1438#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1439
1440
1441
1442
1443#define MM40_PROT_CFG 0x1370
1444#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1445#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1446#define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1447#define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1448#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1449#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1450#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1451#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1452#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1453#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1454#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1455
1456
1457
1458
1459#define GF20_PROT_CFG 0x1374
1460#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1461#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1462#define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1463#define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1464#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1465#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1466#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1467#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1468#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1469#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1470#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1471
1472
1473
1474
1475#define GF40_PROT_CFG 0x1378
1476#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1477#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1478#define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1479#define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1480#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1481#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1482#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1483#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1484#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1485#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1486#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1487
1488
1489
1490
1491#define EXP_CTS_TIME 0x137c
1492
1493
1494
1495
1496#define EXP_ACK_TIME 0x1380
1497
1498
1499#define TX_PWR_CFG_5 0x1384
1500#define TX_PWR_CFG_5_MCS16_CH0 FIELD32(0x0000000f)
1501#define TX_PWR_CFG_5_MCS16_CH1 FIELD32(0x000000f0)
1502#define TX_PWR_CFG_5_MCS16_CH2 FIELD32(0x00000f00)
1503#define TX_PWR_CFG_5_MCS18_CH0 FIELD32(0x000f0000)
1504#define TX_PWR_CFG_5_MCS18_CH1 FIELD32(0x00f00000)
1505#define TX_PWR_CFG_5_MCS18_CH2 FIELD32(0x0f000000)
1506
1507
1508#define TX_PWR_CFG_6 0x1388
1509#define TX_PWR_CFG_6_MCS20_CH0 FIELD32(0x0000000f)
1510#define TX_PWR_CFG_6_MCS20_CH1 FIELD32(0x000000f0)
1511#define TX_PWR_CFG_6_MCS20_CH2 FIELD32(0x00000f00)
1512#define TX_PWR_CFG_6_MCS22_CH0 FIELD32(0x000f0000)
1513#define TX_PWR_CFG_6_MCS22_CH1 FIELD32(0x00f00000)
1514#define TX_PWR_CFG_6_MCS22_CH2 FIELD32(0x0f000000)
1515
1516
1517#define TX_PWR_CFG_0_EXT 0x1390
1518#define TX_PWR_CFG_0_EXT_CCK1_CH2 FIELD32(0x0000000f)
1519#define TX_PWR_CFG_0_EXT_CCK5_CH2 FIELD32(0x00000f00)
1520#define TX_PWR_CFG_0_EXT_OFDM6_CH2 FIELD32(0x000f0000)
1521#define TX_PWR_CFG_0_EXT_OFDM12_CH2 FIELD32(0x0f000000)
1522
1523
1524#define TX_PWR_CFG_1_EXT 0x1394
1525#define TX_PWR_CFG_1_EXT_OFDM24_CH2 FIELD32(0x0000000f)
1526#define TX_PWR_CFG_1_EXT_OFDM48_CH2 FIELD32(0x00000f00)
1527#define TX_PWR_CFG_1_EXT_MCS0_CH2 FIELD32(0x000f0000)
1528#define TX_PWR_CFG_1_EXT_MCS2_CH2 FIELD32(0x0f000000)
1529
1530
1531#define TX_PWR_CFG_2_EXT 0x1398
1532#define TX_PWR_CFG_2_EXT_MCS4_CH2 FIELD32(0x0000000f)
1533#define TX_PWR_CFG_2_EXT_MCS6_CH2 FIELD32(0x00000f00)
1534#define TX_PWR_CFG_2_EXT_MCS8_CH2 FIELD32(0x000f0000)
1535#define TX_PWR_CFG_2_EXT_MCS10_CH2 FIELD32(0x0f000000)
1536
1537
1538#define TX_PWR_CFG_3_EXT 0x139c
1539#define TX_PWR_CFG_3_EXT_MCS12_CH2 FIELD32(0x0000000f)
1540#define TX_PWR_CFG_3_EXT_MCS14_CH2 FIELD32(0x00000f00)
1541#define TX_PWR_CFG_3_EXT_STBC0_CH2 FIELD32(0x000f0000)
1542#define TX_PWR_CFG_3_EXT_STBC2_CH2 FIELD32(0x0f000000)
1543
1544
1545#define TX_PWR_CFG_4_EXT 0x13a0
1546#define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f)
1547#define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00)
1548
1549
1550#define TX_PWR_CFG_7 0x13d4
1551#define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f)
1552#define TX_PWR_CFG_7_OFDM54_CH1 FIELD32(0x000000f0)
1553#define TX_PWR_CFG_7_OFDM54_CH2 FIELD32(0x00000f00)
1554#define TX_PWR_CFG_7_MCS7_CH0 FIELD32(0x000f0000)
1555#define TX_PWR_CFG_7_MCS7_CH1 FIELD32(0x00f00000)
1556#define TX_PWR_CFG_7_MCS7_CH2 FIELD32(0x0f000000)
1557
1558
1559#define TX_PWR_CFG_8 0x13d8
1560#define TX_PWR_CFG_8_MCS15_CH0 FIELD32(0x0000000f)
1561#define TX_PWR_CFG_8_MCS15_CH1 FIELD32(0x000000f0)
1562#define TX_PWR_CFG_8_MCS15_CH2 FIELD32(0x00000f00)
1563#define TX_PWR_CFG_8_MCS23_CH0 FIELD32(0x000f0000)
1564#define TX_PWR_CFG_8_MCS23_CH1 FIELD32(0x00f00000)
1565#define TX_PWR_CFG_8_MCS23_CH2 FIELD32(0x0f000000)
1566
1567
1568#define TX_PWR_CFG_9 0x13dc
1569#define TX_PWR_CFG_9_STBC7_CH0 FIELD32(0x0000000f)
1570#define TX_PWR_CFG_9_STBC7_CH1 FIELD32(0x000000f0)
1571#define TX_PWR_CFG_9_STBC7_CH2 FIELD32(0x00000f00)
1572
1573
1574
1575
1576#define RX_FILTER_CFG 0x1400
1577#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1578#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1579#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1580#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1581#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1582#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1583#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1584#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1585#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1586#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1587#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1588#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1589#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1590#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1591#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1592#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1593#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605#define AUTO_RSP_CFG 0x1404
1606#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1607#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1608#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1609#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1610#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1611#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1612#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1613
1614
1615
1616
1617#define LEGACY_BASIC_RATE 0x1408
1618
1619
1620
1621
1622#define HT_BASIC_RATE 0x140c
1623
1624
1625
1626
1627#define HT_CTRL_CFG 0x1410
1628
1629
1630
1631
1632#define SIFS_COST_CFG 0x1414
1633
1634
1635
1636
1637
1638#define RX_PARSER_CFG 0x1418
1639
1640
1641
1642
1643#define TX_SEC_CNT0 0x1500
1644
1645
1646
1647
1648#define RX_SEC_CNT0 0x1504
1649
1650
1651
1652
1653#define CCMP_FC_MUTE 0x1508
1654
1655
1656
1657
1658#define TXOP_HLDR_ADDR0 0x1600
1659
1660
1661
1662
1663#define TXOP_HLDR_ADDR1 0x1604
1664
1665
1666
1667
1668#define TXOP_HLDR_ET 0x1608
1669
1670
1671
1672
1673#define QOS_CFPOLL_RA_DW0 0x160c
1674
1675
1676
1677
1678#define QOS_CFPOLL_RA_DW1 0x1610
1679
1680
1681
1682
1683#define QOS_CFPOLL_QC 0x1614
1684
1685
1686
1687
1688#define RX_STA_CNT0 0x1700
1689#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1690#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1691
1692
1693
1694
1695#define RX_STA_CNT1 0x1704
1696#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1697#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1698
1699
1700
1701
1702#define RX_STA_CNT2 0x1708
1703#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1704#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1705
1706
1707
1708
1709#define TX_STA_CNT0 0x170c
1710#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1711#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1712
1713
1714
1715
1716#define TX_STA_CNT1 0x1710
1717#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1718#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1719
1720
1721
1722
1723#define TX_STA_CNT2 0x1714
1724#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1725#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751#define TX_STA_FIFO 0x1718
1752#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1753#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1754#define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1755#define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1756#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1757#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1758#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1759#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1760#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1761#define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1762#define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1763
1764
1765
1766
1767#define TX_AGG_CNT 0x171c
1768#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1769#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1770
1771
1772
1773
1774#define TX_AGG_CNT0 0x1720
1775#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1776#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1777
1778
1779
1780
1781#define TX_AGG_CNT1 0x1724
1782#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1783#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1784
1785
1786
1787
1788#define TX_AGG_CNT2 0x1728
1789#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1790#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1791
1792
1793
1794
1795#define TX_AGG_CNT3 0x172c
1796#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1797#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1798
1799
1800
1801
1802#define TX_AGG_CNT4 0x1730
1803#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1804#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1805
1806
1807
1808
1809#define TX_AGG_CNT5 0x1734
1810#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1811#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1812
1813
1814
1815
1816#define TX_AGG_CNT6 0x1738
1817#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1818#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1819
1820
1821
1822
1823#define TX_AGG_CNT7 0x173c
1824#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1825#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1826
1827
1828
1829
1830
1831
1832#define MPDU_DENSITY_CNT 0x1740
1833#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1834#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863#define MAC_WCID_BASE 0x1800
1864#define PAIRWISE_KEY_TABLE_BASE 0x4000
1865#define MAC_IVEIV_TABLE_BASE 0x6000
1866#define MAC_WCID_ATTRIBUTE_BASE 0x6800
1867#define SHARED_KEY_TABLE_BASE 0x6c00
1868#define SHARED_KEY_MODE_BASE 0x7000
1869
1870#define MAC_WCID_ENTRY(__idx) \
1871 (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
1872#define PAIRWISE_KEY_ENTRY(__idx) \
1873 (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1874#define MAC_IVEIV_ENTRY(__idx) \
1875 (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
1876#define MAC_WCID_ATTR_ENTRY(__idx) \
1877 (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
1878#define SHARED_KEY_ENTRY(__idx) \
1879 (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1880#define SHARED_KEY_MODE_ENTRY(__idx) \
1881 (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
1882
1883struct mac_wcid_entry {
1884 u8 mac[6];
1885 u8 reserved[2];
1886} __packed;
1887
1888struct hw_key_entry {
1889 u8 key[16];
1890 u8 tx_mic[8];
1891 u8 rx_mic[8];
1892} __packed;
1893
1894struct mac_iveiv_entry {
1895 u8 iv[8];
1896} __packed;
1897
1898
1899
1900
1901#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1902#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1903#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1904#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1905#define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
1906#define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
1907#define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
1908#define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1909
1910
1911
1912
1913#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1914#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1915#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1916#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1917#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1918#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1919#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1920#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930#define H2M_MAILBOX_CSR 0x7010
1931#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1932#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1933#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1934#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1935
1936
1937
1938
1939
1940
1941#define H2M_MAILBOX_CID 0x7014
1942#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1943#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1944#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1945#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1946
1947
1948
1949
1950
1951#define H2M_MAILBOX_STATUS 0x701c
1952
1953
1954
1955
1956#define H2M_INT_SRC 0x7024
1957
1958
1959
1960
1961#define H2M_BBP_AGENT 0x7028
1962
1963
1964
1965
1966#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1967#define MCU_LEDCS_POLARITY FIELD8(0x01)
1968
1969
1970
1971
1972
1973
1974#define HW_CS_CTS_BASE 0x7700
1975
1976
1977
1978
1979
1980#define HW_DFS_CTS_BASE 0x7780
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990#define TXRX_CSR1 0x77d0
1991
1992
1993
1994
1995
1996
1997#define HW_DEBUG_SETTING_BASE 0x77f0
1998#define HW_DEBUG_SETTING_BASE2 0x7770
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015#define HW_BEACON_BASE0 0x7800
2016#define HW_BEACON_BASE1 0x7a00
2017#define HW_BEACON_BASE2 0x7c00
2018#define HW_BEACON_BASE3 0x7e00
2019#define HW_BEACON_BASE4 0x7200
2020#define HW_BEACON_BASE5 0x7400
2021#define HW_BEACON_BASE6 0x5dc0
2022#define HW_BEACON_BASE7 0x5bc0
2023
2024#define HW_BEACON_BASE(__index) \
2025 (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
2026 (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
2027 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
2028
2029#define BEACON_BASE_TO_OFFSET(_base) (((_base) - 0x4000) / 64)
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044#define BBP1_TX_POWER_CTRL FIELD8(0x03)
2045#define BBP1_TX_ANTENNA FIELD8(0x18)
2046
2047
2048
2049
2050#define BBP3_RX_ADC FIELD8(0x03)
2051#define BBP3_RX_ANTENNA FIELD8(0x18)
2052#define BBP3_HT40_MINUS FIELD8(0x20)
2053#define BBP3_ADC_MODE_SWITCH FIELD8(0x40)
2054#define BBP3_ADC_INIT_MODE FIELD8(0x80)
2055
2056
2057
2058
2059#define BBP4_TX_BF FIELD8(0x01)
2060#define BBP4_BANDWIDTH FIELD8(0x18)
2061#define BBP4_MAC_IF_CTRL FIELD8(0x40)
2062
2063
2064#define BBP27_RX_CHAIN_SEL FIELD8(0x60)
2065
2066
2067
2068
2069#define BBP47_TSSI_REPORT_SEL FIELD8(0x03)
2070#define BBP47_TSSI_UPDATE_REQ FIELD8(0x04)
2071#define BBP47_TSSI_TSSI_MODE FIELD8(0x18)
2072#define BBP47_TSSI_ADC6 FIELD8(0x80)
2073
2074
2075
2076
2077#define BBP49_UPDATE_FLAG FIELD8(0x01)
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088#define BBP105_DETECT_SIG_ON_PRIMARY FIELD8(0x01)
2089#define BBP105_FEQ FIELD8(0x02)
2090#define BBP105_MLD FIELD8(0x04)
2091#define BBP105_SIG_REMODULATION FIELD8(0x08)
2092
2093
2094
2095
2096#define BBP109_TX0_POWER FIELD8(0x0f)
2097#define BBP109_TX1_POWER FIELD8(0xf0)
2098
2099
2100#define BBP110_TX2_POWER FIELD8(0x0f)
2101
2102
2103
2104
2105
2106#define BBP138_RX_ADC1 FIELD8(0x02)
2107#define BBP138_RX_ADC2 FIELD8(0x04)
2108#define BBP138_TX_DAC1 FIELD8(0x20)
2109#define BBP138_TX_DAC2 FIELD8(0x40)
2110
2111
2112
2113
2114#define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
2115
2116
2117
2118
2119#define BBP254_BIT7 FIELD8(0x80)
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129#define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
2130#define RFCSR1_PLL_PD FIELD8(0x02)
2131#define RFCSR1_RX0_PD FIELD8(0x04)
2132#define RFCSR1_TX0_PD FIELD8(0x08)
2133#define RFCSR1_RX1_PD FIELD8(0x10)
2134#define RFCSR1_TX1_PD FIELD8(0x20)
2135#define RFCSR1_RX2_PD FIELD8(0x40)
2136#define RFCSR1_TX2_PD FIELD8(0x80)
2137
2138
2139
2140
2141#define RFCSR2_RESCAL_EN FIELD8(0x80)
2142
2143
2144
2145
2146#define RFCSR3_K FIELD8(0x0f)
2147
2148#define RFCSR3_PA1_BIAS_CCK FIELD8(0x70)
2149#define RFCSR3_PA2_CASCODE_BIAS_CCKK FIELD8(0x80)
2150
2151#define RFCSR3_VCOCAL_EN FIELD8(0x80)
2152
2153#define RFCSR3_BIT1 FIELD8(0x02)
2154#define RFCSR3_BIT2 FIELD8(0x04)
2155#define RFCSR3_BIT3 FIELD8(0x08)
2156#define RFCSR3_BIT4 FIELD8(0x10)
2157#define RFCSR3_BIT5 FIELD8(0x20)
2158
2159
2160
2161
2162#define RFCSR5_R1 FIELD8(0x0c)
2163
2164
2165
2166
2167#define RFCSR6_R1 FIELD8(0x03)
2168#define RFCSR6_R2 FIELD8(0x40)
2169#define RFCSR6_TXDIV FIELD8(0x0c)
2170
2171#define RFCSR6_VCO_IC FIELD8(0xc0)
2172
2173
2174
2175
2176#define RFCSR7_RF_TUNING FIELD8(0x01)
2177#define RFCSR7_BIT1 FIELD8(0x02)
2178#define RFCSR7_BIT2 FIELD8(0x04)
2179#define RFCSR7_BIT3 FIELD8(0x08)
2180#define RFCSR7_BIT4 FIELD8(0x10)
2181#define RFCSR7_BIT5 FIELD8(0x20)
2182#define RFCSR7_BITS67 FIELD8(0xc0)
2183
2184
2185
2186
2187#define RFCSR9_K FIELD8(0x0f)
2188#define RFCSR9_N FIELD8(0x10)
2189#define RFCSR9_UNKNOWN FIELD8(0x60)
2190#define RFCSR9_MOD FIELD8(0x80)
2191
2192
2193
2194
2195#define RFCSR11_R FIELD8(0x03)
2196#define RFCSR11_PLL_MOD FIELD8(0x0c)
2197#define RFCSR11_MOD FIELD8(0xc0)
2198
2199
2200#define RFCSR11_PLL_IDOH FIELD8(0x40)
2201
2202
2203
2204
2205
2206#define RFCSR12_TX_POWER FIELD8(0x1f)
2207#define RFCSR12_DR0 FIELD8(0xe0)
2208
2209
2210
2211
2212#define RFCSR13_TX_POWER FIELD8(0x1f)
2213#define RFCSR13_DR0 FIELD8(0xe0)
2214
2215
2216
2217
2218#define RFCSR15_TX_LO2_EN FIELD8(0x08)
2219
2220
2221
2222
2223#define RFCSR16_TXMIXER_GAIN FIELD8(0x07)
2224
2225
2226
2227
2228#define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
2229#define RFCSR17_TX_LO1_EN FIELD8(0x08)
2230#define RFCSR17_R FIELD8(0x20)
2231#define RFCSR17_CODE FIELD8(0x7f)
2232
2233
2234#define RFCSR18_XO_TUNE_BYPASS FIELD8(0x40)
2235
2236
2237
2238
2239
2240#define RFCSR20_RX_LO1_EN FIELD8(0x08)
2241
2242
2243
2244
2245#define RFCSR21_RX_LO2_EN FIELD8(0x08)
2246
2247
2248
2249
2250#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
2251
2252
2253
2254
2255#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
2256
2257
2258
2259
2260#define RFCSR24_TX_AGC_FC FIELD8(0x1f)
2261#define RFCSR24_TX_H20M FIELD8(0x20)
2262#define RFCSR24_TX_CALIB FIELD8(0x7f)
2263
2264
2265
2266
2267#define RFCSR27_R1 FIELD8(0x03)
2268#define RFCSR27_R2 FIELD8(0x04)
2269#define RFCSR27_R3 FIELD8(0x30)
2270#define RFCSR27_R4 FIELD8(0x40)
2271
2272
2273
2274
2275#define RFCSR29_ADC6_TEST FIELD8(0x01)
2276#define RFCSR29_ADC6_INT_TEST FIELD8(0x02)
2277#define RFCSR29_RSSI_RESET FIELD8(0x04)
2278#define RFCSR29_RSSI_ON FIELD8(0x08)
2279#define RFCSR29_RSSI_RIP_CTRL FIELD8(0x30)
2280#define RFCSR29_RSSI_GAIN FIELD8(0xc0)
2281
2282
2283
2284
2285#define RFCSR30_TX_H20M FIELD8(0x02)
2286#define RFCSR30_RX_H20M FIELD8(0x04)
2287#define RFCSR30_RX_VCM FIELD8(0x18)
2288#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
2289
2290
2291
2292
2293#define RFCSR31_RX_AGC_FC FIELD8(0x1f)
2294#define RFCSR31_RX_H20M FIELD8(0x20)
2295#define RFCSR31_RX_CALIB FIELD8(0x7f)
2296
2297
2298#define RFCSR32_TX_AGC_FC FIELD8(0xf8)
2299
2300
2301#define RFCSR36_RF_BS FIELD8(0x80)
2302
2303
2304
2305
2306#define RFCSR38_RX_LO1_EN FIELD8(0x20)
2307
2308
2309
2310
2311#define RFCSR39_RX_DIV FIELD8(0x40)
2312#define RFCSR39_RX_LO2_EN FIELD8(0x80)
2313
2314
2315
2316
2317#define RFCSR49_TX FIELD8(0x3f)
2318#define RFCSR49_EP FIELD8(0xc0)
2319
2320#define RFCSR49_TX_LO1_IC FIELD8(0x1c)
2321#define RFCSR49_TX_DIV FIELD8(0x20)
2322
2323
2324
2325
2326#define RFCSR50_TX FIELD8(0x3f)
2327#define RFCSR50_EP FIELD8(0xc0)
2328
2329#define RFCSR50_TX_LO1_EN FIELD8(0x20)
2330#define RFCSR50_TX_LO2_EN FIELD8(0x10)
2331
2332
2333
2334#define RFCSR51_BITS01 FIELD8(0x03)
2335#define RFCSR51_BITS24 FIELD8(0x1c)
2336#define RFCSR51_BITS57 FIELD8(0xe0)
2337
2338#define RFCSR53_TX_POWER FIELD8(0x3f)
2339#define RFCSR53_UNKNOWN FIELD8(0xc0)
2340
2341#define RFCSR54_TX_POWER FIELD8(0x3f)
2342#define RFCSR54_UNKNOWN FIELD8(0xc0)
2343
2344#define RFCSR55_TX_POWER FIELD8(0x3f)
2345#define RFCSR55_UNKNOWN FIELD8(0xc0)
2346
2347#define RFCSR57_DRV_CC FIELD8(0xfc)
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
2358#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
2359#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
2360
2361
2362
2363
2364#define RF3_TXPOWER_G FIELD32(0x00003e00)
2365#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
2366#define RF3_TXPOWER_A FIELD32(0x00003c00)
2367
2368
2369
2370
2371#define RF4_TXPOWER_G FIELD32(0x000007c0)
2372#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
2373#define RF4_TXPOWER_A FIELD32(0x00000780)
2374#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
2375#define RF4_HT40 FIELD32(0x00200000)
2376
2377
2378
2379
2380
2381
2382enum rt2800_eeprom_word {
2383 EEPROM_CHIP_ID = 0,
2384 EEPROM_VERSION,
2385 EEPROM_MAC_ADDR_0,
2386 EEPROM_MAC_ADDR_1,
2387 EEPROM_MAC_ADDR_2,
2388 EEPROM_NIC_CONF0,
2389 EEPROM_NIC_CONF1,
2390 EEPROM_FREQ,
2391 EEPROM_LED_AG_CONF,
2392 EEPROM_LED_ACT_CONF,
2393 EEPROM_LED_POLARITY,
2394 EEPROM_NIC_CONF2,
2395 EEPROM_LNA,
2396 EEPROM_RSSI_BG,
2397 EEPROM_RSSI_BG2,
2398 EEPROM_TXMIXER_GAIN_BG,
2399 EEPROM_RSSI_A,
2400 EEPROM_RSSI_A2,
2401 EEPROM_TXMIXER_GAIN_A,
2402 EEPROM_EIRP_MAX_TX_POWER,
2403 EEPROM_TXPOWER_DELTA,
2404 EEPROM_TXPOWER_BG1,
2405 EEPROM_TXPOWER_BG2,
2406 EEPROM_TSSI_BOUND_BG1,
2407 EEPROM_TSSI_BOUND_BG2,
2408 EEPROM_TSSI_BOUND_BG3,
2409 EEPROM_TSSI_BOUND_BG4,
2410 EEPROM_TSSI_BOUND_BG5,
2411 EEPROM_TXPOWER_A1,
2412 EEPROM_TXPOWER_A2,
2413 EEPROM_TSSI_BOUND_A1,
2414 EEPROM_TSSI_BOUND_A2,
2415 EEPROM_TSSI_BOUND_A3,
2416 EEPROM_TSSI_BOUND_A4,
2417 EEPROM_TSSI_BOUND_A5,
2418 EEPROM_TXPOWER_BYRATE,
2419 EEPROM_BBP_START,
2420
2421
2422 EEPROM_EXT_LNA2,
2423 EEPROM_EXT_TXPOWER_BG3,
2424 EEPROM_EXT_TXPOWER_A3,
2425
2426
2427 EEPROM_WORD_COUNT
2428};
2429
2430
2431
2432
2433#define EEPROM_VERSION_FAE FIELD16(0x00ff)
2434#define EEPROM_VERSION_VERSION FIELD16(0xff00)
2435
2436
2437
2438
2439#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
2440#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
2441#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
2442#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
2443#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
2444#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
2445
2446
2447
2448
2449
2450
2451
2452#define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f)
2453#define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0)
2454#define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00)
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475#define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001)
2476#define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002)
2477#define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004)
2478#define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008)
2479#define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010)
2480#define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020)
2481#define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040)
2482#define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080)
2483#define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100)
2484#define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200)
2485#define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400)
2486#define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800)
2487#define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000)
2488#define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000)
2489#define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000)
2490
2491
2492
2493
2494#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
2495#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
2496#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
2511#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
2512#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
2513#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
2514#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
2515#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
2516#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
2517#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
2518#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
2519
2520
2521
2522
2523
2524
2525
2526#define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
2527#define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
2528#define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
2529
2530
2531
2532
2533#define EEPROM_LNA_BG FIELD16(0x00ff)
2534#define EEPROM_LNA_A0 FIELD16(0xff00)
2535
2536
2537
2538
2539#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
2540#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
2541
2542
2543
2544
2545#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
2546#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
2547
2548
2549
2550
2551#define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
2552
2553
2554
2555
2556#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
2557#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
2558
2559
2560
2561
2562#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
2563#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
2564
2565
2566
2567
2568#define EEPROM_TXMIXER_GAIN_A_VAL FIELD16(0x0007)
2569
2570
2571
2572
2573#define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff)
2574#define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00)
2575
2576
2577
2578
2579
2580
2581
2582
2583#define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f)
2584#define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040)
2585#define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
2586#define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00)
2587#define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000)
2588#define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000)
2589
2590
2591
2592
2593#define EEPROM_TXPOWER_BG_SIZE 7
2594#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
2595#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
2596
2597
2598
2599
2600
2601
2602
2603
2604#define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff)
2605#define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00)
2606
2607
2608
2609
2610
2611
2612
2613
2614#define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff)
2615#define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00)
2616
2617
2618
2619
2620
2621
2622
2623#define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff)
2624#define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00)
2625
2626
2627
2628
2629
2630
2631
2632
2633#define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff)
2634#define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00)
2635
2636
2637
2638
2639
2640
2641
2642#define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff)
2643#define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00)
2644
2645
2646
2647
2648#define EEPROM_TXPOWER_A_SIZE 6
2649#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
2650#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
2651
2652
2653#define EEPROM_TXPOWER_ALC FIELD8(0x1f)
2654#define EEPROM_TXPOWER_FINE_CTRL FIELD8(0xe0)
2655
2656
2657
2658
2659
2660
2661
2662
2663#define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff)
2664#define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00)
2665
2666
2667
2668
2669
2670
2671
2672
2673#define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff)
2674#define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00)
2675
2676
2677
2678
2679
2680
2681
2682#define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff)
2683#define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00)
2684
2685
2686
2687
2688
2689
2690
2691
2692#define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff)
2693#define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00)
2694
2695
2696
2697
2698
2699
2700
2701#define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff)
2702#define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00)
2703
2704
2705
2706
2707#define EEPROM_TXPOWER_BYRATE_SIZE 9
2708
2709#define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
2710#define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
2711#define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
2712#define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
2713
2714
2715
2716
2717#define EEPROM_BBP_SIZE 16
2718#define EEPROM_BBP_VALUE FIELD16(0x00ff)
2719#define EEPROM_BBP_REG_ID FIELD16(0xff00)
2720
2721
2722#define EEPROM_EXT_LNA2_A1 FIELD16(0x00ff)
2723#define EEPROM_EXT_LNA2_A2 FIELD16(0xff00)
2724
2725
2726
2727
2728
2729#define EEPROM_IQ_GAIN_CAL_TX0_2G 0x130
2730#define EEPROM_IQ_PHASE_CAL_TX0_2G 0x131
2731#define EEPROM_IQ_GROUPDELAY_CAL_TX0_2G 0x132
2732#define EEPROM_IQ_GAIN_CAL_TX1_2G 0x133
2733#define EEPROM_IQ_PHASE_CAL_TX1_2G 0x134
2734#define EEPROM_IQ_GROUPDELAY_CAL_TX1_2G 0x135
2735#define EEPROM_IQ_GAIN_CAL_RX0_2G 0x136
2736#define EEPROM_IQ_PHASE_CAL_RX0_2G 0x137
2737#define EEPROM_IQ_GROUPDELAY_CAL_RX0_2G 0x138
2738#define EEPROM_IQ_GAIN_CAL_RX1_2G 0x139
2739#define EEPROM_IQ_PHASE_CAL_RX1_2G 0x13A
2740#define EEPROM_IQ_GROUPDELAY_CAL_RX1_2G 0x13B
2741#define EEPROM_RF_IQ_COMPENSATION_CONTROL 0x13C
2742#define EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL 0x13D
2743#define EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G 0x144
2744#define EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G 0x145
2745#define EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G 0X146
2746#define EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G 0x147
2747#define EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G 0x148
2748#define EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G 0x149
2749#define EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G 0x14A
2750#define EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G 0x14B
2751#define EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G 0X14C
2752#define EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G 0x14D
2753#define EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G 0x14E
2754#define EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G 0x14F
2755#define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH36_TO_CH64_5G 0x150
2756#define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH36_TO_CH64_5G 0x151
2757#define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH100_TO_CH138_5G 0x152
2758#define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH100_TO_CH138_5G 0x153
2759#define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH140_TO_CH165_5G 0x154
2760#define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH140_TO_CH165_5G 0x155
2761#define EEPROM_IQ_GAIN_CAL_RX0_CH36_TO_CH64_5G 0x156
2762#define EEPROM_IQ_PHASE_CAL_RX0_CH36_TO_CH64_5G 0x157
2763#define EEPROM_IQ_GAIN_CAL_RX0_CH100_TO_CH138_5G 0X158
2764#define EEPROM_IQ_PHASE_CAL_RX0_CH100_TO_CH138_5G 0x159
2765#define EEPROM_IQ_GAIN_CAL_RX0_CH140_TO_CH165_5G 0x15A
2766#define EEPROM_IQ_PHASE_CAL_RX0_CH140_TO_CH165_5G 0x15B
2767#define EEPROM_IQ_GAIN_CAL_RX1_CH36_TO_CH64_5G 0x15C
2768#define EEPROM_IQ_PHASE_CAL_RX1_CH36_TO_CH64_5G 0x15D
2769#define EEPROM_IQ_GAIN_CAL_RX1_CH100_TO_CH138_5G 0X15E
2770#define EEPROM_IQ_PHASE_CAL_RX1_CH100_TO_CH138_5G 0x15F
2771#define EEPROM_IQ_GAIN_CAL_RX1_CH140_TO_CH165_5G 0x160
2772#define EEPROM_IQ_PHASE_CAL_RX1_CH140_TO_CH165_5G 0x161
2773#define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH36_TO_CH64_5G 0x162
2774#define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH36_TO_CH64_5G 0x163
2775#define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH100_TO_CH138_5G 0x164
2776#define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH100_TO_CH138_5G 0x165
2777#define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH140_TO_CH165_5G 0x166
2778#define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH140_TO_CH165_5G 0x167
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789#define MCU_SLEEP 0x30
2790#define MCU_WAKEUP 0x31
2791#define MCU_RADIO_OFF 0x35
2792#define MCU_CURRENT 0x36
2793#define MCU_LED 0x50
2794#define MCU_LED_STRENGTH 0x51
2795#define MCU_LED_AG_CONF 0x52
2796#define MCU_LED_ACT_CONF 0x53
2797#define MCU_LED_LED_POLARITY 0x54
2798#define MCU_RADAR 0x60
2799#define MCU_BOOT_SIGNAL 0x72
2800#define MCU_ANT_SELECT 0X73
2801#define MCU_FREQ_OFFSET 0x74
2802#define MCU_BBP_SIGNAL 0x80
2803#define MCU_POWER_SAVE 0x83
2804#define MCU_BAND_SELECT 0x91
2805
2806
2807
2808
2809#define TOKEN_SLEEP 1
2810#define TOKEN_RADIO_OFF 2
2811#define TOKEN_WAKEUP 3
2812
2813
2814
2815
2816
2817
2818#define TXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32))
2819#define TXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32))
2820
2821#define RXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32))
2822#define RXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32))
2823#define RXWI_DESC_SIZE_6WORDS (6 * sizeof(__le32))
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846#define TXWI_W0_FRAG FIELD32(0x00000001)
2847#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
2848#define TXWI_W0_CF_ACK FIELD32(0x00000004)
2849#define TXWI_W0_TS FIELD32(0x00000008)
2850#define TXWI_W0_AMPDU FIELD32(0x00000010)
2851#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
2852#define TXWI_W0_TX_OP FIELD32(0x00000300)
2853#define TXWI_W0_MCS FIELD32(0x007f0000)
2854#define TXWI_W0_BW FIELD32(0x00800000)
2855#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
2856#define TXWI_W0_STBC FIELD32(0x06000000)
2857#define TXWI_W0_IFS FIELD32(0x08000000)
2858#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876#define TXWI_W1_ACK FIELD32(0x00000001)
2877#define TXWI_W1_NSEQ FIELD32(0x00000002)
2878#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
2879#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
2880#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2881#define TXWI_W1_PACKETID FIELD32(0xf0000000)
2882#define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
2883#define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
2884
2885
2886
2887
2888#define TXWI_W2_IV FIELD32(0xffffffff)
2889
2890
2891
2892
2893#define TXWI_W3_EIV FIELD32(0xffffffff)
2894
2895
2896
2897
2898
2899
2900
2901
2902#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
2903#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
2904#define RXWI_W0_BSSID FIELD32(0x00001c00)
2905#define RXWI_W0_UDF FIELD32(0x0000e000)
2906#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2907#define RXWI_W0_TID FIELD32(0xf0000000)
2908
2909
2910
2911
2912#define RXWI_W1_FRAG FIELD32(0x0000000f)
2913#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
2914#define RXWI_W1_MCS FIELD32(0x007f0000)
2915#define RXWI_W1_BW FIELD32(0x00800000)
2916#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
2917#define RXWI_W1_STBC FIELD32(0x06000000)
2918#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
2919
2920
2921
2922
2923#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
2924#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
2925#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
2926
2927
2928
2929
2930#define RXWI_W3_SNR0 FIELD32(0x000000ff)
2931#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
2932
2933
2934
2935
2936
2937#define MIN_G_TXPOWER 0
2938#define MIN_A_TXPOWER -7
2939#define MAX_G_TXPOWER 31
2940#define MAX_A_TXPOWER 15
2941#define DEFAULT_TXPOWER 5
2942
2943#define MIN_A_TXPOWER_3593 0
2944#define MAX_A_TXPOWER_3593 31
2945
2946#define TXPOWER_G_FROM_DEV(__txpower) \
2947 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2948
2949#define TXPOWER_A_FROM_DEV(__txpower) \
2950 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2951
2952
2953
2954
2955#define EIRP_MAX_TX_POWER_LIMIT 0x50
2956
2957
2958
2959
2960
2961#define BCN_TBTT_OFFSET 64
2962
2963
2964
2965
2966
2967
2968#define WCID_START 33
2969#define WCID_END 222
2970#define STA_IDS_SIZE (WCID_END - WCID_START + 2)
2971
2972
2973
2974
2975struct rt2800_drv_data {
2976 u8 calibration_bw20;
2977 u8 calibration_bw40;
2978 u8 bbp25;
2979 u8 bbp26;
2980 u8 txmixer_gain_24g;
2981 u8 txmixer_gain_5g;
2982 unsigned int tbtt_tick;
2983 DECLARE_BITMAP(sta_ids, STA_IDS_SIZE);
2984};
2985
2986#endif
2987