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22#ifndef __WL12XX_PRIV_H__
23#define __WL12XX_PRIV_H__
24
25#include "conf.h"
26
27
28#define CHIP_ID_127X_PG10 (0x04030101)
29#define CHIP_ID_127X_PG20 (0x04030111)
30#define CHIP_ID_128X_PG10 (0x05030101)
31#define CHIP_ID_128X_PG20 (0x05030111)
32
33
34#define WL127X_CHIP_VER 6
35
36#define WL127X_IFTYPE_SR_VER 3
37#define WL127X_MAJOR_SR_VER 10
38#define WL127X_SUBTYPE_SR_VER WLCORE_FW_VER_IGNORE
39#define WL127X_MINOR_SR_VER 133
40
41#define WL127X_IFTYPE_MR_VER 5
42#define WL127X_MAJOR_MR_VER 7
43#define WL127X_SUBTYPE_MR_VER WLCORE_FW_VER_IGNORE
44#define WL127X_MINOR_MR_VER 42
45
46
47#define WL128X_CHIP_VER 7
48
49#define WL128X_IFTYPE_SR_VER 3
50#define WL128X_MAJOR_SR_VER 10
51#define WL128X_SUBTYPE_SR_VER WLCORE_FW_VER_IGNORE
52#define WL128X_MINOR_SR_VER 133
53
54#define WL128X_IFTYPE_MR_VER 5
55#define WL128X_MAJOR_MR_VER 7
56#define WL128X_SUBTYPE_MR_VER WLCORE_FW_VER_IGNORE
57#define WL128X_MINOR_MR_VER 42
58
59#define WL12XX_AGGR_BUFFER_SIZE (4 * PAGE_SIZE)
60
61#define WL12XX_NUM_TX_DESCRIPTORS 16
62#define WL12XX_NUM_RX_DESCRIPTORS 8
63
64#define WL12XX_NUM_MAC_ADDRESSES 2
65
66#define WL12XX_RX_BA_MAX_SESSIONS 3
67
68#define WL12XX_MAX_AP_STATIONS 8
69#define WL12XX_MAX_LINKS 12
70
71struct wl127x_rx_mem_pool_addr {
72 u32 addr;
73 u32 addr_extra;
74};
75
76struct wl12xx_priv {
77 struct wl12xx_priv_conf conf;
78
79 int ref_clock;
80 int tcxo_clock;
81
82 struct wl127x_rx_mem_pool_addr *rx_mem_addr;
83};
84
85
86enum {
87 WL12XX_REFCLOCK_19 = 0,
88 WL12XX_REFCLOCK_26 = 1,
89 WL12XX_REFCLOCK_38 = 2,
90 WL12XX_REFCLOCK_52 = 3,
91 WL12XX_REFCLOCK_38_XTAL = 4,
92 WL12XX_REFCLOCK_26_XTAL = 5,
93};
94
95
96enum {
97 WL12XX_TCXOCLOCK_19_2 = 0,
98 WL12XX_TCXOCLOCK_26 = 1,
99 WL12XX_TCXOCLOCK_38_4 = 2,
100 WL12XX_TCXOCLOCK_52 = 3,
101 WL12XX_TCXOCLOCK_16_368 = 4,
102 WL12XX_TCXOCLOCK_32_736 = 5,
103 WL12XX_TCXOCLOCK_16_8 = 6,
104 WL12XX_TCXOCLOCK_33_6 = 7,
105};
106
107struct wl12xx_clock {
108 u32 freq;
109 bool xtal;
110 u8 hw_idx;
111};
112
113struct wl12xx_fw_packet_counters {
114
115 u8 tx_released_pkts[NUM_TX_QUEUES];
116
117
118 u8 tx_lnk_free_pkts[WL12XX_MAX_LINKS];
119
120
121 u8 tx_voice_released_blks;
122
123
124 u8 tx_last_rate;
125
126 u8 padding[2];
127} __packed;
128
129
130struct wl12xx_fw_status {
131 __le32 intr;
132 u8 fw_rx_counter;
133 u8 drv_rx_counter;
134 u8 reserved;
135 u8 tx_results_counter;
136 __le32 rx_pkt_descs[WL12XX_NUM_RX_DESCRIPTORS];
137
138 __le32 fw_localtime;
139
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142
143
144 __le32 link_ps_bitmap;
145
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148
149
150 __le32 link_fast_bitmap;
151
152
153 __le32 total_released_blks;
154
155
156 __le32 tx_total;
157
158 struct wl12xx_fw_packet_counters counters;
159
160 __le32 log_start_addr;
161} __packed;
162
163#endif
164