LXR linux/drivers/staging/apf/xilinx-dma-apf.h

   1/*
   2 * Xilinx AXI DMA Engine support
   3 *
   4 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
   5 *
   6 * This is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 */
  12
  13#ifndef __XILINX_DMA_APF_H
  14#define __XILINX_DMA_APF_H
  15
  16/* ioctls */
  17#include <linux/ioctl.h>
  18
  19/* tasklet */
  20#include <linux/interrupt.h>
  21
  22/* dma stuff */
  23#include <linux/dma-mapping.h>
  24
  25/* xlnk structures */
  26#include "xlnk.h"
  27#include "xlnk-sysdef.h"
  28
  29#define XDMA_IOC_MAGIC 'X'
  30#define XDMA_IOCRESET           _IO(XDMA_IOC_MAGIC, 0)
  31#define XDMA_IOCREQUEST         _IOWR(XDMA_IOC_MAGIC, 1, unsigned long)
  32#define XDMA_IOCRELEASE         _IOWR(XDMA_IOC_MAGIC, 2, unsigned long)
  33#define XDMA_IOCSUBMIT          _IOWR(XDMA_IOC_MAGIC, 3, unsigned long)
  34#define XDMA_IOCWAIT            _IOWR(XDMA_IOC_MAGIC, 4, unsigned long)
  35#define XDMA_IOCGETCONFIG       _IOWR(XDMA_IOC_MAGIC, 5, unsigned long)
  36#define XDMA_IOCSETCONFIG       _IOWR(XDMA_IOC_MAGIC, 6, unsigned long)
  37#define XDMA_IOC_MAXNR          6
  38
  39/* Specific hardware configuration-related constants
  40 */
  41#define XDMA_RESET_LOOP            1000000
  42#define XDMA_HALT_LOOP             1000000
  43#define XDMA_NO_CHANGE             0xFFFF
  44
  45/* General register bits definitions
  46 */
  47#define XDMA_CR_RESET_MASK    0x00000004  /* Reset DMA engine */
  48#define XDMA_CR_RUNSTOP_MASK  0x00000001  /* Start/stop DMA engine */
  49
  50#define XDMA_SR_HALTED_MASK   0x00000001  /* DMA channel halted */
  51#define XDMA_SR_IDLE_MASK     0x00000002  /* DMA channel idle */
  52
  53#define XDMA_SR_ERR_INTERNAL_MASK 0x00000010/* Datamover internal err */
  54#define XDMA_SR_ERR_SLAVE_MASK    0x00000020 /* Datamover slave err */
  55#define XDMA_SR_ERR_DECODE_MASK   0x00000040 /* Datamover decode err */
  56#define XDMA_SR_ERR_SG_INT_MASK   0x00000100 /* SG internal err */
  57#define XDMA_SR_ERR_SG_SLV_MASK   0x00000200 /* SG slave err */
  58#define XDMA_SR_ERR_SG_DEC_MASK   0x00000400 /* SG decode err */
  59#define XDMA_SR_ERR_ALL_MASK      0x00000770 /* All errors */
  60
  61#define XDMA_XR_IRQ_IOC_MASK    0x00001000 /* Completion interrupt */
  62#define XDMA_XR_IRQ_DELAY_MASK  0x00002000 /* Delay interrupt */
  63#define XDMA_XR_IRQ_ERROR_MASK  0x00004000 /* Error interrupt */
  64#define XDMA_XR_IRQ_ALL_MASK        0x00007000 /* All interrupts */
  65
  66#define XDMA_XR_DELAY_MASK    0xFF000000 /* Delay timeout counter */
  67#define XDMA_XR_COALESCE_MASK 0x00FF0000 /* Coalesce counter */
  68
  69#define XDMA_DELAY_SHIFT    24
  70#define XDMA_COALESCE_SHIFT 16
  71
  72#define XDMA_DELAY_MAX     0xFF /**< Maximum delay counter value */
  73#define XDMA_COALESCE_MAX  0xFF /**< Maximum coalescing counter value */
  74
  75/* BD definitions for Axi DMA
  76 */
  77#define XDMA_BD_STS_ACTUAL_LEN_MASK     0x007FFFFF
  78#define XDMA_BD_STS_COMPL_MASK 0x80000000
  79#define XDMA_BD_STS_ERR_MASK   0x70000000
  80#define XDMA_BD_STS_ALL_MASK   0xF0000000
  81
  82/* DMA BD special bits definitions
  83 */
  84#define XDMA_BD_SOP       0x08000000    /* Start of packet bit */
  85#define XDMA_BD_EOP       0x04000000    /* End of packet bit */
  86
  87/* BD Software Flag definitions for Axi DMA
  88 */
  89#define XDMA_BD_SF_POLL_MODE_MASK       0x00000002
  90#define XDMA_BD_SF_SW_DONE_MASK         0x00000001
  91
  92/* driver defines */
  93#define XDMA_MAX_BD_CNT                 16384
  94#define XDMA_MAX_CHANS_PER_DEVICE       2
  95#define XDMA_MAX_TRANS_LEN              0x7FF000
  96#define XDMA_MAX_APPWORDS               5
  97#define XDMA_BD_CLEANUP_THRESHOLD       ((XDMA_MAX_BD_CNT * 8) / 10)
  98
  99#define XDMA_FLAGS_WAIT_COMPLETE 1
 100#define XDMA_FLAGS_TRYWAIT 2
 101
 102/* Platform data definition until ARM supports device tree */
 103struct xdma_channel_config {
 104        char *type;
 105        unsigned int include_dre;
 106        unsigned int datawidth;
 107        unsigned int max_burst_len;
 108        unsigned int irq;
 109        unsigned int poll_mode;
 110        unsigned int lite_mode;
 111};
 112
 113struct xdma_device_config {
 114        char *type;
 115        char *name;
 116        unsigned int include_sg;
 117        unsigned int sg_include_stscntrl_strm;  /* dma only */
 118        unsigned int channel_count;
 119        struct xdma_channel_config *channel_config;
 120};
 121
 122struct xdma_desc_hw {
 123        xlnk_intptr_type next_desc;     /* 0x00 */
 124#if XLNK_SYS_BIT_WIDTH == 32
 125        u32 pad1;       /* 0x04 */
 126#endif
 127        xlnk_intptr_type src_addr;   /* 0x08 */
 128#if XLNK_SYS_BIT_WIDTH == 32
 129        u32 pad2;       /* 0x0c */
 130#endif
 131        u32 addr_vsize; /* 0x10 */
 132        u32 hsize;       /* 0x14 */
 133        u32 control;    /* 0x18 */
 134        u32 status;     /* 0x1c */
 135        u32 app[5];      /* 0x20 */
 136        xlnk_intptr_type dmahead;
 137#if XLNK_SYS_BIT_WIDTH == 32
 138        u32 Reserved0;
 139#endif
 140        u32 sw_flag;    /* 0x3C */
 141} __aligned(64);
 142
 143/* shared by all Xilinx DMA engines */
 144struct xdma_regs {
 145        u32 cr;        /* 0x00 Control Register */
 146        u32 sr;        /* 0x04 Status Register */
 147        u32 cdr;       /* 0x08 Current Descriptor Register */
 148        u32 cdr_hi;
 149        u32 tdr;       /* 0x10 Tail Descriptor Register */
 150        u32 tdr_hi;
 151        u32 src;       /* 0x18 Source Address Register (cdma) */
 152        u32 src_hi;
 153        u32 dst;       /* 0x20 Destination Address Register (cdma) */
 154        u32 dst_hi;
 155        u32 btt_ref;   /* 0x28 Bytes To Transfer (cdma) or
 156                        *               park_ref (vdma)
 157                        */
 158        u32 version;   /* 0x2c version (vdma) */
 159};
 160
 161/* Per DMA specific operations should be embedded in the channel structure */
 162struct xdma_chan {
 163        char name[64];
 164        struct xdma_regs __iomem *regs;
 165        struct device *dev;                     /* The dma device */
 166        struct xdma_desc_hw *bds[XDMA_MAX_BD_CNT];
 167        dma_addr_t bd_phys_addr;
 168        u32 bd_chain_size;
 169        int bd_cur;
 170        int bd_tail;
 171        unsigned int bd_used;                   /* # of BDs passed to hw chan */
 172        enum dma_data_direction direction;      /* Transfer direction */
 173        int id;                                 /* Channel ID */
 174        int irq;                                /* Channel IRQ */
 175        int poll_mode;                          /* Poll mode turned on? */
 176        spinlock_t lock;                        /* Descriptor operation lock */
 177        struct tasklet_struct tasklet;          /* Cleanup work after irq */
 178        struct tasklet_struct dma_err_tasklet;  /* Cleanup work after irq */
 179        int    max_len;                         /* Maximum len per transfer */
 180        int    err;                             /* Channel has errors */
 181        int    client_count;
 182        struct scatterlist scratch_sglist[XDMA_MAX_BD_CNT];
 183};
 184
 185struct xdma_device {
 186        void __iomem *regs;
 187        struct device *dev;
 188        struct list_head node;
 189        struct xdma_chan *chan[XDMA_MAX_CHANS_PER_DEVICE];
 190        u8 channel_count;
 191};
 192
 193struct xdma_head {
 194        xlnk_intptr_type userbuf;
 195        unsigned int size;
 196        unsigned int dmaflag;
 197        enum dma_data_direction dmadir;
 198        void *sglist;
 199        unsigned int sgcnt;
 200        struct completion cmp;
 201        struct xdma_chan *chan;
 202        unsigned int nappwords_o;
 203        u32 appwords_o[XDMA_MAX_APPWORDS];
 204        unsigned int userflag;
 205        u32 last_bd_index;
 206        struct xlnk_dmabuf_reg *dmabuf;
 207};
 208
 209struct xdma_chan *xdma_request_channel(char *name);
 210void xdma_release_channel(struct xdma_chan *chan);
 211void xdma_release_all_channels(void);
 212int xdma_submit(struct xdma_chan *chan,
 213                xlnk_intptr_type userbuf,
 214                void *kaddr,
 215                unsigned int size,
 216                unsigned int nappwords_i,
 217                u32 *appwords_i,
 218                unsigned int nappwords_o,
 219                unsigned int user_flags,
 220                struct xdma_head **dmaheadpp,
 221                struct xlnk_dmabuf_reg *dp);
 222int xdma_wait(struct xdma_head *dmahead,
 223              unsigned int user_flags,
 224              unsigned int *operating_flags);
 225int xdma_getconfig(struct xdma_chan *chan,
 226                   unsigned char *irq_thresh,
 227                   unsigned char *irq_delay);
 228int xdma_setconfig(struct xdma_chan *chan,
 229                   unsigned char irq_thresh,
 230                   unsigned char irq_delay);
 231
 232#endif
 233