1
2
3
4
5
6
7
8
9
10
11
12
13
14
15#ifndef _ASM_POWERPC_QE_H
16#define _ASM_POWERPC_QE_H
17#ifdef __KERNEL__
18
19#include <linux/compiler.h>
20#include <linux/genalloc.h>
21#include <linux/spinlock.h>
22#include <linux/errno.h>
23#include <linux/err.h>
24#include <asm/cpm.h>
25#include <soc/fsl/qe/immap_qe.h>
26#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/types.h>
29
30#define QE_NUM_OF_SNUM 256
31#define QE_NUM_OF_BRGS 16
32#define QE_NUM_OF_PORTS 1024
33
34
35
36#define MEM_PART_SYSTEM 0
37#define MEM_PART_SECONDARY 1
38#define MEM_PART_MURAM 2
39
40
41enum qe_clock {
42 QE_CLK_NONE = 0,
43 QE_BRG1,
44 QE_BRG2,
45 QE_BRG3,
46 QE_BRG4,
47 QE_BRG5,
48 QE_BRG6,
49 QE_BRG7,
50 QE_BRG8,
51 QE_BRG9,
52 QE_BRG10,
53 QE_BRG11,
54 QE_BRG12,
55 QE_BRG13,
56 QE_BRG14,
57 QE_BRG15,
58 QE_BRG16,
59 QE_CLK1,
60 QE_CLK2,
61 QE_CLK3,
62 QE_CLK4,
63 QE_CLK5,
64 QE_CLK6,
65 QE_CLK7,
66 QE_CLK8,
67 QE_CLK9,
68 QE_CLK10,
69 QE_CLK11,
70 QE_CLK12,
71 QE_CLK13,
72 QE_CLK14,
73 QE_CLK15,
74 QE_CLK16,
75 QE_CLK17,
76 QE_CLK18,
77 QE_CLK19,
78 QE_CLK20,
79 QE_CLK21,
80 QE_CLK22,
81 QE_CLK23,
82 QE_CLK24,
83 QE_RSYNC_PIN,
84 QE_TSYNC_PIN,
85 QE_CLK_DUMMY
86};
87
88static inline bool qe_clock_is_brg(enum qe_clock clk)
89{
90 return clk >= QE_BRG1 && clk <= QE_BRG16;
91}
92
93extern spinlock_t cmxgcr_lock;
94
95
96#ifdef CONFIG_QUICC_ENGINE
97extern void qe_reset(void);
98#else
99static inline void qe_reset(void) {}
100#endif
101
102int cpm_muram_init(void);
103
104#if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
105unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
106int cpm_muram_free(unsigned long offset);
107unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
108void __iomem *cpm_muram_addr(unsigned long offset);
109unsigned long cpm_muram_offset(void __iomem *addr);
110dma_addr_t cpm_muram_dma(void __iomem *addr);
111#else
112static inline unsigned long cpm_muram_alloc(unsigned long size,
113 unsigned long align)
114{
115 return -ENOSYS;
116}
117
118static inline int cpm_muram_free(unsigned long offset)
119{
120 return -ENOSYS;
121}
122
123static inline unsigned long cpm_muram_alloc_fixed(unsigned long offset,
124 unsigned long size)
125{
126 return -ENOSYS;
127}
128
129static inline void __iomem *cpm_muram_addr(unsigned long offset)
130{
131 return NULL;
132}
133
134static inline unsigned long cpm_muram_offset(void __iomem *addr)
135{
136 return -ENOSYS;
137}
138
139static inline dma_addr_t cpm_muram_dma(void __iomem *addr)
140{
141 return 0;
142}
143#endif
144
145
146#define QE_PIO_PINS 32
147
148struct qe_pio_regs {
149 __be32 cpodr;
150 __be32 cpdata;
151 __be32 cpdir1;
152 __be32 cpdir2;
153 __be32 cppar1;
154 __be32 cppar2;
155#ifdef CONFIG_PPC_85xx
156 u8 pad[8];
157#endif
158};
159
160#define QE_PIO_DIR_IN 2
161#define QE_PIO_DIR_OUT 1
162extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
163 int dir, int open_drain, int assignment,
164 int has_irq);
165#ifdef CONFIG_QUICC_ENGINE
166extern int par_io_init(struct device_node *np);
167extern int par_io_of_config(struct device_node *np);
168extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
169 int assignment, int has_irq);
170extern int par_io_data_set(u8 port, u8 pin, u8 val);
171#else
172static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
173static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
174static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
175 int assignment, int has_irq) { return -ENOSYS; }
176static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
177#endif
178
179
180
181
182struct qe_pin;
183#ifdef CONFIG_QE_GPIO
184extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
185extern void qe_pin_free(struct qe_pin *qe_pin);
186extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
187extern void qe_pin_set_dedicated(struct qe_pin *pin);
188#else
189static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
190{
191 return ERR_PTR(-ENOSYS);
192}
193static inline void qe_pin_free(struct qe_pin *qe_pin) {}
194static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
195static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
196#endif
197
198#ifdef CONFIG_QUICC_ENGINE
199int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
200#else
201static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
202 u32 cmd_input)
203{
204 return -ENOSYS;
205}
206#endif
207
208
209enum qe_clock qe_clock_source(const char *source);
210unsigned int qe_get_brg_clk(void);
211int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
212int qe_get_snum(void);
213void qe_put_snum(u8 snum);
214unsigned int qe_get_num_of_risc(void);
215unsigned int qe_get_num_of_snums(void);
216
217static inline int qe_alive_during_sleep(void)
218{
219
220
221
222
223
224
225
226
227
228
229
230
231
232#ifdef CONFIG_PPC_85xx
233 return 0;
234#else
235 return 1;
236#endif
237}
238
239
240#define qe_muram_init cpm_muram_init
241#define qe_muram_alloc cpm_muram_alloc
242#define qe_muram_alloc_fixed cpm_muram_alloc_fixed
243#define qe_muram_free cpm_muram_free
244#define qe_muram_addr cpm_muram_addr
245#define qe_muram_offset cpm_muram_offset
246
247#define qe_setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
248#define qe_clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
249
250#define qe_setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
251#define qe_clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
252
253#define qe_setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
254#define qe_clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
255
256#define qe_clrsetbits32(addr, clear, set) \
257 iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
258#define qe_clrsetbits16(addr, clear, set) \
259 iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
260#define qe_clrsetbits8(addr, clear, set) \
261 iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
262
263
264
265
266
267
268struct qe_firmware {
269 struct qe_header {
270 __be32 length;
271 u8 magic[3];
272 u8 version;
273 } header;
274 u8 id[62];
275 u8 split;
276 u8 count;
277 struct {
278 __be16 model;
279 u8 major;
280 u8 minor;
281 } __attribute__ ((packed)) soc;
282 u8 padding[4];
283 __be64 extended_modes;
284 __be32 vtraps[8];
285 u8 reserved[4];
286 struct qe_microcode {
287 u8 id[32];
288 __be32 traps[16];
289 __be32 eccr;
290 __be32 iram_offset;
291 __be32 count;
292 __be32 code_offset;
293 u8 major;
294 u8 minor;
295 u8 revision;
296 u8 padding;
297 u8 reserved[4];
298 } __attribute__ ((packed)) microcode[1];
299
300
301} __attribute__ ((packed));
302
303struct qe_firmware_info {
304 char id[64];
305 u32 vtraps[8];
306 u64 extended_modes;
307};
308
309#ifdef CONFIG_QUICC_ENGINE
310
311int qe_upload_firmware(const struct qe_firmware *firmware);
312#else
313static inline int qe_upload_firmware(const struct qe_firmware *firmware)
314{
315 return -ENOSYS;
316}
317#endif
318
319
320struct qe_firmware_info *qe_get_firmware_info(void);
321
322
323int qe_usb_clock_set(enum qe_clock clk, int rate);
324
325
326struct qe_bd {
327 __be16 status;
328 __be16 length;
329 __be32 buf;
330} __attribute__ ((packed));
331
332#define BD_STATUS_MASK 0xffff0000
333#define BD_LENGTH_MASK 0x0000ffff
334
335
336#define QE_INTR_TABLE_ALIGN 16
337#define QE_ALIGNMENT_OF_BD 8
338#define QE_ALIGNMENT_OF_PRAM 64
339
340
341#define QE_RISC_ALLOCATION_RISC1 0x1
342#define QE_RISC_ALLOCATION_RISC2 0x2
343#define QE_RISC_ALLOCATION_RISC3 0x4
344#define QE_RISC_ALLOCATION_RISC4 0x8
345#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
346 QE_RISC_ALLOCATION_RISC2)
347#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
348 QE_RISC_ALLOCATION_RISC2 | \
349 QE_RISC_ALLOCATION_RISC3 | \
350 QE_RISC_ALLOCATION_RISC4)
351
352
353enum qe_fltr_tbl_lookup_key_size {
354 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
355 = 0x3f,
356
357 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
358 = 0x5f,
359
360};
361
362
363enum qe_fltr_largest_external_tbl_lookup_key_size {
364 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
365 = 0x0,
366 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
367 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES,
368 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
369 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES,
370};
371
372
373struct qe_timer_tables {
374 u16 tm_base;
375 u16 tm_ptr;
376 u16 r_tmr;
377 u16 r_tmv;
378 u32 tm_cmd;
379 u32 tm_cnt;
380} __attribute__ ((packed));
381
382#define QE_FLTR_TAD_SIZE 8
383
384
385struct qe_fltr_tad {
386 u8 serialized[QE_FLTR_TAD_SIZE];
387} __attribute__ ((packed));
388
389
390enum comm_dir {
391 COMM_DIR_NONE = 0,
392 COMM_DIR_RX = 1,
393 COMM_DIR_TX = 2,
394 COMM_DIR_RX_AND_TX = 3
395};
396
397
398
399
400
401#define QE_CMXUCR_MII_ENET_MNG 0x00007000
402#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
403#define QE_CMXUCR_GRANT 0x00008000
404#define QE_CMXUCR_TSA 0x00004000
405#define QE_CMXUCR_BKPT 0x00000100
406#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
407
408
409
410#define QE_CMXGCR_MII_ENET_MNG 0x00007000
411#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
412#define QE_CMXGCR_USBCS 0x0000000f
413#define QE_CMXGCR_USBCS_CLK3 0x1
414#define QE_CMXGCR_USBCS_CLK5 0x2
415#define QE_CMXGCR_USBCS_CLK7 0x3
416#define QE_CMXGCR_USBCS_CLK9 0x4
417#define QE_CMXGCR_USBCS_CLK13 0x5
418#define QE_CMXGCR_USBCS_CLK17 0x6
419#define QE_CMXGCR_USBCS_CLK19 0x7
420#define QE_CMXGCR_USBCS_CLK21 0x8
421#define QE_CMXGCR_USBCS_BRG9 0x9
422#define QE_CMXGCR_USBCS_BRG10 0xa
423
424
425
426#define QE_CR_FLG 0x00010000
427#define QE_RESET 0x80000000
428#define QE_INIT_TX_RX 0x00000000
429#define QE_INIT_RX 0x00000001
430#define QE_INIT_TX 0x00000002
431#define QE_ENTER_HUNT_MODE 0x00000003
432#define QE_STOP_TX 0x00000004
433#define QE_GRACEFUL_STOP_TX 0x00000005
434#define QE_RESTART_TX 0x00000006
435#define QE_CLOSE_RX_BD 0x00000007
436#define QE_SWITCH_COMMAND 0x00000007
437#define QE_SET_GROUP_ADDRESS 0x00000008
438#define QE_START_IDMA 0x00000009
439#define QE_MCC_STOP_RX 0x00000009
440#define QE_ATM_TRANSMIT 0x0000000a
441#define QE_HPAC_CLEAR_ALL 0x0000000b
442#define QE_GRACEFUL_STOP_RX 0x0000001a
443#define QE_RESTART_RX 0x0000001b
444#define QE_HPAC_SET_PRIORITY 0x0000010b
445#define QE_HPAC_STOP_TX 0x0000020b
446#define QE_HPAC_STOP_RX 0x0000030b
447#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
448#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
449#define QE_HPAC_START_TX 0x0000060b
450#define QE_HPAC_START_RX 0x0000070b
451#define QE_USB_STOP_TX 0x0000000a
452#define QE_USB_RESTART_TX 0x0000000c
453#define QE_QMC_STOP_TX 0x0000000c
454#define QE_QMC_STOP_RX 0x0000000d
455#define QE_SS7_SU_FIL_RESET 0x0000000e
456
457#define QE_RESET_BCS 0x0000000a
458#define QE_MCC_INIT_TX_RX_16 0x00000003
459#define QE_MCC_STOP_TX 0x00000004
460#define QE_MCC_INIT_TX_1 0x00000005
461#define QE_MCC_INIT_RX_1 0x00000006
462#define QE_MCC_RESET 0x00000007
463#define QE_SET_TIMER 0x00000008
464#define QE_RANDOM_NUMBER 0x0000000c
465#define QE_ATM_MULTI_THREAD_INIT 0x00000011
466#define QE_ASSIGN_PAGE 0x00000012
467#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
468#define QE_START_FLOW_CONTROL 0x00000014
469#define QE_STOP_FLOW_CONTROL 0x00000015
470#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
471
472#define QE_ASSIGN_RISC 0x00000010
473#define QE_CR_MCN_NORMAL_SHIFT 6
474#define QE_CR_MCN_USB_SHIFT 4
475#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
476#define QE_CR_SNUM_SHIFT 17
477
478
479
480#define QE_CR_SUBBLOCK_INVALID 0x00000000
481#define QE_CR_SUBBLOCK_USB 0x03200000
482#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
483#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
484#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
485#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
486#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
487#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
488#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
489#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
490#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
491#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
492#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
493#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
494#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
495#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
496#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
497#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
498#define QE_CR_SUBBLOCK_MCC1 0x03800000
499#define QE_CR_SUBBLOCK_MCC2 0x03a00000
500#define QE_CR_SUBBLOCK_MCC3 0x03000000
501#define QE_CR_SUBBLOCK_IDMA1 0x02800000
502#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
503#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
504#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
505#define QE_CR_SUBBLOCK_HPAC 0x01e00000
506#define QE_CR_SUBBLOCK_SPI1 0x01400000
507#define QE_CR_SUBBLOCK_SPI2 0x01600000
508#define QE_CR_SUBBLOCK_RAND 0x01c00000
509#define QE_CR_SUBBLOCK_TIMER 0x01e00000
510#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
511
512
513#define QE_CR_PROTOCOL_UNSPECIFIED 0x00
514#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
515#define QE_CR_PROTOCOL_QMC 0x02
516#define QE_CR_PROTOCOL_UART 0x04
517#define QE_CR_PROTOCOL_ATM_POS 0x0A
518#define QE_CR_PROTOCOL_ETHERNET 0x0C
519#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
520
521
522#define QE_BRGC_ENABLE 0x00010000
523#define QE_BRGC_DIVISOR_SHIFT 1
524#define QE_BRGC_DIVISOR_MAX 0xFFF
525#define QE_BRGC_DIV16 1
526
527
528#define QE_GTCFR1_PCAS 0x80
529#define QE_GTCFR1_STP2 0x20
530#define QE_GTCFR1_RST2 0x10
531#define QE_GTCFR1_GM2 0x08
532#define QE_GTCFR1_GM1 0x04
533#define QE_GTCFR1_STP1 0x02
534#define QE_GTCFR1_RST1 0x01
535
536
537#define QE_SDSR_BER1 0x02000000
538#define QE_SDSR_BER2 0x01000000
539
540#define QE_SDMR_GLB_1_MSK 0x80000000
541#define QE_SDMR_ADR_SEL 0x20000000
542#define QE_SDMR_BER1_MSK 0x02000000
543#define QE_SDMR_BER2_MSK 0x01000000
544#define QE_SDMR_EB1_MSK 0x00800000
545#define QE_SDMR_ER1_MSK 0x00080000
546#define QE_SDMR_ER2_MSK 0x00040000
547#define QE_SDMR_CEN_MASK 0x0000E000
548#define QE_SDMR_SBER_1 0x00000200
549#define QE_SDMR_SBER_2 0x00000200
550#define QE_SDMR_EB1_PR_MASK 0x000000C0
551#define QE_SDMR_ER1_PR 0x00000008
552
553#define QE_SDMR_CEN_SHIFT 13
554#define QE_SDMR_EB1_PR_SHIFT 6
555
556#define QE_SDTM_MSNUM_SHIFT 24
557
558#define QE_SDEBCR_BA_MASK 0x01FFFFFF
559
560
561#define QE_CP_CERCR_MEE 0x8000
562#define QE_CP_CERCR_IEE 0x4000
563#define QE_CP_CERCR_CIR 0x0800
564
565
566#define QE_IRAM_IADD_AIE 0x80000000
567#define QE_IRAM_IADD_BADDR 0x00080000
568#define QE_IRAM_READY 0x80000000
569
570
571#define UPGCR_PROTOCOL 0x80000000
572#define UPGCR_TMS 0x40000000
573#define UPGCR_RMS 0x20000000
574#define UPGCR_ADDR 0x10000000
575#define UPGCR_DIAG 0x01000000
576
577
578#define UCC_GUEMR_MODE_MASK_RX 0x02
579#define UCC_GUEMR_MODE_FAST_RX 0x02
580#define UCC_GUEMR_MODE_SLOW_RX 0x00
581#define UCC_GUEMR_MODE_MASK_TX 0x01
582#define UCC_GUEMR_MODE_FAST_TX 0x01
583#define UCC_GUEMR_MODE_SLOW_TX 0x00
584#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
585#define UCC_GUEMR_SET_RESERVED3 0x10
586
587
588
589struct ucc_slow_pram {
590 __be16 rbase;
591 __be16 tbase;
592 u8 rbmr;
593 u8 tbmr;
594 __be16 mrblr;
595 __be32 rstate;
596 __be32 rptr;
597 __be16 rbptr;
598 __be16 rcount;
599 __be32 rtemp;
600 __be32 tstate;
601 __be32 tptr;
602 __be16 tbptr;
603 __be16 tcount;
604 __be32 ttemp;
605 __be32 rcrc;
606 __be32 tcrc;
607} __attribute__ ((packed));
608
609
610#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
611#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
612#define UCC_SLOW_GUMR_H_REVD 0x00002000
613#define UCC_SLOW_GUMR_H_TRX 0x00001000
614#define UCC_SLOW_GUMR_H_TTX 0x00000800
615#define UCC_SLOW_GUMR_H_CDP 0x00000400
616#define UCC_SLOW_GUMR_H_CTSP 0x00000200
617#define UCC_SLOW_GUMR_H_CDS 0x00000100
618#define UCC_SLOW_GUMR_H_CTSS 0x00000080
619#define UCC_SLOW_GUMR_H_TFL 0x00000040
620#define UCC_SLOW_GUMR_H_RFW 0x00000020
621#define UCC_SLOW_GUMR_H_TXSY 0x00000010
622#define UCC_SLOW_GUMR_H_4SYNC 0x00000004
623#define UCC_SLOW_GUMR_H_8SYNC 0x00000008
624#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
625#define UCC_SLOW_GUMR_H_RTSM 0x00000002
626#define UCC_SLOW_GUMR_H_RSYN 0x00000001
627
628#define UCC_SLOW_GUMR_L_TCI 0x10000000
629#define UCC_SLOW_GUMR_L_RINV 0x02000000
630#define UCC_SLOW_GUMR_L_TINV 0x01000000
631#define UCC_SLOW_GUMR_L_TEND 0x00040000
632#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
633#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
634#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
635#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
636#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
637#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
638#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
639#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
640#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
641#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
642#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
643#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
644#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
645#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
646#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
647#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
648#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
649#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
650#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
651#define UCC_SLOW_GUMR_L_ENR 0x00000020
652#define UCC_SLOW_GUMR_L_ENT 0x00000010
653#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
654#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
655#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
656#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
657#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
658
659
660#define UCC_FAST_GUMR_LOOPBACK 0x40000000
661#define UCC_FAST_GUMR_TCI 0x20000000
662#define UCC_FAST_GUMR_TRX 0x10000000
663#define UCC_FAST_GUMR_TTX 0x08000000
664#define UCC_FAST_GUMR_CDP 0x04000000
665#define UCC_FAST_GUMR_CTSP 0x02000000
666#define UCC_FAST_GUMR_CDS 0x01000000
667#define UCC_FAST_GUMR_CTSS 0x00800000
668#define UCC_FAST_GUMR_TXSY 0x00020000
669#define UCC_FAST_GUMR_RSYN 0x00010000
670#define UCC_FAST_GUMR_RTSM 0x00002000
671#define UCC_FAST_GUMR_REVD 0x00000400
672#define UCC_FAST_GUMR_ENR 0x00000020
673#define UCC_FAST_GUMR_ENT 0x00000010
674
675
676#define UCC_UART_UCCE_AB 0x0200
677#define UCC_UART_UCCE_IDLE 0x0100
678#define UCC_UART_UCCE_GRA 0x0080
679#define UCC_UART_UCCE_BRKE 0x0040
680#define UCC_UART_UCCE_BRKS 0x0020
681#define UCC_UART_UCCE_CCR 0x0008
682#define UCC_UART_UCCE_BSY 0x0004
683#define UCC_UART_UCCE_TX 0x0002
684#define UCC_UART_UCCE_RX 0x0001
685
686
687#define UCC_HDLC_UCCE_GLR 0x1000
688#define UCC_HDLC_UCCE_GLT 0x0800
689#define UCC_HDLC_UCCE_IDLE 0x0100
690#define UCC_HDLC_UCCE_BRKE 0x0040
691#define UCC_HDLC_UCCE_BRKS 0x0020
692#define UCC_HDLC_UCCE_TXE 0x0010
693#define UCC_HDLC_UCCE_RXF 0x0008
694#define UCC_HDLC_UCCE_BSY 0x0004
695#define UCC_HDLC_UCCE_TXB 0x0002
696#define UCC_HDLC_UCCE_RXB 0x0001
697
698
699#define UCC_BISYNC_UCCE_GRA 0x0080
700#define UCC_BISYNC_UCCE_TXE 0x0010
701#define UCC_BISYNC_UCCE_RCH 0x0008
702#define UCC_BISYNC_UCCE_BSY 0x0004
703#define UCC_BISYNC_UCCE_TXB 0x0002
704#define UCC_BISYNC_UCCE_RXB 0x0001
705
706
707#define UCC_GETH_UCCE_MPD 0x80000000
708#define UCC_GETH_UCCE_SCAR 0x40000000
709#define UCC_GETH_UCCE_GRA 0x20000000
710#define UCC_GETH_UCCE_CBPR 0x10000000
711#define UCC_GETH_UCCE_BSY 0x08000000
712#define UCC_GETH_UCCE_RXC 0x04000000
713#define UCC_GETH_UCCE_TXC 0x02000000
714#define UCC_GETH_UCCE_TXE 0x01000000
715#define UCC_GETH_UCCE_TXB7 0x00800000
716#define UCC_GETH_UCCE_TXB6 0x00400000
717#define UCC_GETH_UCCE_TXB5 0x00200000
718#define UCC_GETH_UCCE_TXB4 0x00100000
719#define UCC_GETH_UCCE_TXB3 0x00080000
720#define UCC_GETH_UCCE_TXB2 0x00040000
721#define UCC_GETH_UCCE_TXB1 0x00020000
722#define UCC_GETH_UCCE_TXB0 0x00010000
723#define UCC_GETH_UCCE_RXB7 0x00008000
724#define UCC_GETH_UCCE_RXB6 0x00004000
725#define UCC_GETH_UCCE_RXB5 0x00002000
726#define UCC_GETH_UCCE_RXB4 0x00001000
727#define UCC_GETH_UCCE_RXB3 0x00000800
728#define UCC_GETH_UCCE_RXB2 0x00000400
729#define UCC_GETH_UCCE_RXB1 0x00000200
730#define UCC_GETH_UCCE_RXB0 0x00000100
731#define UCC_GETH_UCCE_RXF7 0x00000080
732#define UCC_GETH_UCCE_RXF6 0x00000040
733#define UCC_GETH_UCCE_RXF5 0x00000020
734#define UCC_GETH_UCCE_RXF4 0x00000010
735#define UCC_GETH_UCCE_RXF3 0x00000008
736#define UCC_GETH_UCCE_RXF2 0x00000004
737#define UCC_GETH_UCCE_RXF1 0x00000002
738#define UCC_GETH_UCCE_RXF0 0x00000001
739
740
741#define UCC_UART_UPSMR_FLC 0x8000
742#define UCC_UART_UPSMR_SL 0x4000
743#define UCC_UART_UPSMR_CL_MASK 0x3000
744#define UCC_UART_UPSMR_CL_8 0x3000
745#define UCC_UART_UPSMR_CL_7 0x2000
746#define UCC_UART_UPSMR_CL_6 0x1000
747#define UCC_UART_UPSMR_CL_5 0x0000
748#define UCC_UART_UPSMR_UM_MASK 0x0c00
749#define UCC_UART_UPSMR_UM_NORMAL 0x0000
750#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
751#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
752#define UCC_UART_UPSMR_FRZ 0x0200
753#define UCC_UART_UPSMR_RZS 0x0100
754#define UCC_UART_UPSMR_SYN 0x0080
755#define UCC_UART_UPSMR_DRT 0x0040
756#define UCC_UART_UPSMR_PEN 0x0010
757#define UCC_UART_UPSMR_RPM_MASK 0x000c
758#define UCC_UART_UPSMR_RPM_ODD 0x0000
759#define UCC_UART_UPSMR_RPM_LOW 0x0004
760#define UCC_UART_UPSMR_RPM_EVEN 0x0008
761#define UCC_UART_UPSMR_RPM_HIGH 0x000C
762#define UCC_UART_UPSMR_TPM_MASK 0x0003
763#define UCC_UART_UPSMR_TPM_ODD 0x0000
764#define UCC_UART_UPSMR_TPM_LOW 0x0001
765#define UCC_UART_UPSMR_TPM_EVEN 0x0002
766#define UCC_UART_UPSMR_TPM_HIGH 0x0003
767
768
769#define UCC_GETH_UPSMR_FTFE 0x80000000
770#define UCC_GETH_UPSMR_PTPE 0x40000000
771#define UCC_GETH_UPSMR_ECM 0x04000000
772#define UCC_GETH_UPSMR_HSE 0x02000000
773#define UCC_GETH_UPSMR_PRO 0x00400000
774#define UCC_GETH_UPSMR_CAP 0x00200000
775#define UCC_GETH_UPSMR_RSH 0x00100000
776#define UCC_GETH_UPSMR_RPM 0x00080000
777#define UCC_GETH_UPSMR_R10M 0x00040000
778#define UCC_GETH_UPSMR_RLPB 0x00020000
779#define UCC_GETH_UPSMR_TBIM 0x00010000
780#define UCC_GETH_UPSMR_RES1 0x00002000
781#define UCC_GETH_UPSMR_RMM 0x00001000
782#define UCC_GETH_UPSMR_CAM 0x00000400
783#define UCC_GETH_UPSMR_BRO 0x00000200
784#define UCC_GETH_UPSMR_SMM 0x00000080
785#define UCC_GETH_UPSMR_SGMM 0x00000020
786
787
788#define UCC_SLOW_TOD 0x8000
789#define UCC_FAST_TOD 0x8000
790
791
792
793#define UCC_BMR_GBL 0x20
794#define UCC_BMR_BO_BE 0x10
795#define UCC_BMR_CETM 0x04
796#define UCC_BMR_DTB 0x02
797#define UCC_BMR_BDB 0x01
798
799
800#define FC_GBL 0x20
801#define FC_DTB_LCL 0x02
802#define UCC_FAST_FUNCTION_CODE_GBL 0x20
803#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
804#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
805
806#endif
807#endif
808