1/* 2 * Xilinx Controls Header 3 * 4 * Copyright (C) 2013-2015 Ideas on Board 5 * Copyright (C) 2013-2015 Xilinx, Inc. 6 * 7 * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> 8 * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 9 * 10 * This software is licensed under the terms of the GNU General Public 11 * License version 2, as published by the Free Software Foundation, and 12 * may be copied, distributed, and modified under those terms. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20#ifndef __UAPI_XILINX_V4L2_CONTROLS_H__ 21#define __UAPI_XILINX_V4L2_CONTROLS_H__ 22 23#include <linux/v4l2-controls.h> 24 25#define V4L2_CID_XILINX_OFFSET 0xc000 26#define V4L2_CID_XILINX_BASE (V4L2_CID_USER_BASE + V4L2_CID_XILINX_OFFSET) 27 28/* 29 * Private Controls for Xilinx Video IPs 30 */ 31 32/* 33 * Xilinx TPG Video IP 34 */ 35 36#define V4L2_CID_XILINX_TPG (V4L2_CID_USER_BASE + 0xc000) 37 38/* Draw cross hairs */ 39#define V4L2_CID_XILINX_TPG_CROSS_HAIRS (V4L2_CID_XILINX_TPG + 1) 40/* Enable a moving box */ 41#define V4L2_CID_XILINX_TPG_MOVING_BOX (V4L2_CID_XILINX_TPG + 2) 42/* Mask out a color component */ 43#define V4L2_CID_XILINX_TPG_COLOR_MASK (V4L2_CID_XILINX_TPG + 3) 44/* Enable a stuck pixel feature */ 45#define V4L2_CID_XILINX_TPG_STUCK_PIXEL (V4L2_CID_XILINX_TPG + 4) 46/* Enable a noisy output */ 47#define V4L2_CID_XILINX_TPG_NOISE (V4L2_CID_XILINX_TPG + 5) 48/* Enable the motion feature */ 49#define V4L2_CID_XILINX_TPG_MOTION (V4L2_CID_XILINX_TPG + 6) 50/* Configure the motion speed of moving patterns */ 51#define V4L2_CID_XILINX_TPG_MOTION_SPEED (V4L2_CID_XILINX_TPG + 7) 52/* The row of horizontal cross hair location */ 53#define V4L2_CID_XILINX_TPG_CROSS_HAIR_ROW (V4L2_CID_XILINX_TPG + 8) 54/* The colum of vertical cross hair location */ 55#define V4L2_CID_XILINX_TPG_CROSS_HAIR_COLUMN (V4L2_CID_XILINX_TPG + 9) 56/* Set starting point of sine wave for horizontal component */ 57#define V4L2_CID_XILINX_TPG_ZPLATE_HOR_START (V4L2_CID_XILINX_TPG + 10) 58/* Set speed of the horizontal component */ 59#define V4L2_CID_XILINX_TPG_ZPLATE_HOR_SPEED (V4L2_CID_XILINX_TPG + 11) 60/* Set starting point of sine wave for vertical component */ 61#define V4L2_CID_XILINX_TPG_ZPLATE_VER_START (V4L2_CID_XILINX_TPG + 12) 62/* Set speed of the vertical component */ 63#define V4L2_CID_XILINX_TPG_ZPLATE_VER_SPEED (V4L2_CID_XILINX_TPG + 13) 64/* Moving box size */ 65#define V4L2_CID_XILINX_TPG_BOX_SIZE (V4L2_CID_XILINX_TPG + 14) 66/* Moving box color */ 67#define V4L2_CID_XILINX_TPG_BOX_COLOR (V4L2_CID_XILINX_TPG + 15) 68/* Upper limit count of generated stuck pixels */ 69#define V4L2_CID_XILINX_TPG_STUCK_PIXEL_THRESH (V4L2_CID_XILINX_TPG + 16) 70/* Noise level */ 71#define V4L2_CID_XILINX_TPG_NOISE_GAIN (V4L2_CID_XILINX_TPG + 17) 72/* Foreground pattern (HLS)*/ 73#define V4L2_CID_XILINX_TPG_HLS_FG_PATTERN (V4L2_CID_XILINX_TPG + 18) 74 75/* 76 * Xilinx CRESAMPLE Video IP 77 */ 78 79#define V4L2_CID_XILINX_CRESAMPLE (V4L2_CID_USER_BASE + 0xc020) 80 81/* The field parity for interlaced video */ 82#define V4L2_CID_XILINX_CRESAMPLE_FIELD_PARITY (V4L2_CID_XILINX_CRESAMPLE + 1) 83/* Specify if the first line of video contains the Chroma information */ 84#define V4L2_CID_XILINX_CRESAMPLE_CHROMA_PARITY (V4L2_CID_XILINX_CRESAMPLE + 2) 85 86/* 87 * Xilinx RGB2YUV Video IPs 88 */ 89 90#define V4L2_CID_XILINX_RGB2YUV (V4L2_CID_USER_BASE + 0xc040) 91 92/* Maximum Luma(Y) value */ 93#define V4L2_CID_XILINX_RGB2YUV_YMAX (V4L2_CID_XILINX_RGB2YUV + 1) 94/* Minimum Luma(Y) value */ 95#define V4L2_CID_XILINX_RGB2YUV_YMIN (V4L2_CID_XILINX_RGB2YUV + 2) 96/* Maximum Cb Chroma value */ 97#define V4L2_CID_XILINX_RGB2YUV_CBMAX (V4L2_CID_XILINX_RGB2YUV + 3) 98/* Minimum Cb Chroma value */ 99#define V4L2_CID_XILINX_RGB2YUV_CBMIN (V4L2_CID_XILINX_RGB2YUV + 4) 100/* Maximum Cr Chroma value */ 101#define V4L2_CID_XILINX_RGB2YUV_CRMAX (V4L2_CID_XILINX_RGB2YUV + 5) 102/* Minimum Cr Chroma value */ 103#define V4L2_CID_XILINX_RGB2YUV_CRMIN (V4L2_CID_XILINX_RGB2YUV + 6) 104/* The offset compensation value for Luma(Y) */ 105#define V4L2_CID_XILINX_RGB2YUV_YOFFSET (V4L2_CID_XILINX_RGB2YUV + 7) 106/* The offset compensation value for Cb Chroma */ 107#define V4L2_CID_XILINX_RGB2YUV_CBOFFSET (V4L2_CID_XILINX_RGB2YUV + 8) 108/* The offset compensation value for Cr Chroma */ 109#define V4L2_CID_XILINX_RGB2YUV_CROFFSET (V4L2_CID_XILINX_RGB2YUV + 9) 110 111/* Y = CA * R + (1 - CA - CB) * G + CB * B */ 112 113/* CA coefficient */ 114#define V4L2_CID_XILINX_RGB2YUV_ACOEF (V4L2_CID_XILINX_RGB2YUV + 10) 115/* CB coefficient */ 116#define V4L2_CID_XILINX_RGB2YUV_BCOEF (V4L2_CID_XILINX_RGB2YUV + 11) 117/* CC coefficient */ 118#define V4L2_CID_XILINX_RGB2YUV_CCOEF (V4L2_CID_XILINX_RGB2YUV + 12) 119/* CD coefficient */ 120#define V4L2_CID_XILINX_RGB2YUV_DCOEF (V4L2_CID_XILINX_RGB2YUV + 13) 121 122/* 123 * Xilinx HLS Video IP 124 */ 125 126#define V4L2_CID_XILINX_HLS (V4L2_CID_USER_BASE + 0xc060) 127 128/* The IP model */ 129#define V4L2_CID_XILINX_HLS_MODEL (V4L2_CID_XILINX_HLS + 1) 130 131/* 132 * Xilinx MIPI CSI2 Rx Subsystem 133 */ 134 135/* Base ID */ 136#define V4L2_CID_XILINX_MIPICSISS (V4L2_CID_USER_BASE + 0xc080) 137 138/* Active Lanes */ 139#define V4L2_CID_XILINX_MIPICSISS_ACT_LANES (V4L2_CID_XILINX_MIPICSISS + 1) 140/* Frames received since streaming is set */ 141#define V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER (V4L2_CID_XILINX_MIPICSISS + 2) 142/* Reset all event counters */ 143#define V4L2_CID_XILINX_MIPICSISS_RESET_COUNTERS (V4L2_CID_XILINX_MIPICSISS + 3) 144 145/* 146 * Xilinx Gamma Correction IP 147 */ 148 149/* Base ID */ 150#define V4L2_CID_XILINX_GAMMA_CORR (V4L2_CID_USER_BASE + 0xc0c0) 151/* Adjust Red Gamma */ 152#define V4L2_CID_XILINX_GAMMA_CORR_RED_GAMMA (V4L2_CID_XILINX_GAMMA_CORR + 1) 153/* Adjust Blue Gamma */ 154#define V4L2_CID_XILINX_GAMMA_CORR_BLUE_GAMMA (V4L2_CID_XILINX_GAMMA_CORR + 2) 155/* Adjust Green Gamma */ 156#define V4L2_CID_XILINX_GAMMA_CORR_GREEN_GAMMA (V4L2_CID_XILINX_GAMMA_CORR + 3) 157 158/* 159 * Xilinx Color Space Converter (CSC) VPSS 160 */ 161 162/* Base ID */ 163#define V4L2_CID_XILINX_CSC (V4L2_CID_USER_BASE + 0xc0a0) 164/* Adjust Brightness */ 165#define V4L2_CID_XILINX_CSC_BRIGHTNESS (V4L2_CID_XILINX_CSC + 1) 166/* Adjust Contrast */ 167#define V4L2_CID_XILINX_CSC_CONTRAST (V4L2_CID_XILINX_CSC + 2) 168/* Adjust Red Gain */ 169#define V4L2_CID_XILINX_CSC_RED_GAIN (V4L2_CID_XILINX_CSC + 3) 170/* Adjust Green Gain */ 171#define V4L2_CID_XILINX_CSC_GREEN_GAIN (V4L2_CID_XILINX_CSC + 4) 172/* Adjust Blue Gain */ 173#define V4L2_CID_XILINX_CSC_BLUE_GAIN (V4L2_CID_XILINX_CSC + 5) 174 175/* 176 * Xilinx SDI Rx Subsystem 177 */ 178 179/* Base ID */ 180#define V4L2_CID_XILINX_SDIRX (V4L2_CID_USER_BASE + 0xc100) 181 182/* Framer Control */ 183#define V4L2_CID_XILINX_SDIRX_FRAMER (V4L2_CID_XILINX_SDIRX + 1) 184/* Video Lock Window Control */ 185#define V4L2_CID_XILINX_SDIRX_VIDLOCK_WINDOW (V4L2_CID_XILINX_SDIRX + 2) 186/* EDH Error Mask Control */ 187#define V4L2_CID_XILINX_SDIRX_EDH_ERRCNT_ENABLE (V4L2_CID_XILINX_SDIRX + 3) 188/* Mode search Control */ 189#define V4L2_CID_XILINX_SDIRX_SEARCH_MODES (V4L2_CID_XILINX_SDIRX + 4) 190/* Get Detected Mode control */ 191#define V4L2_CID_XILINX_SDIRX_MODE_DETECT (V4L2_CID_XILINX_SDIRX + 5) 192/* Get CRC error status */ 193#define V4L2_CID_XILINX_SDIRX_CRC (V4L2_CID_XILINX_SDIRX + 6) 194/* Get EDH error count control */ 195#define V4L2_CID_XILINX_SDIRX_EDH_ERRCNT (V4L2_CID_XILINX_SDIRX + 7) 196/* Get EDH status control */ 197#define V4L2_CID_XILINX_SDIRX_EDH_STATUS (V4L2_CID_XILINX_SDIRX + 8) 198 199#endif /* __UAPI_XILINX_V4L2_CONTROLS_H__ */ 200