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17#include <linux/irqchip/arm-gic.h>
18#include <linux/kvm.h>
19#include <linux/kvm_host.h>
20#include <kvm/arm_vgic.h>
21#include <asm/kvm_mmu.h>
22
23#include "vgic.h"
24
25
26
27
28
29
30
31static unsigned long *u64_to_bitmask(u64 *val)
32{
33#if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
34 *val = (*val >> 32) | (*val << 32);
35#endif
36 return (unsigned long *)val;
37}
38
39void vgic_v2_process_maintenance(struct kvm_vcpu *vcpu)
40{
41 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
42
43 if (cpuif->vgic_misr & GICH_MISR_EOI) {
44 u64 eisr = cpuif->vgic_eisr;
45 unsigned long *eisr_bmap = u64_to_bitmask(&eisr);
46 int lr;
47
48 for_each_set_bit(lr, eisr_bmap, kvm_vgic_global_state.nr_lr) {
49 u32 intid = cpuif->vgic_lr[lr] & GICH_LR_VIRTUALID;
50
51 WARN_ON(cpuif->vgic_lr[lr] & GICH_LR_STATE);
52
53
54 if (vgic_valid_spi(vcpu->kvm, intid))
55 kvm_notify_acked_irq(vcpu->kvm, 0,
56 intid - VGIC_NR_PRIVATE_IRQS);
57 }
58 }
59
60
61 cpuif->vgic_hcr &= ~GICH_HCR_UIE;
62
63
64
65
66
67
68
69
70 cpuif->vgic_eisr = 0;
71}
72
73void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
74{
75 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
76
77 cpuif->vgic_hcr |= GICH_HCR_UIE;
78}
79
80
81
82
83
84
85
86
87void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
88{
89 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
90 int lr;
91
92 for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
93 u32 val = cpuif->vgic_lr[lr];
94 u32 intid = val & GICH_LR_VIRTUALID;
95 struct vgic_irq *irq;
96
97 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
98
99 spin_lock(&irq->irq_lock);
100
101
102 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
103
104
105 if (irq->config == VGIC_CONFIG_EDGE &&
106 (val & GICH_LR_PENDING_BIT)) {
107 irq->pending = true;
108
109 if (vgic_irq_is_sgi(intid)) {
110 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
111
112 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
113 irq->source |= (1 << cpuid);
114 }
115 }
116
117
118
119
120
121 if (irq->config == VGIC_CONFIG_LEVEL) {
122 if (!(val & GICH_LR_PENDING_BIT))
123 irq->soft_pending = false;
124
125 irq->pending = irq->line_level || irq->soft_pending;
126 }
127
128 spin_unlock(&irq->irq_lock);
129 vgic_put_irq(vcpu->kvm, irq);
130 }
131}
132
133
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142
143
144void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
145{
146 u32 val = irq->intid;
147
148 if (irq->pending) {
149 val |= GICH_LR_PENDING_BIT;
150
151 if (irq->config == VGIC_CONFIG_EDGE)
152 irq->pending = false;
153
154 if (vgic_irq_is_sgi(irq->intid)) {
155 u32 src = ffs(irq->source);
156
157 BUG_ON(!src);
158 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
159 irq->source &= ~(1 << (src - 1));
160 if (irq->source)
161 irq->pending = true;
162 }
163 }
164
165 if (irq->active)
166 val |= GICH_LR_ACTIVE_BIT;
167
168 if (irq->hw) {
169 val |= GICH_LR_HW;
170 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
171 } else {
172 if (irq->config == VGIC_CONFIG_LEVEL)
173 val |= GICH_LR_EOI;
174 }
175
176
177 val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
178
179 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
180}
181
182void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
183{
184 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
185}
186
187void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
188{
189 u32 vmcr;
190
191 vmcr = (vmcrp->ctlr << GICH_VMCR_CTRL_SHIFT) & GICH_VMCR_CTRL_MASK;
192 vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
193 GICH_VMCR_ALIAS_BINPOINT_MASK;
194 vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
195 GICH_VMCR_BINPOINT_MASK;
196 vmcr |= (vmcrp->pmr << GICH_VMCR_PRIMASK_SHIFT) &
197 GICH_VMCR_PRIMASK_MASK;
198
199 vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = vmcr;
200}
201
202void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
203{
204 u32 vmcr = vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr;
205
206 vmcrp->ctlr = (vmcr & GICH_VMCR_CTRL_MASK) >>
207 GICH_VMCR_CTRL_SHIFT;
208 vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
209 GICH_VMCR_ALIAS_BINPOINT_SHIFT;
210 vmcrp->bpr = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
211 GICH_VMCR_BINPOINT_SHIFT;
212 vmcrp->pmr = (vmcr & GICH_VMCR_PRIMASK_MASK) >>
213 GICH_VMCR_PRIMASK_SHIFT;
214}
215
216void vgic_v2_enable(struct kvm_vcpu *vcpu)
217{
218
219
220
221
222
223 vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
224 vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
225
226
227 vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
228}
229
230
231static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
232{
233 if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
234 return false;
235 if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
236 return false;
237
238 if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
239 return true;
240 if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
241 return true;
242
243 return false;
244}
245
246int vgic_v2_map_resources(struct kvm *kvm)
247{
248 struct vgic_dist *dist = &kvm->arch.vgic;
249 int ret = 0;
250
251 if (vgic_ready(kvm))
252 goto out;
253
254 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
255 IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
256 kvm_err("Need to set vgic cpu and dist addresses first\n");
257 ret = -ENXIO;
258 goto out;
259 }
260
261 if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
262 kvm_err("VGIC CPU and dist frames overlap\n");
263 ret = -EINVAL;
264 goto out;
265 }
266
267
268
269
270
271 ret = vgic_init(kvm);
272 if (ret) {
273 kvm_err("Unable to initialize VGIC dynamic data structures\n");
274 goto out;
275 }
276
277 ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
278 if (ret) {
279 kvm_err("Unable to register VGIC MMIO regions\n");
280 goto out;
281 }
282
283 if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
284 ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
285 kvm_vgic_global_state.vcpu_base,
286 KVM_VGIC_V2_CPU_SIZE, true);
287 if (ret) {
288 kvm_err("Unable to remap VGIC CPU to VCPU\n");
289 goto out;
290 }
291 }
292
293 dist->ready = true;
294
295out:
296 if (ret)
297 kvm_vgic_destroy(kvm);
298 return ret;
299}
300
301DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
302
303
304
305
306
307
308
309int vgic_v2_probe(const struct gic_kvm_info *info)
310{
311 int ret;
312 u32 vtr;
313
314 if (!info->vctrl.start) {
315 kvm_err("GICH not present in the firmware table\n");
316 return -ENXIO;
317 }
318
319 if (!PAGE_ALIGNED(info->vcpu.start) ||
320 !PAGE_ALIGNED(resource_size(&info->vcpu))) {
321 kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
322 kvm_vgic_global_state.vcpu_base_va = ioremap(info->vcpu.start,
323 resource_size(&info->vcpu));
324 if (!kvm_vgic_global_state.vcpu_base_va) {
325 kvm_err("Cannot ioremap GICV\n");
326 return -ENOMEM;
327 }
328
329 ret = create_hyp_io_mappings(kvm_vgic_global_state.vcpu_base_va,
330 kvm_vgic_global_state.vcpu_base_va + resource_size(&info->vcpu),
331 info->vcpu.start);
332 if (ret) {
333 kvm_err("Cannot map GICV into hyp\n");
334 goto out;
335 }
336
337 static_branch_enable(&vgic_v2_cpuif_trap);
338 }
339
340 kvm_vgic_global_state.vctrl_base = ioremap(info->vctrl.start,
341 resource_size(&info->vctrl));
342 if (!kvm_vgic_global_state.vctrl_base) {
343 kvm_err("Cannot ioremap GICH\n");
344 ret = -ENOMEM;
345 goto out;
346 }
347
348 vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
349 kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
350
351 ret = create_hyp_io_mappings(kvm_vgic_global_state.vctrl_base,
352 kvm_vgic_global_state.vctrl_base +
353 resource_size(&info->vctrl),
354 info->vctrl.start);
355 if (ret) {
356 kvm_err("Cannot map VCTRL into hyp\n");
357 goto out;
358 }
359
360 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
361 if (ret) {
362 kvm_err("Cannot register GICv2 KVM device\n");
363 goto out;
364 }
365
366 kvm_vgic_global_state.can_emulate_gicv2 = true;
367 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
368 kvm_vgic_global_state.type = VGIC_V2;
369 kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
370
371 kvm_info("vgic-v2@%llx\n", info->vctrl.start);
372
373 return 0;
374out:
375 if (kvm_vgic_global_state.vctrl_base)
376 iounmap(kvm_vgic_global_state.vctrl_base);
377 if (kvm_vgic_global_state.vcpu_base_va)
378 iounmap(kvm_vgic_global_state.vcpu_base_va);
379
380 return ret;
381}
382