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12#include <linux/interrupt.h>
13#include <linux/delay.h>
14#include <linux/sched.h>
15#include <linux/sched_clock.h>
16#include <linux/clk.h>
17#include <linux/clockchips.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/timecounter.h>
21#include <asm/cpuinfo.h>
22
23static void __iomem *timer_baseaddr;
24
25static unsigned int freq_div_hz;
26static unsigned int timer_clock_freq;
27
28#define TCSR0 (0x00)
29#define TLR0 (0x04)
30#define TCR0 (0x08)
31#define TCSR1 (0x10)
32#define TLR1 (0x14)
33#define TCR1 (0x18)
34
35#define TCSR_MDT (1<<0)
36#define TCSR_UDT (1<<1)
37#define TCSR_GENT (1<<2)
38#define TCSR_CAPT (1<<3)
39#define TCSR_ARHT (1<<4)
40#define TCSR_LOAD (1<<5)
41#define TCSR_ENIT (1<<6)
42#define TCSR_ENT (1<<7)
43#define TCSR_TINT (1<<8)
44#define TCSR_PWMA (1<<9)
45#define TCSR_ENALL (1<<10)
46
47static unsigned int (*read_fn)(void __iomem *);
48static void (*write_fn)(u32, void __iomem *);
49
50static void timer_write32(u32 val, void __iomem *addr)
51{
52 iowrite32(val, addr);
53}
54
55static unsigned int timer_read32(void __iomem *addr)
56{
57 return ioread32(addr);
58}
59
60static void timer_write32_be(u32 val, void __iomem *addr)
61{
62 iowrite32be(val, addr);
63}
64
65static unsigned int timer_read32_be(void __iomem *addr)
66{
67 return ioread32be(addr);
68}
69
70static inline void xilinx_timer0_stop(void)
71{
72 write_fn(read_fn(timer_baseaddr + TCSR0) & ~TCSR_ENT,
73 timer_baseaddr + TCSR0);
74}
75
76static inline void xilinx_timer0_start_periodic(unsigned long load_val)
77{
78 if (!load_val)
79 load_val = 1;
80
81 write_fn(load_val, timer_baseaddr + TLR0);
82
83
84 write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
85
86
87
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89
90
91
92
93
94
95
96
97
98
99 write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
100 timer_baseaddr + TCSR0);
101}
102
103static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
104{
105 if (!load_val)
106 load_val = 1;
107
108 write_fn(load_val, timer_baseaddr + TLR0);
109
110
111 write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
112
113 write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
114 timer_baseaddr + TCSR0);
115}
116
117static int xilinx_timer_set_next_event(unsigned long delta,
118 struct clock_event_device *dev)
119{
120 pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
121 xilinx_timer0_start_oneshot(delta);
122 return 0;
123}
124
125static int xilinx_timer_shutdown(struct clock_event_device *evt)
126{
127 pr_info("%s\n", __func__);
128 xilinx_timer0_stop();
129 return 0;
130}
131
132static int xilinx_timer_set_periodic(struct clock_event_device *evt)
133{
134 pr_info("%s\n", __func__);
135 xilinx_timer0_start_periodic(freq_div_hz);
136 return 0;
137}
138
139static struct clock_event_device clockevent_xilinx_timer = {
140 .name = "xilinx_clockevent",
141 .features = CLOCK_EVT_FEAT_ONESHOT |
142 CLOCK_EVT_FEAT_PERIODIC,
143 .shift = 8,
144 .rating = 300,
145 .set_next_event = xilinx_timer_set_next_event,
146 .set_state_shutdown = xilinx_timer_shutdown,
147 .set_state_periodic = xilinx_timer_set_periodic,
148};
149
150static inline void timer_ack(void)
151{
152 write_fn(read_fn(timer_baseaddr + TCSR0), timer_baseaddr + TCSR0);
153}
154
155static irqreturn_t timer_interrupt(int irq, void *dev_id)
156{
157 struct clock_event_device *evt = &clockevent_xilinx_timer;
158#ifdef CONFIG_HEART_BEAT
159 microblaze_heartbeat();
160#endif
161 timer_ack();
162 evt->event_handler(evt);
163 return IRQ_HANDLED;
164}
165
166static struct irqaction timer_irqaction = {
167 .handler = timer_interrupt,
168 .flags = IRQF_TIMER,
169 .name = "timer",
170 .dev_id = &clockevent_xilinx_timer,
171};
172
173static __init int xilinx_clockevent_init(void)
174{
175 clockevent_xilinx_timer.mult =
176 div_sc(timer_clock_freq, NSEC_PER_SEC,
177 clockevent_xilinx_timer.shift);
178 clockevent_xilinx_timer.max_delta_ns =
179 clockevent_delta2ns((u32)~0, &clockevent_xilinx_timer);
180 clockevent_xilinx_timer.min_delta_ns =
181 clockevent_delta2ns(1, &clockevent_xilinx_timer);
182 clockevent_xilinx_timer.cpumask = cpumask_of(0);
183 clockevents_register_device(&clockevent_xilinx_timer);
184
185 return 0;
186}
187
188static u64 xilinx_clock_read(void)
189{
190 return read_fn(timer_baseaddr + TCR1);
191}
192
193static cycle_t xilinx_read(struct clocksource *cs)
194{
195
196 return (cycle_t)xilinx_clock_read();
197}
198
199static struct timecounter xilinx_tc = {
200 .cc = NULL,
201};
202
203static cycle_t xilinx_cc_read(const struct cyclecounter *cc)
204{
205 return xilinx_read(NULL);
206}
207
208static struct cyclecounter xilinx_cc = {
209 .read = xilinx_cc_read,
210 .mask = CLOCKSOURCE_MASK(32),
211 .shift = 8,
212};
213
214static int __init init_xilinx_timecounter(void)
215{
216 xilinx_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC,
217 xilinx_cc.shift);
218
219 timecounter_init(&xilinx_tc, &xilinx_cc, sched_clock());
220
221 return 0;
222}
223
224static struct clocksource clocksource_microblaze = {
225 .name = "xilinx_clocksource",
226 .rating = 300,
227 .read = xilinx_read,
228 .mask = CLOCKSOURCE_MASK(32),
229 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
230};
231
232static int __init xilinx_clocksource_init(void)
233{
234 int ret;
235
236 ret = clocksource_register_hz(&clocksource_microblaze,
237 timer_clock_freq);
238 if (ret) {
239 pr_err("failed to register clocksource");
240 return ret;
241 }
242
243
244 write_fn(read_fn(timer_baseaddr + TCSR1) & ~TCSR_ENT,
245 timer_baseaddr + TCSR1);
246
247 write_fn(TCSR_TINT|TCSR_ENT|TCSR_ARHT, timer_baseaddr + TCSR1);
248
249
250 return init_xilinx_timecounter();
251}
252
253static int __init xilinx_timer_init(struct device_node *timer)
254{
255 struct clk *clk;
256 static int initialized;
257 u32 irq;
258 u32 timer_num = 1;
259 int ret;
260
261 if (initialized)
262 return -EINVAL;
263
264 initialized = 1;
265
266 timer_baseaddr = of_iomap(timer, 0);
267 if (!timer_baseaddr) {
268 pr_err("ERROR: invalid timer base address\n");
269 return -ENXIO;
270 }
271
272 write_fn = timer_write32;
273 read_fn = timer_read32;
274
275 write_fn(TCSR_MDT, timer_baseaddr + TCSR0);
276 if (!(read_fn(timer_baseaddr + TCSR0) & TCSR_MDT)) {
277 write_fn = timer_write32_be;
278 read_fn = timer_read32_be;
279 }
280
281 irq = irq_of_parse_and_map(timer, 0);
282 if (irq <= 0) {
283 pr_err("Failed to parse and map irq");
284 return -EINVAL;
285 }
286
287 of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num);
288 if (timer_num) {
289 pr_err("Please enable two timers in HW\n");
290 return -EINVAL;
291 }
292
293 pr_info("%s: irq=%d\n", timer->full_name, irq);
294
295 clk = of_clk_get(timer, 0);
296 if (IS_ERR(clk)) {
297 pr_err("ERROR: timer CCF input clock not found\n");
298
299 of_property_read_u32(timer, "clock-frequency",
300 &timer_clock_freq);
301 } else {
302 timer_clock_freq = clk_get_rate(clk);
303 }
304
305 if (!timer_clock_freq) {
306 pr_err("ERROR: Using CPU clock frequency\n");
307 timer_clock_freq = cpuinfo.cpu_clock_freq;
308 }
309
310 freq_div_hz = timer_clock_freq / HZ;
311
312 ret = setup_irq(irq, &timer_irqaction);
313 if (ret) {
314 pr_err("Failed to setup IRQ");
315 return ret;
316 }
317
318#ifdef CONFIG_HEART_BEAT
319 microblaze_setup_heartbeat();
320#endif
321
322 ret = xilinx_clocksource_init();
323 if (ret)
324 return ret;
325
326 ret = xilinx_clockevent_init();
327 if (ret)
328 return ret;
329
330 sched_clock_register(xilinx_clock_read, 32, timer_clock_freq);
331
332 return 0;
333}
334
335CLOCKSOURCE_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a",
336 xilinx_timer_init);
337
