LXR linux/arch/mips/include/asm/mach-loongson64/irq.h

   1#ifndef __ASM_MACH_LOONGSON64_IRQ_H_
   2#define __ASM_MACH_LOONGSON64_IRQ_H_
   3
   4#include <boot_param.h>
   5
   6#ifdef CONFIG_CPU_LOONGSON3
   7
   8/* cpu core interrupt numbers */
   9#define MIPS_CPU_IRQ_BASE 56
  10
  11#define LOONGSON_UART_IRQ   (MIPS_CPU_IRQ_BASE + 2) /* UART */
  12#define LOONGSON_HT1_IRQ    (MIPS_CPU_IRQ_BASE + 3) /* HT1 */
  13#define LOONGSON_TIMER_IRQ  (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
  14
  15#define LOONGSON_HT1_CFG_BASE           loongson_sysconf.ht_control_base
  16#define LOONGSON_HT1_INT_VECTOR_BASE    (LOONGSON_HT1_CFG_BASE + 0x80)
  17#define LOONGSON_HT1_INT_EN_BASE        (LOONGSON_HT1_CFG_BASE + 0xa0)
  18#define LOONGSON_HT1_INT_VECTOR(n)      \
  19                LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * (n))
  20#define LOONGSON_HT1_INTN_EN(n)         \
  21                LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * (n))
  22
  23#define LOONGSON_INT_ROUTER_OFFSET      0x1400
  24#define LOONGSON_INT_ROUTER_INTEN       \
  25          LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24)
  26#define LOONGSON_INT_ROUTER_INTENSET    \
  27          LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28)
  28#define LOONGSON_INT_ROUTER_INTENCLR    \
  29          LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c)
  30#define LOONGSON_INT_ROUTER_ENTRY(n)    \
  31          LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n)
  32#define LOONGSON_INT_ROUTER_LPC         LOONGSON_INT_ROUTER_ENTRY(0x0a)
  33#define LOONGSON_INT_ROUTER_HT1(n)      LOONGSON_INT_ROUTER_ENTRY(n + 0x18)
  34
  35#define LOONGSON_INT_COREx_INTy(x, y)   (1<<(x) | 1<<(y+4))     /* route to int y of core x */
  36
  37#endif
  38
  39extern void fixup_irqs(void);
  40extern void loongson3_ipi_interrupt(struct pt_regs *regs);
  41
  42#include_next <irq.h>
  43#endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */
  44