1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#include <linux/clk-provider.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/platform_device.h>
27#include <linux/slab.h>
28
29#define TBG_SEL 0x0
30#define DIV_SEL0 0x4
31#define DIV_SEL1 0x8
32#define DIV_SEL2 0xC
33#define CLK_SEL 0x10
34#define CLK_DIS 0x14
35
36struct clk_periph_driver_data {
37 struct clk_hw_onecell_data *hw_data;
38 spinlock_t lock;
39};
40
41struct clk_double_div {
42 struct clk_hw hw;
43 void __iomem *reg1;
44 u8 shift1;
45 void __iomem *reg2;
46 u8 shift2;
47};
48
49#define to_clk_double_div(_hw) container_of(_hw, struct clk_double_div, hw)
50
51struct clk_periph_data {
52 const char *name;
53 const char * const *parent_names;
54 int num_parents;
55 struct clk_hw *mux_hw;
56 struct clk_hw *rate_hw;
57 struct clk_hw *gate_hw;
58 bool is_double_div;
59};
60
61static const struct clk_div_table clk_table6[] = {
62 { .val = 1, .div = 1, },
63 { .val = 2, .div = 2, },
64 { .val = 3, .div = 3, },
65 { .val = 4, .div = 4, },
66 { .val = 5, .div = 5, },
67 { .val = 6, .div = 6, },
68 { .val = 0, .div = 0, },
69};
70
71static const struct clk_div_table clk_table1[] = {
72 { .val = 0, .div = 1, },
73 { .val = 1, .div = 2, },
74 { .val = 0, .div = 0, },
75};
76
77static const struct clk_div_table clk_table2[] = {
78 { .val = 0, .div = 2, },
79 { .val = 1, .div = 4, },
80 { .val = 0, .div = 0, },
81};
82static const struct clk_ops clk_double_div_ops;
83
84#define PERIPH_GATE(_name, _bit) \
85struct clk_gate gate_##_name = { \
86 .reg = (void *)CLK_DIS, \
87 .bit_idx = _bit, \
88 .hw.init = &(struct clk_init_data){ \
89 .ops = &clk_gate_ops, \
90 } \
91};
92
93#define PERIPH_MUX(_name, _shift) \
94struct clk_mux mux_##_name = { \
95 .reg = (void *)TBG_SEL, \
96 .shift = _shift, \
97 .mask = 3, \
98 .hw.init = &(struct clk_init_data){ \
99 .ops = &clk_mux_ro_ops, \
100 } \
101};
102
103#define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \
104struct clk_double_div rate_##_name = { \
105 .reg1 = (void *)_reg1, \
106 .reg2 = (void *)_reg2, \
107 .shift1 = _shift1, \
108 .shift2 = _shift2, \
109 .hw.init = &(struct clk_init_data){ \
110 .ops = &clk_double_div_ops, \
111 } \
112};
113
114#define PERIPH_DIV(_name, _reg, _shift, _table) \
115struct clk_divider rate_##_name = { \
116 .reg = (void *)_reg, \
117 .table = _table, \
118 .shift = _shift, \
119 .hw.init = &(struct clk_init_data){ \
120 .ops = &clk_divider_ro_ops, \
121 } \
122};
123
124#define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\
125static PERIPH_GATE(_name, _bit); \
126static PERIPH_MUX(_name, _shift); \
127static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
128
129#define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \
130static PERIPH_GATE(_name, _bit); \
131static PERIPH_MUX(_name, _shift); \
132static PERIPH_DIV(_name, _reg, _shift1, _table);
133
134#define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \
135static PERIPH_GATE(_name, _bit); \
136static PERIPH_DIV(_name, _reg, _shift, _table);
137
138#define PERIPH_CLK_MUX_DIV(_name, _shift, _reg, _shift_div, _table) \
139static PERIPH_MUX(_name, _shift); \
140static PERIPH_DIV(_name, _reg, _shift_div, _table);
141
142#define PERIPH_CLK_MUX_DD(_name, _shift, _reg1, _reg2, _shift1, _shift2)\
143static PERIPH_MUX(_name, _shift); \
144static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
145
146#define REF_CLK_FULL(_name) \
147 { .name = #_name, \
148 .parent_names = (const char *[]){ "TBG-A-P", \
149 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
150 .num_parents = 4, \
151 .mux_hw = &mux_##_name.hw, \
152 .gate_hw = &gate_##_name.hw, \
153 .rate_hw = &rate_##_name.hw, \
154 }
155
156#define REF_CLK_FULL_DD(_name) \
157 { .name = #_name, \
158 .parent_names = (const char *[]){ "TBG-A-P", \
159 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
160 .num_parents = 4, \
161 .mux_hw = &mux_##_name.hw, \
162 .gate_hw = &gate_##_name.hw, \
163 .rate_hw = &rate_##_name.hw, \
164 .is_double_div = true, \
165 }
166
167#define REF_CLK_GATE(_name, _parent_name) \
168 { .name = #_name, \
169 .parent_names = (const char *[]){ _parent_name}, \
170 .num_parents = 1, \
171 .gate_hw = &gate_##_name.hw, \
172 }
173
174#define REF_CLK_GATE_DIV(_name, _parent_name) \
175 { .name = #_name, \
176 .parent_names = (const char *[]){ _parent_name}, \
177 .num_parents = 1, \
178 .gate_hw = &gate_##_name.hw, \
179 .rate_hw = &rate_##_name.hw, \
180 }
181
182#define REF_CLK_MUX_DIV(_name) \
183 { .name = #_name, \
184 .parent_names = (const char *[]){ "TBG-A-P", \
185 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
186 .num_parents = 4, \
187 .mux_hw = &mux_##_name.hw, \
188 .rate_hw = &rate_##_name.hw, \
189 }
190
191#define REF_CLK_MUX_DD(_name) \
192 { .name = #_name, \
193 .parent_names = (const char *[]){ "TBG-A-P", \
194 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
195 .num_parents = 4, \
196 .mux_hw = &mux_##_name.hw, \
197 .rate_hw = &rate_##_name.hw, \
198 .is_double_div = true, \
199 }
200
201
202PERIPH_CLK_FULL_DD(mmc, 2, 0, DIV_SEL2, DIV_SEL2, 16, 13);
203PERIPH_CLK_FULL_DD(sata_host, 3, 2, DIV_SEL2, DIV_SEL2, 10, 7);
204PERIPH_CLK_FULL_DD(sec_at, 6, 4, DIV_SEL1, DIV_SEL1, 3, 0);
205PERIPH_CLK_FULL_DD(sec_dap, 7, 6, DIV_SEL1, DIV_SEL1, 9, 6);
206PERIPH_CLK_FULL_DD(tscem, 8, 8, DIV_SEL1, DIV_SEL1, 15, 12);
207PERIPH_CLK_FULL(tscem_tmx, 10, 10, DIV_SEL1, 18, clk_table6);
208static PERIPH_GATE(avs, 11);
209PERIPH_CLK_FULL_DD(pwm, 13, 14, DIV_SEL0, DIV_SEL0, 3, 0);
210PERIPH_CLK_FULL_DD(sqf, 12, 12, DIV_SEL1, DIV_SEL1, 27, 24);
211static PERIPH_GATE(i2c_2, 16);
212static PERIPH_GATE(i2c_1, 17);
213PERIPH_CLK_GATE_DIV(ddr_phy, 19, DIV_SEL0, 18, clk_table2);
214PERIPH_CLK_FULL_DD(ddr_fclk, 21, 16, DIV_SEL0, DIV_SEL0, 15, 12);
215PERIPH_CLK_FULL(trace, 22, 18, DIV_SEL0, 20, clk_table6);
216PERIPH_CLK_FULL(counter, 23, 20, DIV_SEL0, 23, clk_table6);
217PERIPH_CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19);
218PERIPH_CLK_MUX_DIV(cpu, 22, DIV_SEL0, 28, clk_table6);
219
220static struct clk_periph_data data_nb[] ={
221 REF_CLK_FULL_DD(mmc),
222 REF_CLK_FULL_DD(sata_host),
223 REF_CLK_FULL_DD(sec_at),
224 REF_CLK_FULL_DD(sec_dap),
225 REF_CLK_FULL_DD(tscem),
226 REF_CLK_FULL(tscem_tmx),
227 REF_CLK_GATE(avs, "xtal"),
228 REF_CLK_FULL_DD(sqf),
229 REF_CLK_FULL_DD(pwm),
230 REF_CLK_GATE(i2c_2, "xtal"),
231 REF_CLK_GATE(i2c_1, "xtal"),
232 REF_CLK_GATE_DIV(ddr_phy, "TBG-A-S"),
233 REF_CLK_FULL_DD(ddr_fclk),
234 REF_CLK_FULL(trace),
235 REF_CLK_FULL(counter),
236 REF_CLK_FULL_DD(eip97),
237 REF_CLK_MUX_DIV(cpu),
238 { },
239};
240
241
242PERIPH_CLK_MUX_DD(gbe_50, 6, DIV_SEL2, DIV_SEL2, 6, 9);
243PERIPH_CLK_MUX_DD(gbe_core, 8, DIV_SEL1, DIV_SEL1, 18, 21);
244PERIPH_CLK_MUX_DD(gbe_125, 10, DIV_SEL1, DIV_SEL1, 6, 9);
245static PERIPH_GATE(gbe1_50, 0);
246static PERIPH_GATE(gbe0_50, 1);
247static PERIPH_GATE(gbe1_125, 2);
248static PERIPH_GATE(gbe0_125, 3);
249PERIPH_CLK_GATE_DIV(gbe1_core, 4, DIV_SEL1, 13, clk_table1);
250PERIPH_CLK_GATE_DIV(gbe0_core, 5, DIV_SEL1, 14, clk_table1);
251PERIPH_CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, clk_table1);
252PERIPH_CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6);
253PERIPH_CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12);
254PERIPH_CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18);
255
256static struct clk_periph_data data_sb[] = {
257 REF_CLK_MUX_DD(gbe_50),
258 REF_CLK_MUX_DD(gbe_core),
259 REF_CLK_MUX_DD(gbe_125),
260 REF_CLK_GATE(gbe1_50, "gbe_50"),
261 REF_CLK_GATE(gbe0_50, "gbe_50"),
262 REF_CLK_GATE(gbe1_125, "gbe_125"),
263 REF_CLK_GATE(gbe0_125, "gbe_125"),
264 REF_CLK_GATE_DIV(gbe1_core, "gbe_core"),
265 REF_CLK_GATE_DIV(gbe0_core, "gbe_core"),
266 REF_CLK_GATE_DIV(gbe_bm, "gbe_core"),
267 REF_CLK_FULL_DD(sdio),
268 REF_CLK_FULL_DD(usb32_usb2_sys),
269 REF_CLK_FULL_DD(usb32_ss_sys),
270 { },
271};
272
273static unsigned int get_div(void __iomem *reg, int shift)
274{
275 u32 val;
276
277 val = (readl(reg) >> shift) & 0x7;
278 if (val > 6)
279 return 0;
280 return val;
281}
282
283static unsigned long clk_double_div_recalc_rate(struct clk_hw *hw,
284 unsigned long parent_rate)
285{
286 struct clk_double_div *double_div = to_clk_double_div(hw);
287 unsigned int div;
288
289 div = get_div(double_div->reg1, double_div->shift1);
290 div *= get_div(double_div->reg2, double_div->shift2);
291
292 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
293}
294
295static const struct clk_ops clk_double_div_ops = {
296 .recalc_rate = clk_double_div_recalc_rate,
297};
298
299static const struct of_device_id armada_3700_periph_clock_of_match[] = {
300 { .compatible = "marvell,armada-3700-periph-clock-nb",
301 .data = data_nb, },
302 { .compatible = "marvell,armada-3700-periph-clock-sb",
303 .data = data_sb, },
304 { }
305};
306static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
307 void __iomem *reg, spinlock_t *lock,
308 struct device *dev, struct clk_hw **hw)
309{
310 const struct clk_ops *mux_ops = NULL, *gate_ops = NULL,
311 *rate_ops = NULL;
312 struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *rate_hw = NULL;
313
314 if (data->mux_hw) {
315 struct clk_mux *mux;
316
317 mux_hw = data->mux_hw;
318 mux = to_clk_mux(mux_hw);
319 mux->lock = lock;
320 mux_ops = mux_hw->init->ops;
321 mux->reg = reg + (u64)mux->reg;
322 }
323
324 if (data->gate_hw) {
325 struct clk_gate *gate;
326
327 gate_hw = data->gate_hw;
328 gate = to_clk_gate(gate_hw);
329 gate->lock = lock;
330 gate_ops = gate_hw->init->ops;
331 gate->reg = reg + (u64)gate->reg;
332 gate->flags = CLK_GATE_SET_TO_DISABLE;
333 }
334
335 if (data->rate_hw) {
336 rate_hw = data->rate_hw;
337 rate_ops = rate_hw->init->ops;
338 if (data->is_double_div) {
339 struct clk_double_div *rate;
340
341 rate = to_clk_double_div(rate_hw);
342 rate->reg1 = reg + (u64)rate->reg1;
343 rate->reg2 = reg + (u64)rate->reg2;
344 } else {
345 struct clk_divider *rate = to_clk_divider(rate_hw);
346 const struct clk_div_table *clkt;
347 int table_size = 0;
348
349 rate->reg = reg + (u64)rate->reg;
350 for (clkt = rate->table; clkt->div; clkt++)
351 table_size++;
352 rate->width = order_base_2(table_size);
353 rate->lock = lock;
354 }
355 }
356
357 *hw = clk_hw_register_composite(dev, data->name, data->parent_names,
358 data->num_parents, mux_hw,
359 mux_ops, rate_hw, rate_ops,
360 gate_hw, gate_ops, CLK_IGNORE_UNUSED);
361
362 if (IS_ERR(*hw))
363 return PTR_ERR(*hw);
364
365 return 0;
366}
367
368static int armada_3700_periph_clock_probe(struct platform_device *pdev)
369{
370 struct clk_periph_driver_data *driver_data;
371 struct device_node *np = pdev->dev.of_node;
372 const struct clk_periph_data *data;
373 struct device *dev = &pdev->dev;
374 int num_periph = 0, i, ret;
375 struct resource *res;
376 void __iomem *reg;
377
378 data = of_device_get_match_data(dev);
379 if (!data)
380 return -ENODEV;
381
382 while (data[num_periph].name)
383 num_periph++;
384
385 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
386 reg = devm_ioremap_resource(dev, res);
387 if (IS_ERR(reg))
388 return PTR_ERR(reg);
389
390 driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL);
391 if (!driver_data)
392 return -ENOMEM;
393
394 driver_data->hw_data = devm_kzalloc(dev, sizeof(*driver_data->hw_data) +
395 sizeof(*driver_data->hw_data->hws) * num_periph,
396 GFP_KERNEL);
397 if (!driver_data->hw_data)
398 return -ENOMEM;
399 driver_data->hw_data->num = num_periph;
400
401 spin_lock_init(&driver_data->lock);
402
403 for (i = 0; i < num_periph; i++) {
404 struct clk_hw **hw = &driver_data->hw_data->hws[i];
405
406 if (armada_3700_add_composite_clk(&data[i], reg,
407 &driver_data->lock, dev, hw))
408 dev_err(dev, "Can't register periph clock %s\n",
409 data[i].name);
410
411 }
412
413 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
414 driver_data->hw_data);
415 if (ret) {
416 for (i = 0; i < num_periph; i++)
417 clk_hw_unregister(driver_data->hw_data->hws[i]);
418 return ret;
419 }
420
421 platform_set_drvdata(pdev, driver_data);
422 return 0;
423}
424
425static int armada_3700_periph_clock_remove(struct platform_device *pdev)
426{
427 struct clk_periph_driver_data *data = platform_get_drvdata(pdev);
428 struct clk_hw_onecell_data *hw_data = data->hw_data;
429 int i;
430
431 of_clk_del_provider(pdev->dev.of_node);
432
433 for (i = 0; i < hw_data->num; i++)
434 clk_hw_unregister(hw_data->hws[i]);
435
436 return 0;
437}
438
439static struct platform_driver armada_3700_periph_clock_driver = {
440 .probe = armada_3700_periph_clock_probe,
441 .remove = armada_3700_periph_clock_remove,
442 .driver = {
443 .name = "marvell-armada-3700-periph-clock",
444 .of_match_table = armada_3700_periph_clock_of_match,
445 },
446};
447
448builtin_platform_driver(armada_3700_periph_clock_driver);
449
